Xilinx AXI JTAG Demo

Remotely control FPGA-based AXI buses. This repository hosts the source code for a simple application showcasing an implementation for issuing remotely read and write commands on an AXI4 bus using a TCP socket.

📝 Note:

Only Digilent Arty A7 FPGA boards are supported.

Quick Start

Configuring the FPGA

First thing is to build a bitstream (aka FPGA configuration file) embedding the required IP cores. The Makefile file present in the root directory provides a default targets which builds the required bitstream and loads it into an Arty A7 hooked on the host.

$ make

Launching the AXI Transaction Server

$ ./jam-demo-server/run_server

Running Commands

$ nc 127.0.0.1 9900
version
2020.1
read C0000000 1
read @0xC0000000: 0x00000000
write C0000000 cafedeca
write @0xC0000000: 0xcafedeca
read C0000000 1
read @0xC0000000: 0xcafedeca
quit

Supported commands:

• version
• read
• write
• quit

FPGA Firmware

This demonstration requires the targeted FPGA to be configured with a bitstream instantiating the jtag_axi IP core.

Such bitstream can be built for the Digilent Arty A7 FPGA board using the project located in the jam-demo-firmware/ directory.