Skip to content

A simple bank system done with verlilog then converted into C

Notifications You must be signed in to change notification settings

Manar20575/Architecture-Project

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

23 Commits
 
 
 
 
 
 
 
 

Repository files navigation

Architecture-Project

Implementing an embedded system inside a bank which monitors the clients queue in front of the tellers. Monitoring was divided into calculating number of people waiting in the queue, and displaying the expected waiting time for each client in the queue, and the maximum number of clients in the queue. The system was simulated using ModelSim, and coded using Verilog.

Team members

Menna Omran, Manar Hamada and Mona Hamdy

For more details Check :

https://drive.google.com/file/d/1xx4a9fX1Fn299bipuKdIKXZUUrTjWjCC/view?usp=sharing

About

A simple bank system done with verlilog then converted into C

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published