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debug sdcard ready after reset test #766
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Paul Gardner-Stephen committed Mar 2, 2024
1 parent 15aa99e commit eba43fb
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Showing 3 changed files with 11 additions and 3 deletions.
4 changes: 4 additions & 0 deletions src/vhdl/sdcard.vhdl
Original file line number Diff line number Diff line change
Expand Up @@ -326,6 +326,8 @@ begin
sclkPhaseTimer_v := 0; -- Don't delay the initialization right after reset.
busy_o <= '1'; -- Busy while the SD card interface is being initialized.

report "SDCARD: reset_i asserted";

elsif sclkPhaseTimer_v /= 0 then
-- Setting the clock phase timer to a non-zero value delays any further actions
-- and generates the slower SPI clock from the faster master clock.
Expand Down Expand Up @@ -354,6 +356,8 @@ begin

busy_o <= '1'; -- Busy by default. Only false when waiting for R/W from host or stalled by error.

report "SDCARD: state_v = " & FsmState_t'image(state_v);

case state_v is

when START_INIT => -- Deselect the SD card and send it a bunch of clock pulses with MOSI high.
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2 changes: 1 addition & 1 deletion src/vhdl/sdcardio.vhdl
Original file line number Diff line number Diff line change
Expand Up @@ -1294,7 +1294,7 @@ begin -- behavioural
when x"80" =>
-- status / command register
-- error status in bit 6 so that V flag can be used for check
report "reading $D680 SDCARD status register" severity note;
-- report "reading $D680 SDCARD status register" severity note;
fastio_rdata(7) <= sd_interface_select_internal;
fastio_rdata(6) <= sdio_error;
fastio_rdata(5) <= sdio_fsm_error;
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8 changes: 6 additions & 2 deletions src/vhdl/tb_sdcard.vhdl
Original file line number Diff line number Diff line change
Expand Up @@ -183,20 +183,24 @@ begin
while test_suite loop

if run("SD card ready following RESET sequence") then

-- This sequence will cause sdcard.vhdl to begin its initialisation sequence.

reg_write(x"D3080",x"00"); -- assert RESET
reg_write(x"D3080",x"01"); -- release RESET

for i in 1 to 1000 loop
for i in 1 to 100000 loop
reg_read(x"D3080");
if fastio_rdata(1 downto 0) = "00" then
report "SD card reported READY after " & integer'image(i) & " cycles.";
exit;
end if;
end loop;
if fastio_rdata(1 downto 0) /= "00" then
assert false report "SD card was not READY following reset: sdcard_busy="
report "SD card was not READY following reset: sdcard_busy="
& std_logic'image(fastio_rdata(1)) & ", sdio_busy=" & std_logic'image(fastio_rdata(0));
reg_read(x"D309B");
assert false report "sdcard.vhdl FSM state = " & integer'image(to_integer(fastio_rdata));
end if;

end if;
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