make address widths correctly vary with RAM size #736

MEGA65 · Aug 13, 2024 · cac36c9 · cac36c9
1 parent b9994c3
commit cac36c9
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/src/vhdl/dpram8x4096.vhdl b/src/vhdl/dpram8x4096.vhdl
@@ -55,13 +55,13 @@ begin
       if ena = '1' then	
         for i in 0 to NB_COL-1 loop
           if wea(i) = '1' then
-            RAM(to_integer(unsigned(addra(11 downto 0))))((i+1)*COL_WIDTH-1 downto i*COL_WIDTH)	 := dina((i+1)*COL_WIDTH-1 downto i*COL_WIDTH);
+            RAM(to_integer(unsigned(addra((ADDR_WIDTH-1) downto 0))))((i+1)*COL_WIDTH-1 downto i*COL_WIDTH)	 := dina((i+1)*COL_WIDTH-1 downto i*COL_WIDTH);
           end if;			 
         end loop;
       end if;
     end if;
     if ena = '1' then	                  
-      douta <= RAM(to_integer(unsigned(addra(11 downto 0))));
+      douta <= RAM(to_integer(unsigned(addra((ADDR_WIDTH-1) downto 0))));
     else
       douta <= (others => 'Z');
     end if;
@@ -75,13 +75,13 @@ begin
       if enb = '1' then
         for i in 0 to NB_COL-1 loop
           if web(i) = '1' then
-            RAM(to_integer(unsigned(addrb(11 downto 0))))((i+1)*COL_WIDTH-1 downto i*COL_WIDTH)	 := dinb((i+1)*COL_WIDTH-1 downto i*COL_WIDTH);
+            RAM(to_integer(unsigned(addrb((ADDR_WIDTH-1) downto 0))))((i+1)*COL_WIDTH-1 downto i*COL_WIDTH)	 := dinb((i+1)*COL_WIDTH-1 downto i*COL_WIDTH);
             if silence_internal_drive='0' then
               report "1541RAM: Writing $" & to_hexstring(dinb) & " to address $" & to_hexstring(to_unsigned(to_integer(unsigned(addrb)),16));
             end if;
           end if;
         end loop;
-        doutb <= RAM(to_integer(unsigned(addrb(11 downto 0))));
+        doutb <= RAM(to_integer(unsigned(addrb((ADDR_WIDTH-1) downto 0))));
       end if;
     end if;
   end process;