use std_logic_vector for signal comparisons #768

MEGA65 · Jan 8, 2024 · b1eeaa4 · b1eeaa4
1 parent ef949f8
commit b1eeaa4
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Showing 5 changed files with 168 additions and 66 deletions.
diff --git a/src/vhdl/74LS165.vhdl b/src/vhdl/74LS165.vhdl
@@ -9,7 +9,7 @@ use work.cputypes.all;
 
 entity sim74LS165 is
   port (
-    q : in unsigned(7 downto 0);
+    q : in std_logic_vector(7 downto 0);
     ser : in std_logic;
     sh_ld_n : in std_logic;       -- latch sr into register
     clk : in std_logic;      -- shift register clock
@@ -21,7 +21,7 @@ end sim74LS165;
 
 architecture simulated of sim74LS165 is
 
-  signal sr : unsigned(7 downto 0);
+  signal sr : std_logic_vector(7 downto 0);
 
 begin
 

diff --git a/src/vhdl/74LS595.vhdl b/src/vhdl/74LS595.vhdl
@@ -10,7 +10,7 @@ use work.cputypes.all;
 entity sim74LS595 is
   generic ( unit : integer := 999);
   port (
-    q : out unsigned(7 downto 0);
+    q : out std_logic_vector(7 downto 0);
     ser : in std_logic;
     g_n : in std_logic;       -- Gate, i.e., oe_n
     rclk : in std_logic;       -- latch sr into register
@@ -22,8 +22,8 @@ end sim74LS595;
 
 architecture simulated of sim74LS595 is
 
-  signal sr : unsigned(7 downto 0);
-  signal q_int : unsigned(7 downto 0);
+  signal sr : std_logic_vector(7 downto 0);
+  signal q_int : std_logic_vector(7 downto 0);
 
 begin
 

diff --git a/src/vhdl/exp_board_serial_rings.vhdl b/src/vhdl/exp_board_serial_rings.vhdl
@@ -40,9 +40,9 @@ entity exp_board_ring_ctrl is
     c1565_rst_o : in std_logic;
 
     -- User port
-    user_d_i : out unsigned(7 downto 0);
-    user_d_o : in unsigned(7 downto 0);
-    user_d_en_n : in unsigned(7 downto 0);
+    user_d_i : out std_logic_vector(7 downto 0);
+    user_d_o : in std_logic_vector(7 downto 0);
+    user_d_en_n : in std_logic_vector(7 downto 0);
 
     user_pa2_o : out std_logic;
     user_sp1_o : out std_logic;

diff --git a/src/vhdl/sim_exp_board_rings.vhdl b/src/vhdl/sim_exp_board_rings.vhdl
@@ -30,9 +30,9 @@ entity sim_exp_board_rings is
     c1565_rst_o : out std_logic;
 
     -- User port
-    user_d_i : in unsigned(7 downto 0);
-    user_d_o : out unsigned(7 downto 0);
-    user_d_en_n : out unsigned(7 downto 0);
+    user_d_i : in std_logic_vector(7 downto 0);
+    user_d_o : out std_logic_vector(7 downto 0);
+    user_d_en_n : out std_logic_vector(7 downto 0);
 
     user_pa2_i : in std_logic;
     user_sp1_i : in std_logic;