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begin implementing test harness for SD card #766
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Paul Gardner-Stephen
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Jan 24, 2024
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
use Std.TextIO.all; | ||
use work.debugtools.all; | ||
use work.cputypes.all; | ||
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library vunit_lib; | ||
context vunit_lib.vunit_context; | ||
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entity tb_sdcard is | ||
generic (runner_cfg : string); | ||
end entity; | ||
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architecture test_arch of tb_sdcard is | ||
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signal pixelclock : std_logic := '0'; | ||
signal clock41 : std_logic := '0'; | ||
signal clock162 : std_logic := '0'; | ||
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signal reset : std_logic := '0'; | ||
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signal fastio_addr : unsigned(19 downto 0); | ||
signal fastio_waddr : unsigned(7 downto 0); | ||
signal fastio_raddr : unsigned(7 downto 0); | ||
signal fastio_read : std_logic := '0'; | ||
signal fastio_write : std_logic := '0'; | ||
signal cs : std_logic := '0'; | ||
signal sector_cs : std_logic := '0'; | ||
signal sector_cs_fast : std_logic := '0'; | ||
signal sd_bus_number : std_logic := '0'; | ||
signal cs_bo : std_logic := '0'; | ||
signal sckl_o : std_logic := '0'; | ||
signal mosi_o : std_logic := '0'; | ||
signal miso_i : std_logic := '0'; | ||
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begin | ||
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sdcard_controller0: entity work.sdcardio | ||
generic map ( target => simulation, | ||
cpu_freq => 40_500_000, | ||
cache_size => 128 ) -- 128 sectors = 64KB | ||
port map ( clock => clock41, | ||
pixelclk => pixelclock, | ||
reset => reset, | ||
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------------------------------------------------------------------------- | ||
-- Fastio register access interface | ||
------------------------------------------------------------------------- | ||
fastio_addr => fastio_addr, | ||
fastio_addr_fast => fastio_addr, | ||
fastio_write => fastio_write, | ||
fastio_read => fastio_read, | ||
fastio_wdata => fastio_wdata, | ||
fastio_rdata_sel => fastio_rdata, | ||
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sdcardio_cs => cs, | ||
colourram_at_dc00 => '0', | ||
viciii_iomode => "11", | ||
sectorbuffercs => sector_cs, | ||
sectorbuffercs_fast => sector_cs_fast, | ||
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------------------------------------------------------------------------- | ||
-- Lines for the SDcard interface itself | ||
------------------------------------------------------------------------- | ||
sd_interface_select => sd_bus_number, | ||
cs_bo => cs_bo, | ||
sclk_o => sckl_o, | ||
mosi_o => mosi_o, | ||
miso_i => miso_i, | ||
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------------------------------------------------------------------------- | ||
-- Other inputs to sdcardio.vhdl that are not relevant | ||
------------------------------------------------------------------------- | ||
f011_cs => '0', | ||
hw_errata_disable_toggle => '0', | ||
hw_errata_enable_toggle => '0', | ||
audio_loopback => (others => '0'); | ||
hypervisor_mode => '0', | ||
secure_mode => '0', | ||
fpga_temperature => (others => '0'), | ||
pwm_knob => (others => '0'), | ||
virtualise_f011_drive0 => '0', | ||
virtualise_f011_drive1 => '0', | ||
last_scan_code => (others => '0'), | ||
dipsw_hi => (others => '0'), | ||
dipsw => (others => '0'), | ||
j21in => (others => '0'), | ||
sw => (others => '0'), | ||
btn => (others => '0'), | ||
f_index => '0', | ||
f_track0 => '0', | ||
f_writeprotect => '0', | ||
f_rdata => '0', | ||
f_diskchanged => '0', | ||
sd1541_request_toggle => '0', | ||
sd1541_enable => '0', | ||
sd1541_track => (others => '0'), | ||
aclMISO => '0', | ||
aclInt1 => '0', | ||
aclInt2 => '0', | ||
tmpSDA => '0', | ||
tmpSCL => '0', | ||
tmpInt => '0', | ||
tmpCT => '0', | ||
i2c1SDA => '0', | ||
i2c1SCL => '0', | ||
touchSDA => '0', | ||
touchSCL => '0', | ||
QspiDB_in => x"0" | ||
); | ||
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main : process | ||
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variable v : unsigned(15 downto 0); | ||
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procedure clock_tick is | ||
begin | ||
clock162 <= not clock162; | ||
if clock162 = '1' then | ||
pixelclock <= not pixelclock; | ||
if pixelclock='1' then | ||
check_sdram_read_strobe; | ||
clock41 <= not clock41; | ||
end if; | ||
end if; | ||
wait for 6.173 ns; | ||
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end procedure; | ||
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begin | ||
test_runner_setup(runner, runner_cfg); | ||
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while test_suite loop | ||
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if run("SDcard responds to reset request") then | ||
assert false report "not implemented"; | ||
end if; | ||
end loop; | ||
test_runner_cleanup(runner); | ||
end process; | ||
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end architecture; |
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#!/bin/env python3 | ||
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from vunit import VUnit | ||
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# Create VUnit instance by parsing command line arguments | ||
vu = VUnit.from_argv(compile_builtins=False) | ||
vu.add_vhdl_builtins() | ||
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# Create library 'lib' | ||
lib = vu.add_library("lib") | ||
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lib.add_source_files("src/vhdl/tb_sdcard.vhdl"); | ||
lib.add_source_files("src/vhdl/debugtools.vhdl") | ||
lib.add_source_files("src/vhdl/cputypes.vhdl") | ||
lib.add_source_files("src/vhdl/victypes.vhdl") | ||
lib.add_source_files("src/vhdl/sdcardio.vhdl") | ||
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vu.set_compile_option("ghdl.a_flags", ["-frelaxed-rules","-fsynopsys"]) | ||
vu.set_sim_option("ghdl.elab_flags", ["-frelaxed-rules","-fsynopsys"]) | ||
vu.set_sim_option("ghdl.sim_flags", ["--ieee-asserts=disable"]) | ||
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# Run vunit function | ||
vu.main() |