v4.1.3

* HAL: Reference clock frequency error improvement: The lora_gateway HAL has
been updated (3 registers changed) to improve the performance of all gateways
based on SX130x. The fix greatly improves the reception of packet at SF12, when
the frequency offset of the incoming packet is large (mostly below -20ppm of
frequency offset).

WARNING: Systems which do not have the patch will be more prone to packet loss
over time, when the crystals of the end-devices will be ageing and have more
frequency offset.

VERSION

@@ -1 +1 @@
-4.1.2
+4.1.3

libloragw/src/loragw_hal.c

@@ -305,6 +305,11 @@ void lgw_constant_adjust(void) {
     // lgw_reg_w(LGW_MBWSSF_TRACKING_INTEGRAL,0); /* default 0 */
     // lgw_reg_w(LGW_MBWSSF_AGC_FREEZE_ON_DETECT,1); /* default 1 */
 
+    /* Improvement of reference clock frequency error tolerance */
+    lgw_reg_w(LGW_ADJUST_MODEM_START_OFFSET_RDX4, 1); /* default 0 */
+    lgw_reg_w(LGW_ADJUST_MODEM_START_OFFSET_SF12_RDX4, 4094); /* default 4092 */
+    lgw_reg_w(LGW_CORR_MAC_GAIN, 7); /* default 5 */
+
     /* FSK datapath setup */
     lgw_reg_w(LGW_FSK_RX_INVERT,1); /* default 0 */
     lgw_reg_w(LGW_FSK_MODEM_INVERT_IQ,1); /* default 0 */

readme.md

@@ -70,6 +70,18 @@ chip through GPIO, before starting any application using the concentrator.
 4. Changelog
 -------------
 
+### v4.1.3 ###
+
+* HAL: Reference clock frequency error improvement: The lora_gateway HAL has
+been updated (3 registers changed) to improve the performance of all gateways
+based on SX130x. The fix greatly improves the reception of packet at SF12, when
+the frequency offset of the incoming packet is large (mostly below -20ppm of
+frequency offset).
+
+WARNING: Systems which do not have the patch will be more prone to packet loss
+over time, when the crystals of the end-devices will be ageing and have more
+frequency offset.
+
 ### v4.1.2 ###
 
 * HAL: Changed configuration of IQ polarity of FPGA for TX to comply with FPGA