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1. Hdl_Bits Hdl_Bits Public

   The answers to the Verilog questions on the site https://hdlbits.01xz.net/wiki/Main_Page.

   Verilog

2. Sky130_PDK_INV_VTC Sky130_PDK_INV_VTC Public

   Creating vtc for an inverter in xschem utilizing sky 130 pdk pfets and nfets with variable W factor to observe how it affects the inverter's switching point.

3. Enhanced-S-DES-as-RNG-for-stream-cipher-VLSI-implementation-using-Opensource-tools Enhanced-S-DES-as-RNG-for-stream-cipher-VLSI-implementation-using-Opensource-tools Public

   Enhanced version of S-DES algorithm modified to be used as a random number generator to make a stream cipher the project completed the VLSI flow with only Opensource software's.

   Python

4. RRISC-V-32I-RTL RRISC-V-32I-RTL Public

   RISC_V 32bit Integer instruction computer architecture RTL using HDL

   Verilog

5. esp8266-UDP-to-FM-PWM-pin- esp8266-UDP-to-FM-PWM-pin- Public

   Experimental approach to send audio data to ESP using UDP protocol and using PWM pin for FM modulation for transmission.

   C++

6. Uart-Protocol-RTL Uart-Protocol-RTL Public

   8bit - UART protocol

   SystemVerilog