My projects in the Computer Architecture and Prediction Mechanisms courses at UT Austin.

Arm Instruction Emulator

AArch64 instruction subset emulator. Supports 20 instructions.

C-Routines

API for communicating sequential processes (CSP) called c-routines.

Instruction Pipelining

Pipelined cpu architecture with word addressable memory in verilog.

Malloc/Free

Malloc/Free using a linked list representation of memory blocks.

Optimized Arm Instruction Emulator

Optimized AArch64 instruction subset emulator. 10x faster.

Single Cycle CPU

Single-cycle cpu architecture with byte addressable memory in verilog.

Branch Prediction

Instruction branch predictor logic to be used in ChampSim.

Cache Replacement

Cache replacement policies to be used in ChampSim.

Machine Learning Branch Prediction

Branch prediction using machine learning classifiers.