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4 add support for 64 bit register #5

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merged 3 commits into from
Apr 19, 2024
Merged

4 add support for 64 bit register #5

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caab441
Added support for 64 bit.
pellico Apr 16, 2024
002ee2d
Added :: in front of core to force to use external crate.
pellico Apr 16, 2024
af86cd1
Merge branch 'main' into 4-add-support-for-64-bit-register
pellico Apr 17, 2024
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1 change: 1 addition & 0 deletions src/rust_gen/xml2ir.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -97,6 +97,7 @@ fn get_register(reg: &svd::Register) -> Register {
.size
.expect("All registers shall have a defined size")
{
64 => BitSize::BIT64,
32 => BitSize::BIT32,
16 => BitSize::BIT16,
8 => BitSize::BIT8,
Expand Down
12 changes: 6 additions & 6 deletions templates/rust/common.tera
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@@ -1,8 +1,8 @@
/*
{{ir.license_text}}
*/
use core::convert::From;
use core::marker::PhantomData;
use ::core::convert::From;
use ::core::marker::PhantomData;

{% if tracing %}
#[cfg(feature = "tracing")]
Expand All @@ -22,7 +22,7 @@ pub(crate) mod sealed {
impl Access for R {}
impl Access for W {}
impl Access for RW {}
use core::ops::{BitAnd, BitAndAssign, BitOrAssign, Not, Shl, Shr};
use ::core::ops::{BitAnd, BitAndAssign, BitOrAssign, Not, Shl, Shr};

// It would be better with const fn
// waiting for RFC: const functions in traits #3490
Expand Down Expand Up @@ -346,16 +346,16 @@ where
#[cfg(not(feature="tracing"))]
{% endif -%}
unsafe {
core::arch::tricore::intrinsics::__ldmst(self.ptr as *mut u32, res.data, res.mask);
::core::arch::tricore::intrinsics::__ldmst(self.ptr as *mut u32, res.data, res.mask);
}

}
}

#[cfg(not(feature="tracing"))]
use core::arch::tricore::intrinsics::{__mfcr, __mtcr};
use ::core::arch::tricore::intrinsics::{__mfcr, __mtcr};
#[cfg(all(any(target_feature = "tc18", doc),not(feature="tracing")))]
use core::arch::tricore::intrinsics::{__mfdcr, __mtdcr};
use ::core::arch::tricore::intrinsics::{__mfdcr, __mtdcr};

/// Type of core special register of Aurix (CSFR)
pub struct RegCore<T: RegSpec, A: Access, const ADDR: u16> {
Expand Down
8 changes: 5 additions & 3 deletions templates/rust/macros.tera
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Expand Up @@ -5,6 +5,8 @@ u8
u16
{%- elif bit_size=="BIT32" -%}
u32
{%- elif bit_size=="BIT64" -%}
u64
{%- else -%}
Unsupported register size
{%- endif -%}
Expand Down Expand Up @@ -99,7 +101,7 @@ impl {{reg_struct_name}} {
{%- endfor %}
}
{% endif -%}
impl core::default::Default for {{reg_struct_name}} {
impl ::core::default::Default for {{reg_struct_name}} {
#[inline(always)]
fn default() -> {{reg_struct_name}} {
<crate::RegValueT::<{{reg_struct_name}}_SPEC> as RegisterValue<_>>::new({{reg.reset_value}})
Expand Down Expand Up @@ -159,8 +161,8 @@ pub fn {{cluster_func}}(self) -> [{{cluster_struct_path}};{{cluster.dim}}] {
#[doc = "{{cluster.description | svd_description_to_doc}}"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct {{ cluster_struct }}(pub(super) *mut u8);
unsafe impl core::marker::Send for {{ cluster_struct}} {}
unsafe impl core::marker::Sync for {{ cluster_struct }} {}
unsafe impl ::core::marker::Send for {{ cluster_struct}} {}
unsafe impl ::core::marker::Sync for {{ cluster_struct }} {}
impl {{cluster_struct}} {
{% for register_name,reg in cluster.registers -%}
{{self::register_func(types_mod=cluster_mod,reg=reg)}}
Expand Down
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