GitHub - Gonadeepika/Router_verification: Router 1 x3 is a Basic level Design of Wireless Fidelity Router Model • The top level consists of 4 blocks-3 FIFO{First In First Out Register) , 1 Register, 1 Synchroniser and 1 Control Block (FSM-Finite State Machine) • RTL and Testbench are coded in verilog and the waveforms are generated using Modelsim software. • The Synthesis was performed u

router_verification

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
.github/workflows		.github/workflows
Makefile		Makefile
README.md		README.md
dst_agent.sv		dst_agent.sv
dst_agt_config.sv		dst_agt_config.sv
dst_agt_top.sv		dst_agt_top.sv
dst_driver.sv		dst_driver.sv
dst_monitor.sv		dst_monitor.sv
dst_seqs.sv		dst_seqs.sv
dst_sequencer.sv		dst_sequencer.sv
dst_xtn.sv		dst_xtn.sv
router_env.sv		router_env.sv
router_env_config.sv		router_env_config.sv
router_fifo.sv		router_fifo.sv
router_fsm.sv		router_fsm.sv
router_if.sv		router_if.sv
router_pkg.sv		router_pkg.sv
router_reg.sv		router_reg.sv
router_scoreboard.sv		router_scoreboard.sv
router_sync.sv		router_sync.sv
router_tb.sv		router_tb.sv
router_top.sv		router_top.sv
router_virtual_seqs.sv		router_virtual_seqs.sv
router_virtual_sequencer.sv		router_virtual_sequencer.sv
router_vtest_lib.sv		router_vtest_lib.sv
src_agent.sv		src_agent.sv
src_agt_config.sv		src_agt_config.sv
src_agt_top.sv		src_agt_top.sv
src_drivr.sv		src_drivr.sv
src_monitor.sv		src_monitor.sv
src_seqs.sv		src_seqs.sv
src_sequencer.sv		src_sequencer.sv
src_xtn.sv		src_xtn.sv
tags		tags
top.sv		top.sv

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