Add memory protection support to RISC-V port #1175
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Related to FreeRTOS#908 Add memory protection support to the RISC-V port. * **Memory Protection Configurations and Settings** - Add memory protection-related configurations and settings in `portable/GCC/RISC-V/portmacro.h` and `portable/IAR/RISC-V/portmacro.h`. - Define macros for enabling and disabling memory protection in both files. * **Critical Section Handling** - Update the `portENTER_CRITICAL` and `portEXIT_CRITICAL` macros in `portable/GCC/RISC-V/portmacro.h` and `portable/IAR/RISC-V/portmacro.h` to handle memory protection. * **Chip-Specific Extensions** - Add memory protection-related definitions and macros in `portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h` and `portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h`. - Define macros for saving and restoring memory protection context in both files. * **Port Functions** - Add functions for enabling and disabling memory protection in `portable/GCC/RISC-V/port.c` and `portable/IAR/RISC-V/port.c`. Working on still: portASM.s planning to implement ASAP
* Add `portcontextSAVE_CONTEXT_INTERNAL` macro to save memory protection context * Add `portcontextRESTORE_CONTEXT` macro to restore memory protection context
* Add `portcontextSAVE_CONTEXT_INTERNAL` macro to save memory protection context * Add `portcontextRESTORE_CONTEXT` macro to restore memory protection context
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Hi @vishwamartur, Thank you for your time and effort. |
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I have changed this PR to draft. Please mark it ready when you are done with the changes. Please also include the details about how are you testing these changes. |
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Thank you for the feedback and support! I haven’t conducted testing yet, as I don’t currently have access to a compatible platform for this setup. If there are any suggestions for a testing approach or available emulators that support memory protection configurations for RISC-V, please let me know, and I’ll be glad to proceed accordingly. Thanks again for your guidance! |
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For RISC-V, you can try using this QEmu demo - https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS/Demo/RISC-V-Qemu-virt_GCC. If you do not have a platform to test, how are you developing these changes? |
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@vishwamartur Please share the testing details. Would you also share the details about how you developed these changes. |
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As I have not heard back, I am closing this PR. Please feel free to create a new one when you are ready with the changes. |
Related to #908
Add memory protection support to the RISC-V port.
Memory Protection Configurations and Settings
portable/GCC/RISC-V/portmacro.handportable/IAR/RISC-V/portmacro.h.Critical Section Handling
portENTER_CRITICALandportEXIT_CRITICALmacros inportable/GCC/RISC-V/portmacro.handportable/IAR/RISC-V/portmacro.hto handle memory protection.Chip-Specific Extensions
portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.handportable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h.Port Functions
portable/GCC/RISC-V/port.candportable/IAR/RISC-V/port.c.Working on still: portASM.s planning to implement ASAP