align MPU regions to their size

FOME-Tech · Jan 23, 2025 · e957fa3 · e957fa3
1 parent 8ab08d2
commit e957fa3
Show file tree

Hide file tree

Showing 4 changed files with 10 additions and 9 deletions.
diff --git a/firmware/global.h b/firmware/global.h
@@ -65,24 +65,25 @@ typedef unsigned int time_t;
 #define CCM_OPTIONAL __attribute__((section(".ram4")))
 #define SDRAM_OPTIONAL __attribute__((section(".ram7")))
 #define NO_CACHE		// F4 has no cache, do nothing
-#define SDMMC_MEMORY	// F4 has no cache, do nothing
+#define SDMMC_MEMORY(size)	// F4 has no cache, do nothing
 #elif defined(STM32F7XX)
 // DTCM memory is 128k
 #define CCM_OPTIONAL __attribute__((section(".ram3")))
 //TODO: update LD file!
 #define SDRAM_OPTIONAL __attribute__((section(".ram7")))
 // SRAM2 is 16k and set to disable dcache
 #define NO_CACHE __attribute__((section(".ram2")))
-#define SDMMC_MEMORY NO_CACHE
+#define SDMMC_MEMORY(size) NO_CACHE
 #elif defined(STM32H7XX)
 // DTCM memory is 128k
 #define CCM_OPTIONAL __attribute__((section(".ram5")))
 //TODO: update LD file!
 #define SDRAM_OPTIONAL __attribute__((section(".ram8")))
 // SRAM3 is 32k and set to disable dcache
 #define NO_CACHE __attribute__((section(".ram3")))
-// On H7, SDMMC1 can only talk to AXI, and aligned to a cache line (32 bytes)
-#define SDMMC_MEMORY __attribute__((section(".ram0"))) __attribute__ ((aligned (32)))
+// On H7, SDMMC1 can only talk to AXI, and aligned to the size of the
+// object, so its MPU region can disable caching
+#define SDMMC_MEMORY(size) __attribute__((section(".ram0")))  __attribute__ ((aligned (size)))
 #else /* this MCU doesn't need these */
 #define CCM_OPTIONAL
 #define NO_CACHE

diff --git a/firmware/hw_layer/mass_storage/mass_storage_init.cpp b/firmware/hw_layer/mass_storage/mass_storage_init.cpp
@@ -40,7 +40,7 @@
 
 // One block buffer per LUN
 static NO_CACHE uint8_t blkbufIni[MMCSD_BLOCK_SIZE];
-static SDMMC_MEMORY uint8_t blkbufSdmmc[MMCSD_BLOCK_SIZE];
+static SDMMC_MEMORY(MMCSD_BLOCK_SIZE) uint8_t blkbufSdmmc[MMCSD_BLOCK_SIZE];
 
 static CCM_OPTIONAL MassStorageController msd(usb_driver);
 
@@ -118,7 +118,7 @@ void initUsbMsd() {
 		static_assert(sizeof(blkbufSdmmc) == 512);
 		uint32_t size = MPU_RASR_SIZE_512;
 
-		mpuConfigureRegion(MPU_REGION_4,
+		mpuConfigureRegion(MPU_REGION_5,
 						base,
 						MPU_RASR_ATTR_AP_RW_RW |
 						MPU_RASR_ATTR_NON_CACHEABLE |

diff --git a/firmware/hw_layer/mmc_card.cpp b/firmware/hw_layer/mmc_card.cpp
@@ -96,7 +96,7 @@ struct {
 
 	// Fill the struct out to a full MPU region
 	uint8_t padding[2048 - sizeof(usedPart)];
-} mmcCardCacheControlledStorage SDMMC_MEMORY;
+} mmcCardCacheControlledStorage SDMMC_MEMORY(2048);
 
 static FATFS& MMC_FS = mmcCardCacheControlledStorage.usedPart.fs;
 static FIL& FDLogFile = mmcCardCacheControlledStorage.usedPart.file;
@@ -330,7 +330,7 @@ static BaseBlockDevice* initializeMmcBlockDevice() {
 		static_assert(sizeof(mmcCardCacheControlledStorage) == 2048);
 		uint32_t size = MPU_RASR_SIZE_2K;
 
-		mpuConfigureRegion(MPU_REGION_5,
+		mpuConfigureRegion(MPU_REGION_6,
 						base,
 						MPU_RASR_ATTR_AP_RW_RW |
 						MPU_RASR_ATTR_NON_CACHEABLE |

diff --git a/firmware/hw_layer/ports/stm32/stm32h7/cfg/mcuconf.h b/firmware/hw_layer/ports/stm32/stm32h7/cfg/mcuconf.h
@@ -53,7 +53,7 @@
 /*
  * Memory attributes settings.
  */
-#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_7
 #ifndef STM32_NOCACHE_SRAM1_SRAM2
 #define STM32_NOCACHE_SRAM1_SRAM2           FALSE
 #endif // STM32_NOCACHE_SRAM1_SRAM2