FOME-ize LSE max_wait patches

FOME-Tech · Jan 16, 2025 · 7ea171c · 7ea171c
1 parent abc1094
commit 7ea171c
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Showing 18 changed files with 81 additions and 81 deletions.
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c
@@ -68,7 +68,7 @@ static void hal_lld_backup_domain_init(void) {
 
   /* If enabled then the LSE is started.*/
 #if STM32_LSE_ENABLED
-  int rusefiLseCounter = 0;
+  int fomeLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
@@ -77,7 +77,7 @@ static void hal_lld_backup_domain_init(void) {
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
 #endif
   /* Waits until LSE is stable or times out. */
-  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+  while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
       && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
     ;
 #endif
@@ -88,7 +88,7 @@ static void hal_lld_backup_domain_init(void) {
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
 #if STM32_LSE_ENABLED
-    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
 #else
     RCC->BDCR |= STM32_RTCSEL;
 #endif

diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/os/hal/ports/STM32/STM32F0xx/hal_lld.h
@@ -374,20 +374,20 @@
 /**
  * @brief   Number of times to busy-loop waiting for LSE clock source.
  * @note    The default value of 0 disables this behavior.
- * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ * @note    See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX           0
 #endif
 
 /**
  * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
  * @note    If waiting for the LSE clock source times out due to
- *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
  *          fallback to another.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
 #endif
 
 /**

diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld.c b/os/hal/ports/STM32/STM32F1xx/hal_lld.c
@@ -66,7 +66,7 @@ static void hal_lld_backup_domain_init(void) {
 
   /* If enabled then the LSE is started.*/
 #if STM32_LSE_ENABLED
-  int rusefiLseCounter = 0;
+  int fomeLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
@@ -75,7 +75,7 @@ static void hal_lld_backup_domain_init(void) {
   RCC->BDCR |= RCC_BDCR_LSEON;
 #endif
   /* Waits until LSE is stable or times out. */
-  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+  while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
       && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
     ;
 #endif /* STM32_LSE_ENABLED */
@@ -86,7 +86,7 @@ static void hal_lld_backup_domain_init(void) {
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
 #if STM32_LSE_ENABLED
-    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
 #else
     RCC->BDCR |= STM32_RTCSEL;
 #endif

diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld.h b/os/hal/ports/STM32/STM32F1xx/hal_lld.h
@@ -176,20 +176,20 @@
 /**
  * @brief   Number of times to busy-loop waiting for LSE clock source.
  * @note    The default value of 0 disables this behavior.
- * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ * @note    See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX           0
 #endif
 
 /**
  * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
  * @note    If waiting for the LSE clock source times out due to
- *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
  *          fallback to another.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
 #endif
 /** @} */
 

diff --git a/os/hal/ports/STM32/STM32F37x/hal_lld.c b/os/hal/ports/STM32/STM32F37x/hal_lld.c
@@ -65,7 +65,7 @@ static void hal_lld_backup_domain_init(void) {
 
   /* If enabled then the LSE is started.*/
 #if STM32_LSE_ENABLED
-  int rusefiLseCounter = 0;
+  int fomeLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
@@ -74,7 +74,7 @@ static void hal_lld_backup_domain_init(void) {
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
 #endif
   /* Waits until LSE is stable or times out. */
-  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+  while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
       && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
     ;
 #endif
@@ -85,7 +85,7 @@ static void hal_lld_backup_domain_init(void) {
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
 #if STM32_LSE_ENABLED
-    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
 #else
     RCC->BDCR |= STM32_RTCSEL;
 #endif

diff --git a/os/hal/ports/STM32/STM32F37x/hal_lld.h b/os/hal/ports/STM32/STM32F37x/hal_lld.h
@@ -345,20 +345,20 @@
 /**
  * @brief   Number of times to busy-loop waiting for LSE clock source.
  * @note    The default value of 0 disables this behavior.
- * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ * @note    See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX           0
 #endif
 
 /**
  * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
  * @note    If waiting for the LSE clock source times out due to
- *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
  *          fallback to another.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
 #endif
 
 /**

diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.c b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
@@ -65,7 +65,7 @@ static void hal_lld_backup_domain_init(void) {
 
   /* If enabled then the LSE is started.*/
 #if STM32_LSE_ENABLED
-  int rusefiLseCounter = 0;
+  int fomeLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
@@ -74,7 +74,7 @@ static void hal_lld_backup_domain_init(void) {
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
 #endif
   /* Waits until LSE is stable or times out. */
-  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+  while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
       && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
     ;
 #endif
@@ -85,7 +85,7 @@ static void hal_lld_backup_domain_init(void) {
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
 #if STM32_LSE_ENABLED
-    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
 #else
     RCC->BDCR |= STM32_RTCSEL;
 #endif

diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.h b/os/hal/ports/STM32/STM32F3xx/hal_lld.h
@@ -385,20 +385,20 @@
 /**
  * @brief   Number of times to busy-loop waiting for LSE clock source.
  * @note    The default value of 0 disables this behavior.
- * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ * @note    See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX           0
 #endif
 
 /**
  * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
  * @note    If waiting for the LSE clock source times out due to
- *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
  *          fallback to another.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
 #endif
 
 /**

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -64,7 +64,7 @@ static void hal_lld_backup_domain_init(void) {
   }
 
 #if STM32_LSE_ENABLED
-  int rusefiLseCounter = 0;
+  int fomeLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
@@ -73,7 +73,7 @@ static void hal_lld_backup_domain_init(void) {
   RCC->BDCR |= RCC_BDCR_LSEON;
 #endif
   /* Waits until LSE is stable or times out. */
-  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+  while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
       && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
     ;
 #endif
@@ -84,7 +84,7 @@ static void hal_lld_backup_domain_init(void) {
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
 #if STM32_LSE_ENABLED
-    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
 #else
     RCC->BDCR |= STM32_RTCSEL;
 #endif

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
@@ -623,20 +623,20 @@
 /**
  * @brief   Number of times to busy-loop waiting for LSE clock source.
  * @note    The default value of 0 disables this behavior.
- * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ * @note    See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX           0
 #endif
 
 /**
  * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
  * @note    If waiting for the LSE clock source times out due to
- *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
  *          fallback to another.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
 #endif
 
 /**

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h
@@ -405,20 +405,20 @@
 /**
  * @brief   Number of times to busy-loop waiting for LSE clock source.
  * @note    The default value of 0 disables this behavior.
- * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ * @note    See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX           0
 #endif
 
 /**
  * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
  * @note    If waiting for the LSE clock source times out due to
- *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
  *          fallback to another.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
 #endif
 
 /**

diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
@@ -64,7 +64,7 @@ static void hal_lld_backup_domain_init(void) {
   }
 
 #if STM32_LSE_ENABLED
-  int rusefiLseCounter = 0;
+  int fomeLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
@@ -73,7 +73,7 @@ static void hal_lld_backup_domain_init(void) {
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
 #endif
   /* Waits until LSE is stable or times out. */
-  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+  while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
       && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
     ;
 #endif
@@ -84,7 +84,7 @@ static void hal_lld_backup_domain_init(void) {
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
 #if STM32_LSE_ENABLED
-    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
 #else
     RCC->BDCR |= STM32_RTCSEL;
 #endif

diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h
@@ -516,20 +516,20 @@
 /**
  * @brief   Number of times to busy-loop waiting for LSE clock source.
  * @note    The default value of 0 disables this behavior.
- * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ * @note    See also FOME_STM32_LSE_WAIT_MAX_RTCSEL.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#if !defined(FOME_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX           0
 #endif
 
 /**
  * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
  * @note    If waiting for the LSE clock source times out due to
- *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          FOME_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
  *          fallback to another.
  */
-#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
-#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#if !defined(FOME_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define FOME_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
 #endif
 
 /**

diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
@@ -64,7 +64,7 @@ static inline void init_bkp_domain(void) {
   }
 
 #if STM32_LSE_ENABLED
-  int rusefiLseCounter = 0;
+  int fomeLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
@@ -73,7 +73,7 @@ static inline void init_bkp_domain(void) {
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
 #endif
   /* Waits until LSE is stable or times out. */
-  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+  while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
       && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
     ;
 #endif
@@ -84,7 +84,7 @@ static inline void init_bkp_domain(void) {
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
 #if STM32_LSE_ENABLED
-    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
 #else
     RCC->BDCR |= STM32_RTCSEL;
 #endif

diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.c b/os/hal/ports/STM32/STM32L0xx/hal_lld.c
@@ -63,10 +63,10 @@ static void hal_lld_backup_domain_init(void) {
 
   /* If enabled then the LSE is started.*/
 #if STM32_LSE_ENABLED
-  int rusefiLseCounter = 0;
+  int fomeLseCounter = 0;
   RCC->CSR |= RCC_CSR_LSEON;
   /* Waits until LSE is stable or times out. */
-  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+  while ((!FOME_STM32_LSE_WAIT_MAX || fomeLseCounter++ < FOME_STM32_LSE_WAIT_MAX)
       && (RCC->CSR & RCC_CSR_LSERDY) == 0)
     ;
 #endif
@@ -78,7 +78,7 @@ static void hal_lld_backup_domain_init(void) {
     /* Selects clock source.*/
     RCC->CSR |= STM32_RTCSEL;
 #if STM32_LSE_ENABLED
-    RCC->CSR |= (RCC->CSR & RCC_CSR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+    RCC->CSR |= (RCC->CSR & RCC_CSR_LSERDY) == 0 ? FOME_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
 #else
     RCC->CSR |= STM32_RTCSEL;
 #endif