FPGA based Oscilloscope

Overview

It is intended to build an oscilloscope with hardware resource in FPGA involving the development of the following functionalities:

• Signal acquisition;
• Signal processing functions:
  • Low-Pass Filter (LP);
  • Band-Pass Filter (BP);
  • High-Pass Filter (HP);
• Graphic support through HDMI display, with hardware implemented controller.

Block Diagram

The Processor System (PS) block is responsible for configuring and initializing XADC. When the ADC is configured, a configuration flag must be activated, through the AXI Config slave register. In addition, PS allows debugging the main lines of the system, such as the value converted by XADC (ADC_Val) or the result of applying filters (Result), through the use of an AXI slave debug IP (Debug). The Read XADC block is an AXI-Lite master block that waits for the XADC to be configured by the PS and performs the respective readings to the ADC registers, putting it in the output (ADC_Val). The sampling frequency set for this system was 1 kHz and, since the XADC has a sampling frequency of 1 MHz, an IP was implemented that performs the average of the values converted by the XADC, in a sampling period (1 ms). The average value is cleaned at each sampling and this frequency is defined by the IP Sample These signals and the filter selection signal (filter_select) are used by the filter block (Filters) in order to apply the respective filter on the signal read by the XADC. The signal after applying the filter (result) enters the production block and image transmission via HDMI (HDMIIP). This block uses different clock sources for different tasks: clkRD is the frequency of reading the image into memory; clkWR to write the image to memory; Pixclk represents the reading frequency of a pixel of the image to be transmitted; TMDS_clk, defined by the HDMI protocol, represents the frequency at which HDMI signals are switched, as per the pixel read.

All IPs that use an AXI-Lite interface are connected to a bus IP, called AXI Interconnect, and all communications must be initiated, through the respective AXI protocol handshake, by an IP with an AXI-Lite interface master (AXI_M) which have mapped IP addresses with AXI-Liteslave interface (AXI_S).

Filter IP

HDMI IP

Below is shown the implemented system's block design in Vivado:

Results

LPF

Cut frequency at 50 Hz. Results as expected

20 Hz	50 Hz	100 Hz

HPF

Cut frequency at 50 Hz. Response not well defined in the passband (100 Hz)

20 Hz	50 Hz	100 Hz

BPF

Cut frequency at 50 Hz and 150 Hz. Results dont match expected - always on rejection band

20 Hz	50 Hz	100 Hz

Tools

• Xilinx Vivado 2019.02
• Xilinx Vivado HLS
• Xilinx Vitis 2019.02

Hardware

• Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board

Documentation

• Final report

Project tree

• code/: project sources
• doc/: documentation
• ext/: third-party software and development directory:
  • axi/: AXI-Lite test with vitis: write and read registers;
  • bram_read/: read test to bram;
  • write_read/: write test to bram;
  • dsp/: dsp latency test;
  • helloWorld/: test vitis application;
  • ips_tests/: tests developed for some ips:
    • axi_master_test/: AXI-Lite master to read and write from slave;
    • AXIM_read_xadc_1_test/: AXI-Lite master to read from slave continuously;
    • filters_test/: test filters ip;
    • test_average/: test average ip;
    • test_sample/: test sample ip;
    • test_average/: test average ip;
  • old_ips/: older versions of ips;
  • xadc/: test XADC with vitis application;
  • xadc_axi/: final application;
  • xadc_drp/: test XADC with DRP interface;
  • stm_manager/: STM manager Submodule
• ips/: IP's blocks developed for project:
  • average_ip/: IP to do average with the sampled values;
  • AXIM_read_xadc/: AXI-Lite Master that reads the XADC values;
  • config_done/: AXI-Lite Slave that holds the configuration registers;
  • debugIP/: AXI-Lite Slave allows debug system sugnals, using registers;
  • filtersIP/: IP that filters the digital signal;
  • hdmiIP/: IP that controlls and sends signals by HDMI interface;
  • sampleIP/: IP that makes the sample frequency;

Setup

Note that this repository has submodules. When in doubt, follow the next steps:

$ git clone [email protected]:ESRGgroup9/oscilloscope_fpga.git
$ cd oscilloscope_fpga/
$ git submodule update --init

If you use Vivado:

• Launch vivado;
• In TCL Console:
  • cd <repo_dir>/code;
  • source oscilloscope_fpga.tcl;

In order to debug the application:

• Program and Debug -> Generate Bitstream;
• File -> Export -> Export Hardware... (XSA) -> Include bitstream -> Ok;
• Tools -> Launch Vitis;
• Select workspace;
• Create Application Project...
• Give project a name (Oscilloscope_fpga);
• Create a new platform from hardware (XSA) -> Hit button plus '+' -> Select XSA generated previously;
• Select Empty application;
• Finish;
• Build;
• Run -> Run configurations -> Double click in Single Application Debug;
• Run the Apllication.

---

Directed by:

• Jorge Cabral
• Rui Machado
• Sofia Paiva

Done by:

• Tomás Abreu
• Diogo Fernandes

Engenharia Eletrónica Industrial e Computadores @ Universidade do Minho, 2022