[HLS Verifier] Verilog TB Gen. & Support for Verilator Simulation#696
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Jiahui17 merged 3 commits intoEPFL-LAP:mainfrom Jan 28, 2026
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[HLS Verifier] Verilog TB Gen. & Support for Verilator Simulation#696Jiahui17 merged 3 commits intoEPFL-LAP:mainfrom
Jiahui17 merged 3 commits intoEPFL-LAP:mainfrom
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tools/dynamatic/scripts/simulate.sh
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| cp "$RESOURCE_DIR/templates_verilog/template_two_port_RAM.v" "$COSIM_HDL_SRC_DIR/two_port_RAM.sv" | ||
| cp "$RESOURCE_DIR/templates_verilog/template_single_argument.v" "$COSIM_HDL_SRC_DIR/single_argument.sv" |
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Added testbenches in verilog
Added Verilator