Board Revision 1.2

Please share any observations to implement

Changes in this version:

Schematic

• Regrouped connectors to one side and cleaned up tracing
• Added pinout designators
• Added boxes for optional function groups
• Relabeled R1 and R2 for consistency on PCB
• Reversed J1 for PCB consistency
• Extended J4 for HC-06 BT-module direct connection - EN and State not in use yet
• Added standard ESP32 ICSP header. GPIO0 not connected because it's not broken put on the 30-pin dev board.
• R11 0R bridge not needed anymore - removed
• Added J9 external 5V power supply connector with reverse voltage protection
• Regrouped Favero interfaces - WIP! standard pinout has to be implemented, will be regrouped in 1 connector
• Resolved ERC errors
• Added net classes for easy PCB routing

PCB

• 2-sided layout - ground planes added, R11 removed
• Replaced pin headers with JST-XH footprints
• Regrouped the connectors to one side and placed them close to the exterior of the board
• Regrouped the resistors between the dev board pins.
• Added right angle connector for HC-06 direct connection. Board tugged away under the dev board to keep the design compact. WIP, not yet implemented.
• Tightened the component grouping to save space and shorten the traces
• Maximized trace width to 50mils for measuring circuits to cut down on trace resistance.
• Added ICSP connector. 3.3V, EN, Serial 0 broken out
• Added Gerber files for PCB production
• Cleaned up and completed the silkscreen. WIP, still some tweaks to complete

Caution

Polarity of J8 reversed compared to 1.0 and 1.1 for consistency on PCB. Usually you can swap the cables in your JST connector by using a needle.

Automatic repository changelog:
Full Changelog: Rev1.1-alpha...Rev1.2-alpha

Rev1.2-alpha

Please share any observations to implement

Changes in this version:

Schematic

• Regrouped connectors to one side and cleaned up tracing
• Added pinout designators
• Added boxes for optional function groups
• Relabeled R1 and R2 for consistency on PCB
• Reversed J1 for PCB consistency
• Extended J4 for HC-06 BT-module direct connection - EN and State not in use yet
• Added standard ESP32 ICSP header. GPIO0 not connected because it's not broken put on the 30-pin dev board.
• R11 0R bridge not needed anymore - removed
• Added J9 external 5V power supply connector with reverse voltage protection
• Regrouped Favero interfaces - WIP! standard pinout has to be implemented, will be regrouped in 1 connector
• Resolved ERC errors
• Added net classes for easy PCB routing

PCB

• 2-sided layout - ground planes added, R11 removed
• Replaced pin headers with JST-XH footprints
• Regrouped the connectors to one side and placed them close to the exterior of the board
• Regrouped the resistors between the dev board pins.
• Added right angle connector for HC-06 direct connection. Board tugged away under the dev board to keep the design compact. WIP, not yet implemented.
• Tightened the component grouping to save space and shorten the traces
• Maximized trace width to 50mils for measuring circuits to cut down on trace resistance.
• Added ICSP connector. 3.3V, EN, Serial 0 broken out
• Added Gerber files for PCB production
• Cleaned up and completed the silkscreen. WIP, still some tweaks to complete

Caution

Polarity of J8 reversed compared to 1.0 and 1.1 for consistency on PCB. Usually you can swap the cables in your JST connector by using a needle.

Automatic repository changelog:
Full Changelog: Rev1.1-alpha...Rev1.2-alpha

Rev. 1.1-alpha

Some major revisions to the PCB:

• changed to 2 sided layout. No cost difference for most board manufacturers and easier routing.
• ground planes on both sides, cleans up the design and makes R11 obsolete.
• rerouted all traces with 50mil width for more consistent resistance values.
• added Gerber files for direct upload to board manufacturer.
• cleaned up the silkscreens.

PCBs on order, design not proven or validated