Added analysis and added information to the README.md

Cbabe · Dec 18, 2021 · f597a0e · f597a0e
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diff --git a/16wide/design_analysis.log b/16wide/design_analysis.log
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+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+| Date         : Fri Dec 17 17:11:34 2021
+| Host         : gminer-linux running 64-bit Ubuntu 20.04.3 LTS
+| Command      : report_design_analysis -file design_analysis.log -verbose -show_all
+| Design       : SRAM
+| Device       : xc7a15t
+| Design State : Synthesized
+-------------------------------------------------------------------------------------
+
+Report Design Analysis
+
+Table of Contents
+-----------------
+1. Setup Path Characteristics 1-1
+
+1. Setup Path Characteristics 1-1
+---------------------------------
+
++---------------------------+-----------------------+
+|      Characteristics      |        Path #1        |
++---------------------------+-----------------------+
+| Requirement               | 4.000                 |
+| Path Delay                | 1.652                 |
+| Logic Delay               | 1.319(80%)            |
+| Net Delay                 | 0.333(20%)            |
+| Clock Skew                | -0.145                |
+| Slack                     | 2.104                 |
+| Timing Exception          |                       |
+| Bounding Box Size         | 0% x 0%               |
+| Clock Region Distance     | NA                    |
+| Fixed Loc                 | 0                     |
+| Fixed Route               | 0                     |
+| Hold Fix Detour           | 0                     |
+| Combined LUT Pairs        | 0                     |
+| Clock Relationship        | Safely Timed          |
+| Clock Group               | 1                     |
+| Logic Levels              | 0                     |
+| Routes                    | NA                    |
+| Logical Path              | RAMS32/CLK-(1)-FDRE/D |
+| Start Point Clock         | clk                   |
+| End Point Clock           | clk                   |
+| DSP Block                 | None                  |
+| BRAM                      | None                  |
+| IO Crossings              | 0                     |
+| Config Crossings          | 0                     |
+| SLR Crossings             | 0                     |
+| PBlocks                   | 0                     |
+| High Fanout               | 1                     |
+| Cumulative Fanout         | 1                     |
+| Dont Touch                | 0                     |
+| Mark Debug                | 0                     |
+| Start Point Pin Primitive | RAMS32/CLK            |
+| End Point Pin Primitive   | FDRE/D                |
+| Start Point Pin           | SP/CLK                |
+| End Point Pin             | dataOut_reg[0]/D      |
++---------------------------+-----------------------+
+* Bounding box calculated as % of dimensions for the target device (188, 300)
+
+
diff --git a/16wide/synthesis.checkpoint b/16wide/synthesis.checkpoint
diff --git a/16wide/timing.log b/16wide/timing.log
@@ -0,0 +1,34 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+| Date         : Fri Dec 17 17:11:34 2021
+| Host         : gminer-linux running 64-bit Ubuntu 20.04.3 LTS
+| Command      : report_timing -sort_by group -max_paths 100 -path_type summary -file timing.log -verbose
+| Design       : SRAM
+| Device       : 7a15t-cpg236
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+----------------------------------------------------------------------------------------------------------
+
+Timing Report
+
+Startpoint                     Endpoint                       Slack(ns)     
+----------------------------------------------------------------------------
+SRAM_reg_0_15_0_0/SP/CLK       dataOut_reg[0]/D               2.104         
+SRAM_reg_0_15_10_10/SP/CLK     dataOut_reg[10]/D              2.104         
+SRAM_reg_0_15_11_11/SP/CLK     dataOut_reg[11]/D              2.104         
+SRAM_reg_0_15_12_12/SP/CLK     dataOut_reg[12]/D              2.104         
+SRAM_reg_0_15_13_13/SP/CLK     dataOut_reg[13]/D              2.104         
+SRAM_reg_0_15_14_14/SP/CLK     dataOut_reg[14]/D              2.104         
+SRAM_reg_0_15_15_15/SP/CLK     dataOut_reg[15]/D              2.104         
+SRAM_reg_0_15_1_1/SP/CLK       dataOut_reg[1]/D               2.104         
+SRAM_reg_0_15_2_2/SP/CLK       dataOut_reg[2]/D               2.104         
+SRAM_reg_0_15_3_3/SP/CLK       dataOut_reg[3]/D               2.104         
+SRAM_reg_0_15_4_4/SP/CLK       dataOut_reg[4]/D               2.104         
+SRAM_reg_0_15_5_5/SP/CLK       dataOut_reg[5]/D               2.104         
+SRAM_reg_0_15_6_6/SP/CLK       dataOut_reg[6]/D               2.104         
+SRAM_reg_0_15_7_7/SP/CLK       dataOut_reg[7]/D               2.104         
+SRAM_reg_0_15_8_8/SP/CLK       dataOut_reg[8]/D               2.104         
+SRAM_reg_0_15_9_9/SP/CLK       dataOut_reg[9]/D               2.104         
+
+
+