simple description of the riscv softcore DE10Pro setup

Makefile

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+#LD       = riscv64-unknown-elf-ld
+LD       = ld.lld
+LDSCRIPT = script.ld
+
+all: devicetree.wrapped.elf
+
+%.dtb: %.dts
+	dtc $< -O dtb > $@
+
+%.wrapped.elf: %.dtb script.ld
+	$(LD) -o $@ -b binary -m elf64lriscv -T $(LDSCRIPT) $<
+
+.PHONY: clean
+clean:
+	rm -f *.dtb
+	rm -f *.wrapped.elf

devicetree.dts

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+/dts-v1/;
+
+/ {
+    #address-cells = <1>;
+    #size-cells = <1>;
+    compatible = "unknown,unknown";
+    model = "unknown,unknown";
+    chosen {
+        stdout-path = &ns16550;
+    };
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        timebase-frequency = <500000>;
+        CPU0: cpu@0 {
+            device_type = "cpu";
+            reg = <0>;
+            status = "okay";
+            compatible = "riscv";
+            riscv,isa = "rv64imafdc";
+            mmu-type = "riscv,sv39";
+            clock-frequency = <50000000>;
+            CPU0_intc: interrupt-controller {
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "riscv,cpu-intc";
+            };
+        };
+    };
+    memory@C0000000 {
+        device_type = "memory";
+        reg = <0xC0000000 0x40000000>;
+    };
+    soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "simple-bus";
+        ranges;
+        clint@10000000 {
+            compatible = "riscv,clint0";
+            interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
+            reg = <0x10000000 0x10000>;
+        };
+        plic: interrupt-controller@c000000 {
+            #interrupt-cells = <1>;
+            compatible = "riscv,plic0";
+            interrupt-controller;
+            interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
+            reg = <0xc000000 0x400000>;
+            reg-names = "control";
+            riscv,max-priority = <7>;
+            riscv,ndev = <16>;
+        };
+        ns16550: uart@62300000 {
+            current-speed = <115200>;
+            compatible = "ns16550a";
+            interrupts-extended = <&plic 1>;
+            reg = <0x62300000 0x1000>;
+            clock-frequency = <50000000>;
+            reg-shift = <2>;
+        };
+    };
+};

devicetree.no-uart.dts

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+/dts-v1/;
+
+/ {
+    #address-cells = <1>;
+    #size-cells = <1>;
+    compatible = "unknown,unknown";
+    model = "unknown,unknown";
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        timebase-frequency = <500000>;
+        CPU0: cpu@0 {
+            device_type = "cpu";
+            reg = <0>;
+            status = "okay";
+            compatible = "riscv";
+            riscv,isa = "rv64imafdc";
+            mmu-type = "riscv,sv39";
+            clock-frequency = <50000000>;
+            CPU0_intc: interrupt-controller {
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "riscv,cpu-intc";
+            };
+        };
+    };
+    memory@C0000000 {
+        device_type = "memory";
+        reg = <0xC0000000 0x40000000>;
+    };
+    soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "simple-bus";
+        ranges;
+        clint@10000000 {
+            compatible = "riscv,clint0";
+            interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
+            reg = <0x10000000 0x10000>;
+        };
+        plic: interrupt-controller@c000000 {
+            #interrupt-cells = <1>;
+            compatible = "riscv,plic0";
+            interrupt-controller;
+            interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
+            reg = <0xc000000 0x400000>;
+            reg-names = "control";
+            riscv,max-priority = <7>;
+            riscv,ndev = <16>;
+        };
+    };
+};

script.ld

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+OUTPUT_ARCH( "riscv" )
+/* TARGET( "binary" ) */
+
+SECTIONS
+{
+  . = 0x80000000;
+  _start = .;
+  .data : { *(.data) }
+}