Allow to build on a different version of dtc.

CTSRD-CHERI · Aug 29, 2024 · 89347e3 · 89347e3
1 parent 40c167c
commit 89347e3
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Showing 3 changed files with 9 additions and 2 deletions.
diff --git a/devicetree.dts b/devicetree.dts
@@ -21,6 +21,7 @@
             mmu-type = "riscv,sv39";
             clock-frequency = <50000000>;
             CPU0_intc: interrupt-controller {
+                #address-cells = <1>;
                 #interrupt-cells = <1>;
                 interrupt-controller;
                 compatible = "riscv,cpu-intc";
@@ -42,6 +43,7 @@
             reg = <0x10000000 0x10000>;
         };
         plic: interrupt-controller@c000000 {
+            #address-cells = <1>;
             #interrupt-cells = <1>;
             compatible = "riscv,plic0";
             interrupt-controller;

diff --git a/devicetree.dual.dts b/devicetree.dual.dts
@@ -21,7 +21,8 @@
             mmu-type = "riscv,sv39";
             clock-frequency = <50000000>;
             CPU0_intc: interrupt-controller {
-                #interrupt-cells = <1>;
+                #address-cells = <1>;
+		#interrupt-cells = <1>;
                 interrupt-controller;
                 compatible = "riscv,cpu-intc";
             };
@@ -35,6 +36,7 @@
 		mmu-type = "riscv,sv39";
 		clock-frequency = <50000000>;
 		CPU1_intc: interrupt-controller {
+                        #address-cells = <1>;
 			#interrupt-cells = <1>;
 			interrupt-controller;
 			compatible = "riscv,cpu-intc";
@@ -59,6 +61,7 @@
             reg = <0x10000000 0x10000>;
         };
         plic: interrupt-controller@c000000 {
+            #address-cells = <1>;
             #interrupt-cells = <1>;
             compatible = "riscv,plic0";
             interrupt-controller;

diff --git a/devicetree.no-uart.dts b/devicetree.no-uart.dts
@@ -18,7 +18,8 @@
             mmu-type = "riscv,sv39";
             clock-frequency = <50000000>;
             CPU0_intc: interrupt-controller {
-                #interrupt-cells = <1>;
+                #address-cells = <1>;
+		#interrupt-cells = <1>;
                 interrupt-controller;
                 compatible = "riscv,cpu-intc";
             };
@@ -39,6 +40,7 @@
             reg = <0x10000000 0x10000>;
         };
         plic: interrupt-controller@c000000 {
+            #address-cells = <1>;
             #interrupt-cells = <1>;
             compatible = "riscv,plic0";
             interrupt-controller;