hart, return fault from tick

* Enables better debugging why the machine stopped
BuJo · Oct 7, 2023 · d9ded91 · d9ded91
1 parent 78138a8
commit d9ded91
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Showing 3 changed files with 21 additions and 15 deletions.
diff --git a/src/bin/archtest.rs b/src/bin/archtest.rs
@@ -10,6 +10,7 @@ use rriscv::device::Device;
 use rriscv::dynbus::DynBus;
 use rriscv::hart::Hart;
 use rriscv::htif::Htif;
+use rriscv::plic::Fault;
 use rriscv::ram::Ram;
 use rriscv::rom::Rom;
 
@@ -48,13 +49,17 @@ fn main() {
         tohost = Range { start, end };
     }
 
+
     let bus = Arc::new(bus);
 
     let mut m = Hart::new(0, pc as u32, bus.clone());
     for i in 0..10000 {
-        if !m.tick() {
-            eprintln!("exited at: {}", i);
-            break;
+        match m.tick() {
+            Ok(_) => {}
+            Err(e) => {
+                eprintln!("exited at: {} ({:?})", i, e);
+                break;
+            }
         }
     }
 

diff --git a/src/hart.rs b/src/hart.rs
@@ -7,6 +7,7 @@ use crate::csr;
 use crate::csr::Csr;
 use crate::device::Device;
 use crate::plic::Fault;
+use crate::plic::Fault::Halt;
 use crate::see;
 
 pub struct Hart<BT: Device> {
@@ -45,16 +46,15 @@ impl<BT: Device> Hart<BT> {
         self.stop = true;
     }
 
-    pub fn tick(&mut self) -> bool {
+    pub fn tick(&mut self) -> Result<(), Fault> {
         if self.stop {
-            return false;
+            return Err(Halt);
         }
 
         let res = self
             .fetch_instruction()
             .and_then(|instruction| self.decode_instruction(instruction))
-            .and_then(|(ins, decoded)| self.execute_instruction(decoded, ins))
-            .is_ok();
+            .and_then(|(ins, decoded)| self.execute_instruction(decoded, ins));
 
         // simulate passing of time
         self.csr[csr::MCYCLE] += 3;
@@ -257,11 +257,8 @@ impl<BT: Device> Hart<BT> {
             } => {
                 let addr = (self.get_register(rs1).wrapping_add(imm as u32)) as usize;
                 let val = self.get_register(rs2);
-                self.bus
-                    .write_word(addr, val)
-                    .expect("address being writeable");
-
-                self.dbgins(ins, format!("sw\t{},{}({})", reg(rs2), imm, reg(rs1)))
+                self.dbgins(ins, format!("sw\t{},{}({})", reg(rs2), imm, reg(rs1)));
+                return self.bus.write_word(addr, val);
             }
             // beq Branch ==
             B {

diff --git a/src/main.rs b/src/main.rs
@@ -32,9 +32,13 @@ fn main() {
         let handle = thread::spawn(move || {
             eprintln!("[{}] hart spawned", id);
             let mut m = Hart::new(id, 0, bus);
-            for _ in 0..100 {
-                if !m.tick() {
-                    break;
+            for i in 0..100 {
+                match m.tick() {
+                    Ok(_) => {}
+                    Err(e) => {
+                        eprintln!("exited at: {} ({:?})", i, e);
+                        break;
+                    }
                 }
             }
         });