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csr, move initialization to csr itself
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BuJo committed Sep 27, 2023
1 parent 4ab97b2 commit a2efaa6
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Showing 2 changed files with 34 additions and 30 deletions.
37 changes: 33 additions & 4 deletions src/csr.rs
Original file line number Diff line number Diff line change
@@ -1,15 +1,18 @@
use std::ops::Index;
use std::ops::IndexMut;

const XLEN: u32 = 32;

pub const NUM_CSRS: usize = 4096;

// M-mode registers
pub const MSTATUS: usize = 0x300;
pub const MISA: usize = 0x301;
pub const MEDELEG: usize = 0x301;
pub const MVENDORID: usize = 0xF11;
pub const MARCHID: usize = 0xF12;
pub const MIMPID: usize = 0xF13;
pub const MHARTID: usize = 0xF14;

pub const MCYCLE: usize = 0xB00;
pub const MINSTRET: usize = 0xB02;

Expand All @@ -18,10 +21,36 @@ pub struct Csr {
}

impl Csr {
pub fn new() -> Csr {
Self {
pub fn new(id: u32) -> Csr {
let mut csr = Self {
csrs: [0; NUM_CSRS],
}
};

// RV32 I
csr[MISA] = 0b01 << (XLEN - 2) | 1 << 8;

// Non-commercial implementation
csr[MVENDORID] = 0;

// Open-Source project, unregistered
csr[MARCHID] = 0;

// Version
csr[MIMPID] = 1;

// Current hart
csr[MHARTID] = id;

// Status
csr[MEDELEG] = 0;
csr[MSTATUS] = 0;

// Cycle counters
csr[MCYCLE] = 0; // actually per core, not hart
csr[MINSTRET] = 0;


csr
}
}

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27 changes: 1 addition & 26 deletions src/hart.rs
Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,6 @@ use crate::csr;
use crate::csr::Csr;
use crate::see;

const XLEN: usize = 32;

pub struct Hart {
bus: Arc<Bus>,
registers: [u32; 32],
Expand All @@ -24,39 +22,16 @@ impl Hart {
bus,
registers: [0; 32],
pc: 0,
csr: Csr::new(),
csr: Csr::new(id),
stop: false,
};

// RV32 I
m.csr[csr::MISA] = 0b01 << (XLEN - 2) | 1 << 8;

// Non-commercial implementation
m.csr[csr::MVENDORID] = 0;

// Open-Source project, unregistered
m.csr[csr::MARCHID] = 0;

// Version
m.csr[csr::MIMPID] = 1;

// Current hart
m.csr[csr::MHARTID] = id;

m.reset();

m
}

pub(crate) fn reset(&mut self) {
// Status
self.csr[csr::MEDELEG] = 0;
self.csr[csr::MSTATUS] = 0;

// Cycle counters
self.csr[csr::MCYCLE] = 0; // actually per core, not hart
self.csr[csr::MINSTRET] = 0;

self.pc = 0;
self.registers = [0; 32];
}
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