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fix: Fix building with blocking feature
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BroderickCarlin committed Oct 30, 2023
1 parent eaa192d commit 70a6133
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Showing 3 changed files with 16 additions and 15 deletions.
4 changes: 3 additions & 1 deletion .github/workflows/rust.yml
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,9 @@ jobs:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- name: Build
- name: Build Async
run: cargo build --verbose --features = ["async"]
- name: Build Blocking
run: cargo build --verbose
- name: Run tests
run: cargo test --verbose
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2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,6 @@ embedded-hal = { version = "1.0.0-rc.1", optional = true }
embedded-hal-async = { version = "1.0.0-rc.1", optional = true }

[features]
default = ["async"]
default = ["blocking"]
async = ["embedded-hal-async"]
blocking = ["embedded-hal"]
25 changes: 12 additions & 13 deletions src/lib.rs
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
#![no_std]

use commands::{Command, Mode};
use embedded_hal_async::spi::Operation;
pub use error::*;
use registers::{ReadableRegister, WritableRegister};

Expand Down Expand Up @@ -35,17 +34,17 @@ impl<SPI: embedded_hal::spi::SpiDevice> A7105<SPI> {
pub fn read_reg<const N: usize, R: ReadableRegister<N>>(&mut self) -> Result<R, SPI::Error> {
let mut buf = [0u8; N];
self.spi.transaction(&mut [
Operation::Write(&[R::id() | READ_FLAG]),
Operation::Read(&mut buf),
embedded_hal::spi::Operation::Write(&[R::id() | Self::READ_FLAG]),
embedded_hal::spi::Operation::Read(&mut buf),
])?;
Ok(R::from_slice(buf))
}

/// Writes a value to a regsiter, determined by the specified register type.
pub fn write_reg<R: WritableRegister>(&mut self, reg: R) -> Result<(), SPI::Error> {
self.spi.transaction(&mut [
Operation::Write(&[R::id()]),
Operation::Write(&reg.into_slice()),
embedded_hal::spi::Operation::Write(&[R::id()]),
embedded_hal::spi::Operation::Write(&reg.into_slice()),
])
}

Expand Down Expand Up @@ -76,8 +75,8 @@ impl<SPI: embedded_hal::spi::SpiDevice> A7105<SPI> {
// The packet was valid so reset the read pointer and do the actual read
self.command(Command::ResetFifoReadPointer)?;
self.spi.transaction(&mut [
Operation::Write(&[Self::RX_BUFFER_ID | READ_FLAG]),
Operation::Read(buf),
embedded_hal::spi::Operation::Write(&[Self::RX_BUFFER_ID | Self::READ_FLAG]),
embedded_hal::spi::Operation::Read(buf),
])?;
Ok(())
}
Expand All @@ -86,8 +85,8 @@ impl<SPI: embedded_hal::spi::SpiDevice> A7105<SPI> {
pub fn tx_packet(&mut self, buf: &[u8]) -> Result<(), SPI::Error> {
self.command(Command::ResetFifoWritePointer)?;
self.spi.transaction(&mut [
Operation::Write(&[Self::TX_BUFFER_ID]),
Operation::Write(buf),
embedded_hal::spi::Operation::Write(&[Self::TX_BUFFER_ID]),
embedded_hal::spi::Operation::Write(buf),
])
}
}
Expand All @@ -101,8 +100,8 @@ impl<SPI: embedded_hal_async::spi::SpiDevice> A7105<SPI> {
let mut buf = [0u8; N];
self.spi
.transaction(&mut [
Operation::Write(&[R::id() | Self::READ_FLAG]),
Operation::Read(&mut buf),
embedded_hal_async::spi::Operation::Write(&[R::id() | Self::READ_FLAG]),
embedded_hal_async::spi::Operation::Read(&mut buf),
])
.await?;
Ok(R::from_slice(buf))
Expand All @@ -112,8 +111,8 @@ impl<SPI: embedded_hal_async::spi::SpiDevice> A7105<SPI> {
pub async fn write_reg<R: WritableRegister>(&mut self, reg: R) -> Result<(), SPI::Error> {
self.spi
.transaction(&mut [
Operation::Write(&[R::id()]),
Operation::Write(&reg.into_slice()),
embedded_hal_async::spi::Operation::Write(&[R::id()]),
embedded_hal_async::spi::Operation::Write(&reg.into_slice()),
])
.await
}
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