linker: Map vector table to RAM for AST1060 boot flow #21
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AST1060 does not support XIP; instead, its ROM code copies the entire firmware image from flash to RAM and begins execution there. To support this flow, the vector table must reside in RAM starting at address 0x00000000, rather than being mapped to flash as assumed by the default cortex-m-rt layout. This change updates the linker script to correctly position the vector table for AST1060's ROM-based boot process. Signed-off-by: Steven Lee <[email protected]>
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AST1060 does not support XIP; instead, its ROM code copies the entire firmware image from flash to RAM and begins execution there. To support this flow, the vector table must reside in RAM starting at address 0x00000000, rather than being mapped to flash as assumed by the default cortex-m-rt layout.
This change updates the linker script to correctly position the vector table for AST1060's ROM-based boot process.