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Ashwin-Rajesh/README.md

Ashwin Rajesh

I am a first-year MTech student in Microelectronics and VLSI Design at the Indian Institute of Science, Bangalore, and part of the NeuRonICs lab at DESE. My interests are in digital hardware design for efficient computing. Currently working on the design of low-power hardware for real-time image classification inference on the edge.

  • 16x16 array of convay's game of life in silicon (Skywater130)
  • Dual channel sqaure, sawtooth or sinusoidal function generator (using CORDIC)
  • On BASYS3 FPGA
  • A tiny spice parser and engine written in python
  • An AXI-Lite IP that performs the CORDIC algorithm
  • Extensive convergence and error characterization using randomized inputs
  • 16-bit CPU with a 4-stage pipeline
  • Random instruction generator and assembler (python)
  • Random testing for 100,000 instructions (compared with a gold standard)
  • SPI, I2C and UART master and slave
  • Verilog
  • System verilog
  • Formal verification with symbiyosys

Alongside hardware design, I enjoy programming and creating random (sometimes useless) hobby projects, from Arduino to robotics and ML and this is where a lot of them reside.

  1. GNSS and IMU sensor fusion using Kalman filter (in carla)
  2. Lane Detection using Computer Vision
  3. Universal infrared remote
  4. Stroboscopic waterfall
  5. Step piano
  6. POV display
  7. Morse encoder

Reach me at my LinkedIn : https://www.linkedin.com/in/ashwinrajesh/

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  1. Pytorch_projects Pytorch_projects Public

    Deep learning projects implemented in pytorch as jupyter notebooks, mostly focused on computer vision

    Jupyter Notebook

  2. Kalman_filter_carla Kalman_filter_carla Public

    Kalman filter for self driving cars using imu and gnss data, acquired from the carla simulator

    Jupyter Notebook 5 5

  3. UniversalRemote_ESP32 UniversalRemote_ESP32 Public

    An IOT universal remote controller using the ESP32 microcontroller (ESP32-WROOM32 module), with firmware developed using ESP-IDF

    C++ 2 1

  4. RiSC-16 RiSC-16 Public

    RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in s…

    SystemVerilog 10 1

  5. Verilog_comm Verilog_comm Public

    Implementation of several common digital communication protocols, to be used in FPGAs.

    Verilog 5 2

  6. Verilog_projects Verilog_projects Public

    Some beginner projects using verilog HDL, along with some documentation on basic syntax

    Verilog 10 2