Releases: Artentus/gsim
Releases · Artentus/gsim
1.1.1
1.1.0
Fix zero edge case in BigUint
1.0.8
Implement NEG component
1.0.7
Improve importing of procmux cells
1.0.6
Fix fixup constants using reversed bit order
1.0.5
Add configurable reset values for registers and memory
1.0.4
Fix bug in Yosys import producing invalid graphs if wires contained d…
1.0.3
Mark result types as must_use and add unwrap function
1.0.2
Implement multiply component
1.0.1
Fix shift cell import