GitHub - AlecTaggart/ARM-Single-Cycle: ARM Single-Cycle-CPU Implementation in Logisim

single-cycle implementation of a subset of the ARMv7 instruction set using digital logic in Logisim.

USAGE:

To create ROM run: $ objdump -d file.o | python makerom.py > file_rom.txt

Then load ROM into CPU on Logisim.

FUNCTION:

Function as a single cycle CPU capable of running basic programs like fib_iter, fib_rec, sum_array, find_max.

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
OUTPUT.txt		OUTPUT.txt
OUTPUT.txt.txt		OUTPUT.txt.txt
README.md		README.md
fibIter.o		fibIter.o
fibIter.s		fibIter.s
fibIter.txt		fibIter.txt
fibIter25.txt		fibIter25.txt
fibRec.o		fibRec.o
fibRec.s		fibRec.s
fibRec.txt		fibRec.txt
fibRec10.txt		fibRec10.txt
fibRec7.txt		fibRec7.txt
makerom.py		makerom.py
p4.circ		p4.circ
sumArray.o		sumArray.o
sumArray.s		sumArray.s
sumArray.txt		sumArray.txt
sumArray10.txt		sumArray10.txt
test.o		test.o
test.s		test.s
testclear.o		testclear.o

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