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Update for Jetpack 6.2 and super mode (#8)
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AlexKlimaj authored Jan 29, 2025
1 parent 8564231 commit 38a0f9d
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/*This dtsi file was generated by jetson orin nano&nx pinmux dp_bidir.xlsm Revision: 1.04 */
/*This dtsi file was generated by jetson orin nano&nx pinmux dp.xlsm Revision: 1.03 */
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
Expand All @@ -12,12 +12,12 @@
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS'
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Expand All @@ -29,9 +29,9 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/

#define IO_PAD_VOLTAGE_1_2V 1200000
#define IO_PAD_VOLTAGE_1_8V 1800000
#define IO_PAD_VOLTAGE_3_3V 3300000
#define IO_PAD_VOLTAGE_1_2V 1200000
#define IO_PAD_VOLTAGE_1_8V 1800000
#define IO_PAD_VOLTAGE_3_3V 3300000
/dts-v1/;
/ {
pmc@c360000 {
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@@ -1,4 +1,4 @@
/*This dtsi file was generated by jetson orin nano&nx pinmux dp_bidir.xlsm Revision: 1.04 */
/*This dtsi file was generated by jetson orin nano&nx pinmux dp.xlsm Revision: 1.03 */
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
Expand All @@ -12,12 +12,12 @@
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS'
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Expand Down Expand Up @@ -294,26 +294,6 @@
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

soc_gpio32_pq5 {
nvidia,pins = "soc_gpio32_pq5";
nvidia,function = "extperiph3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

soc_gpio33_pq6 {
nvidia,pins = "soc_gpio33_pq6";
nvidia,function = "extperiph4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

uart1_tx_pr2 {
nvidia,pins = "uart1_tx_pr2";
nvidia,function = "uarta";
Expand Down Expand Up @@ -829,6 +809,26 @@
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

soc_gpio32_pq5 {
nvidia,pins = "soc_gpio32_pq5";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

soc_gpio33_pq6 {
nvidia,pins = "soc_gpio33_pq6";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

uart1_rts_pr4 {
nvidia,pins = "uart1_rts_pr4";
nvidia,function = "rsvd1";
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Expand Up @@ -13,4 +13,4 @@
cvb_eeprom_read_size = <0x0>;
};
};
};
};
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@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/* SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Definitions for Jetson tegra234-p3767-0000 board.
*/
Expand All @@ -11,7 +10,12 @@
"nvidia,p3768-0000+p3767-0001", \
"nvidia,p3768-0000+p3767-0003", \
"nvidia,p3768-0000+p3767-0004", \
"nvidia,p3768-0000+p3767-0005"
"nvidia,p3768-0000+p3767-0005", \
"nvidia,p3768-0000+p3767-0000-super", \
"nvidia,p3768-0000+p3767-0001-super", \
"nvidia,p3768-0000+p3767-0003-super", \
"nvidia,p3768-0000+p3767-0004-super", \
"nvidia,p3768-0000+p3767-0005-super"

#define JETSON_COMPATIBLE_P3509 "nvidia,p3509-0000+p3767-0000", \
"nvidia,p3509-0000+p3767-0001", \
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Expand Up @@ -17,12 +17,17 @@ dtb-y += tegra234-p3740-0002+p3701-0008-nv.dtb
dtb-y += tegra234-p3740-0002+p3701-0008-nv-safety.dtb
dtb-y += tegra234-p3768-0000+p3767-0000-nv.dtb
dtb-y += tegra234-p3768-0000+p3767-0000-nv-px1.dtb
dtb-y += tegra234-p3768-0000+p3767-0000-nv-super.dtb
dtb-y += tegra234-p3768-0000+p3767-0000-nv-taylor-high.dtb
dtb-y += tegra234-p3768-0000+p3767-0000-nv-taylor-low.dtb
dtb-y += tegra234-p3768-0000+p3767-0001-nv.dtb
dtb-y += tegra234-p3768-0000+p3767-0001-nv-super.dtb
dtb-y += tegra234-p3768-0000+p3767-0003-nv.dtb
dtb-y += tegra234-p3768-0000+p3767-0003-nv-super.dtb
dtb-y += tegra234-p3768-0000+p3767-0004-nv.dtb
dtb-y += tegra234-p3768-0000+p3767-0004-nv-super.dtb
dtb-y += tegra234-p3768-0000+p3767-0005-nv.dtb
dtb-y += tegra234-p3768-0000+p3767-0005-nv-super.dtb

ifneq ($(dtb-y),)
dtb-y := $(addprefix $(makefile-path)/,$(dtb-y))
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Expand Up @@ -441,3 +441,5 @@
status = "okay";
};
};

/delete-node/ &{/gpio-keys/key-suspend};
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Expand Up @@ -37,11 +37,29 @@ dtbo-y += tegra234-p3767-0000+p3509-a02-csi.dtbo
dtbo-y += tegra234-p3767-0000+p3509-a02-hdr40.dtbo
dtbo-y += tegra234-p3767-0000+p3509-a02-m2ke.dtbo
dtbo-y += tegra234-p3767-0000+p3768-0000-csi.dtbo
dtbo-y += tegra234-p3740-0002+p3701-0008-hdr20.dtbo
dtbo-y += tegra234-p3740-0002+p3701-0008-m2ke.dtbo
dtbo-y += tegra234-p3740-0002+p3701-0008-m2kb.dtbo
dtbo-y += tegra234-p3740-0002-p3701-0008-csi.dtbo
dtbo-y += tegra234-p3737-camera-dual-imx274-overlay.dtbo
dtbo-y += tegra234-p3737-camera-e3331-overlay.dtbo
dtbo-y += tegra234-p3737-camera-e3333-overlay.dtbo
dtbo-y += tegra234-p3737-camera-imx185-overlay.dtbo
# dtbo-y += tegra234-p3767-camera-p3768-imx219-dual.dtbo
# dtbo-y += tegra234-p3767-camera-p3768-imx477-dual.dtbo
# dtbo-y += tegra234-p3767-camera-p3768-imx477-dual-4lane.dtbo
# dtbo-y += tegra234-p3767-camera-p3768-imx477-imx219.dtbo
# dtbo-y += tegra234-p3740-camera-p3783-a00-overlay.dtbo
dtbo-y += tegra234-p3737-camera-eCAM130A-overlay.dtbo
dtbo-y += tegra234-p3737-camera-dual-hawk-ar0234-e3653-overlay.dtbo
dtbo-y += tegra234-p3737-camera-imx390-overlay.dtbo
dtbo-y += tegra234-p3737-camera-imx390-addr-0x21-overlay.dtbo
dtbo-y += tegra234-p3737-camera-p3762-a00-1Hawk-overlay.dtbo
dtbo-y += tegra234-p3737-camera-p3762-a00-2Hawk-overlay.dtbo
dtbo-y += tegra234-p3737-camera-p3762-a00-3Hawk-3Owl-overlay.dtbo
dtbo-y += tegra234-p3737-camera-p3762-a00-4Hawk-overlay.dtbo
dtbo-y += tegra234-p3737-camera-p3762-a00-4Owl-overlay.dtbo
dtbo-y += tegra234-p3737-camera-p3762-a00-overlay.dtbo
dtbo-y += tegra234-p3740-camera-p3783-a00-overlay.dtbo
# dtbo-y += tegra234-p3767-camera-p3768-imx219-C.dtbo
# dtbo-y += tegra234-p3767-camera-p3768-imx219-A.dtbo
# dtbo-y += tegra234-p3767-camera-p3768-imx219-imx477.dtbo
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