SPI driver issue #91834
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Pateldinkar
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SPI driver issue
#91834
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Hello all,
I am using a peripheral which have an internal FIFO. From that peripheral, I receive the interrupt when fifo is full. I received the interrupt every 160ms and read 360 bytes of data. It uses a fixed register read/write cycle every interrupt for fifo read. This process is successful over the longtime. After some random point of time SPI driver sent the wrong value sequence and due to that, my peripheral internal configuration changed, and it stopped working as per expectations.
In both failure and success cases, it is sent from the same API with a fixed register value. I also verify that the spi_transceive_dt is successful every time.
Can anyone help me debug this issue?
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