drivers: nxp : flexspi: add GD nor flash support

Fix a bug in quad bit enablement.
Add LUT for Giga Device nor flash GD25Q256x.

Signed-off-by: Raymond Lei <[email protected]>

Author: Raymond0225

drivers/flash/flash_mcux_flexspi_nor.c

@@ -339,8 +339,8 @@ static int flash_flexspi_nor_read(const struct device *dev, off_t offset,
 	}
 
 	uint8_t *src = memc_flexspi_get_ahb_address(&data->controller,
-						    data->port,
-						    offset);
+							data->port,
+							offset);
 
 	memcpy(buffer, src, len);
 
@@ -366,8 +366,8 @@ static int flash_flexspi_nor_write(const struct device *dev, off_t offset,
 	unsigned int key = 0;
 
 	uint8_t *dst = memc_flexspi_get_ahb_address(&data->controller,
-						    data->port,
-						    offset);
+							data->port,
+							offset);
 
 	if (memc_flexspi_is_running_xip(&data->controller)) {
 		/*
@@ -436,8 +436,8 @@ static int flash_flexspi_nor_erase(const struct device *dev, off_t offset,
 	unsigned int key = 0;
 
 	uint8_t *dst = memc_flexspi_get_ahb_address(&data->controller,
-						    data->port,
-						    offset);
+							data->port,
+							offset);
 
 	if (offset % SPI_NOR_SECTOR_SIZE) {
 		LOG_ERR("Invalid offset");
@@ -622,14 +622,16 @@ static int flash_flexspi_nor_quad_enable(struct flash_flexspi_nor_data *data,
 				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR2,
 				kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
 
-		/* Set bit 7 of status register 2 */
-		bit = BIT(7);
+		/* Set bit 1 of status register 2 */
+		bit = BIT(1);
 		rd_size = 1;
 		wr_size = 1;
 		break;
 	default:
 		return -ENOTSUP;
 	}
+
+
 	ret = memc_flexspi_set_device_config(&data->controller,
 				&config,
 				(uint32_t *)flexspi_lut,
@@ -638,6 +640,7 @@ static int flash_flexspi_nor_quad_enable(struct flash_flexspi_nor_data *data,
 	if (ret < 0) {
 		return ret;
 	}
+
 	transfer.dataSize = rd_size;
 	transfer.seqIndex = SCRATCH_CMD;
 	transfer.cmdType = kFLEXSPI_Read;
@@ -873,7 +876,7 @@ static int flash_flexspi_nor_config_flash(struct flash_flexspi_nor_data *data,
 	if (ret == 0) {
 		/* Attempt to enable 4 byte addressing */
 		ret = flash_flexspi_nor_4byte_enable(data, flexspi_lut,
-						     dw16.enter_4ba);
+							 dw16.enter_4ba);
 		if (ret == 0) {
 			/* Use 4 byte address width */
 			addr_width = 32;
@@ -892,7 +895,7 @@ static int flash_flexspi_nor_config_flash(struct flash_flexspi_nor_data *data,
 	 * Note- enhanced XIP not currently supported, nor is 4-4-4 mode.
 	 */
 	if (jesd216_bfp_read_support(&header->phdr[0], bfp,
-	    JESD216_MODE_144, &instr) > 0) {
+		JESD216_MODE_144, &instr) > 0) {
 		LOG_DBG("Enable 144 mode");
 		/* Configure for 144 QUAD read mode */
 		if (instr.mode_clocks == 2) {
@@ -919,7 +922,7 @@ static int flash_flexspi_nor_config_flash(struct flash_flexspi_nor_data *data,
 		ret = jesd216_bfp_decode_dw15(&header->phdr[0], bfp, &dw15);
 		if (ret == 0) {
 			ret = flash_flexspi_nor_quad_enable(data, flexspi_lut,
-							    dw15.qer);
+								dw15.qer);
 			if (ret == 0) {
 				/* Now, install 1S-1S-4S page program command */
 				flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
@@ -934,7 +937,7 @@ static int flash_flexspi_nor_config_flash(struct flash_flexspi_nor_data *data,
 		}
 
 	} else if (jesd216_bfp_read_support(&header->phdr[0], bfp,
-	    JESD216_MODE_122, &instr) > 0) {
+		JESD216_MODE_122, &instr) > 0) {
 		LOG_DBG("Enable 122 mode");
 		if (instr.mode_clocks == 4) {
 			mode_cmd = kFLEXSPI_Command_MODE8_SDR;
@@ -1041,8 +1044,8 @@ flash_flexspi_nor_is25_clear_dummy_cycles(struct flash_flexspi_nor_data *data,
 		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x14,
 				kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
 	ret = memc_flexspi_set_device_config(&data->controller, &config, (uint32_t *)flexspi_lut,
-					     FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
-					     data->port);
+						 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
+						 data->port);
 
 	if (ret < 0) {
 		return ret;
@@ -1066,8 +1069,8 @@ flash_flexspi_nor_is25_clear_dummy_cycles(struct flash_flexspi_nor_data *data,
 		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC0,
 				kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
 	ret = memc_flexspi_set_device_config(&data->controller, &config, (uint32_t *)flexspi_lut,
-					     FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
-					     data->port);
+						 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
+						 data->port);
 	if (ret < 0) {
 		return ret;
 	}
@@ -1140,7 +1143,7 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
 				kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
 		/* Device uses bit 1 of status reg 2 for QE */
 		return flash_flexspi_nor_quad_enable(data, flexspi_lut,
-						     JESD216_DW15_QER_VAL_S2B1v5);
+							 JESD216_DW15_QER_VAL_S2B1v5);
 	case 0x2060ef:
 		/* W25Q512NW-IQ/IN flash, use 4 byte read/write */
 		flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
@@ -1171,7 +1174,7 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
 				kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
 		/* Device uses bit 1 of status reg 2 for QE */
 		return flash_flexspi_nor_quad_enable(data, flexspi_lut,
-						     JESD216_DW15_QER_VAL_S2B1v5);
+							 JESD216_DW15_QER_VAL_S2B1v5);
 	case 0x3A25C2:
 		/* MX25U51245G flash, use 4 byte read/write */
 		flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
@@ -1293,7 +1296,40 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
 				kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, SPI_NOR_CMD_WREN,
 				kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0);
 		return 0;
+	case 0x1940C8: /* GD25Q256E */
+		flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
+				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
+				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x20);
+		/* Flash needs 15 dummy cycles */
+		flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
+				kFLEXSPI_Command_MODE8_SDR, kFLEXSPI_4PAD, 0xF0,
+				kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x04);
+		flexspi_lut[READ][2] = FLEXSPI_LUT_SEQ(
+				kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04,
+				kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00);
+
+		data->legacy_poll = true;
+		flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
+				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
+				kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04);
+
+		flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
+				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
+				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20);
+
+		flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
+				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B,
+				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20);
 
+		flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
+				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_4_4B,
+				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20);
+		flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
+				kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04,
+				kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00);
+
+		return flash_flexspi_nor_quad_enable(data, flexspi_lut,
+						JESD216_DW15_QER_VAL_S2B1v6);
 	default:
 		return -ENOTSUP;
 	}
@@ -1337,7 +1373,7 @@ static int flash_flexspi_nor_probe(struct flash_flexspi_nor_data *data)
 
 	/* Setup initial LUT table and FlexSPI configuration */
 	memcpy(flexspi_probe_lut, flash_flexspi_nor_base_lut,
-	       sizeof(flash_flexspi_nor_base_lut));
+		   sizeof(flash_flexspi_nor_base_lut));
 
 	ret = memc_flexspi_set_device_config(&data->controller, &config,
 					(uint32_t *)flexspi_probe_lut,
@@ -1386,7 +1422,7 @@ static int flash_flexspi_nor_probe(struct flash_flexspi_nor_data *data)
 
 	/* Configure flash */
 	ret = flash_flexspi_nor_config_flash(data, header, bfp,
-					     flexspi_probe_lut);
+						 flexspi_probe_lut);
 	if (ret < 0) {
 		goto _exit;
 	}
@@ -1534,12 +1570,12 @@ static DEVICE_API(flash, flash_flexspi_nor_api) = {
 	};								\
 									\
 	DEVICE_DT_INST_DEFINE(n,					\
-			      flash_flexspi_nor_init,			\
-			      NULL,					\
-			      &flash_flexspi_nor_data_##n,		\
-			      &flash_flexspi_nor_config_##n,		\
-			      POST_KERNEL,				\
-			      CONFIG_FLASH_INIT_PRIORITY,		\
-			      &flash_flexspi_nor_api);
+				  flash_flexspi_nor_init,			\
+				  NULL,					\
+				  &flash_flexspi_nor_data_##n,		\
+				  &flash_flexspi_nor_config_##n,		\
+				  POST_KERNEL,				\
+				  CONFIG_FLASH_INIT_PRIORITY,		\
+				  &flash_flexspi_nor_api);
 
 DT_INST_FOREACH_STATUS_OKAY(FLASH_FLEXSPI_NOR)