@@ -43,6 +43,30 @@ static const uint32_t dma_priority[] = {
4343#endif
4444};
4545
46+ #if defined(CONFIG_DMA_STM32U5 )
47+ static const uint32_t dma_src_size [] = {
48+ DMA_SRC_DATAWIDTH_BYTE ,
49+ DMA_SRC_DATAWIDTH_HALFWORD ,
50+ DMA_SRC_DATAWIDTH_WORD ,
51+ };
52+ static const uint32_t dma_dest_size [] = {
53+ DMA_DEST_DATAWIDTH_BYTE ,
54+ DMA_DEST_DATAWIDTH_HALFWORD ,
55+ DMA_DEST_DATAWIDTH_WORD ,
56+ };
57+ #else
58+ static const uint32_t dma_p_size [] = {
59+ DMA_PDATAALIGN_BYTE ,
60+ DMA_PDATAALIGN_HALFWORD ,
61+ DMA_PDATAALIGN_WORD ,
62+ };
63+ static const uint32_t dma_m_size [] = {
64+ DMA_MDATAALIGN_BYTE ,
65+ DMA_MDATAALIGN_HALFWORD ,
66+ DMA_MDATAALIGN_WORD ,
67+ };
68+ #endif
69+
4670struct queue_item {
4771 void * buffer ;
4872 size_t size ;
@@ -317,17 +341,34 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
317341 hdma -> Init .Request = dma_cfg .dma_slot ;
318342#endif
319343
344+ if (dma_cfg .source_data_size != dma_cfg .dest_data_size ) {
345+ LOG_ERR ("Source and destination data sizes are not aligned" );
346+ return - EINVAL ;
347+ }
348+
349+ int idx = find_lsb_set (dma_cfg .source_data_size ) - 1 ;
350+
320351#if defined(CONFIG_DMA_STM32U5 )
352+ if (idx >= ARRAY_SIZE (dma_src_size )) {
353+ LOG_ERR ("Invalid source and destination DMA data size" );
354+ return - EINVAL ;
355+ }
356+
357+ hdma -> Init .SrcDataWidth = dma_src_size [idx ];
358+ hdma -> Init .DestDataWidth = dma_dest_size [idx ];
321359 hdma -> Init .BlkHWRequest = DMA_BREQ_SINGLE_BURST ;
322- hdma -> Init .SrcDataWidth = DMA_SRC_DATAWIDTH_HALFWORD ;
323- hdma -> Init .DestDataWidth = DMA_DEST_DATAWIDTH_HALFWORD ;
324360 hdma -> Init .SrcBurstLength = 1 ;
325361 hdma -> Init .DestBurstLength = 1 ;
326362 hdma -> Init .TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0 | DMA_DEST_ALLOCATED_PORT0 ;
327363 hdma -> Init .TransferEventMode = DMA_TCEM_BLOCK_TRANSFER ;
328364#else
329- hdma -> Init .PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD ;
330- hdma -> Init .MemDataAlignment = DMA_MDATAALIGN_HALFWORD ;
365+ if (idx >= ARRAY_SIZE (dma_m_size )) {
366+ LOG_ERR ("Invalid peripheral and memory DMA data size" );
367+ return - EINVAL ;
368+ }
369+
370+ hdma -> Init .PeriphDataAlignment = dma_p_size [idx ];
371+ hdma -> Init .MemDataAlignment = dma_m_size [idx ];
331372 hdma -> Init .PeriphInc = DMA_PINC_DISABLE ;
332373 hdma -> Init .MemInc = DMA_MINC_ENABLE ;
333374#endif
@@ -836,18 +877,22 @@ static DEVICE_API(i2s, i2s_stm32_driver_api) = {
836877 .read = i2s_stm32_sai_read ,
837878};
838879
839- #define SAI_DMA_CHANNEL_INIT (index , dir , src_dev , dest_dev ) \
880+ #define SAI_DMA_CHANNEL_INIT (index , dir , src , dest ) \
840881 .stream = { \
841882 .dma_dev = DEVICE_DT_GET(STM32_DMA_CTLR(index, dir)), \
842883 .dma_channel = DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \
843884 .reg = (DMA_TypeDef *)DT_REG_ADDR( \
844885 DT_PHANDLE_BY_NAME(DT_DRV_INST(index), dmas, dir)), \
845886 .dma_cfg = { \
846887 .dma_slot = STM32_DMA_SLOT(index, dir, slot), \
847- .channel_direction = src_dev ##_TO_##dest_dev, \
888+ .channel_direction = src ##_TO_##dest, \
848889 .dma_callback = dma_callback, \
849890 .channel_priority = STM32_DMA_CONFIG_PRIORITY( \
850891 STM32_DMA_CHANNEL_CONFIG(index, dir)), \
892+ .source_data_size = STM32_DMA_CONFIG_##src##_DATA_SIZE( \
893+ STM32_DMA_CHANNEL_CONFIG(index, dir)), \
894+ .dest_data_size = STM32_DMA_CONFIG_##dest##_DATA_SIZE( \
895+ STM32_DMA_CHANNEL_CONFIG(index, dir)), \
851896 }, \
852897 .stream_start = stream_start, \
853898 .queue_drop = queue_drop, \
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