From 22899349c062d160e7ed74c103266505b4d899a2 Mon Sep 17 00:00:00 2001 From: Akihiko Odaki Date: Fri, 22 Aug 2025 22:49:45 +0900 Subject: [PATCH 1/2] allow type declarations in tasks and functions IEEE Std 1800-2023 has the following structural hierarchy: 1. A.2.6 Function declarations and A.2.7 Task declarations 2. A.2.8 Block item declarations 3. A.2.1.3 Type declarations Therefore, type declarations can be placed inside task and function declarations. --- src/Language/SystemVerilog/Parser/Parse.y | 14 +++++++++++--- test/core/tf_typedef.sv | 12 ++++++++++++ test/core/tf_typedef.v | 11 +++++++++++ 3 files changed, 34 insertions(+), 3 deletions(-) create mode 100644 test/core/tf_typedef.sv create mode 100644 test/core/tf_typedef.v diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index 2fb2475..da7124c 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -33,7 +33,7 @@ import Language.SystemVerilog.Parser.Tokens %tokentype { Token } %error { parseErrorTok } -%expect 0 +%expect 4 %token @@ -947,9 +947,17 @@ ImportOrExport :: { [PackageItem] } : "import" PackageImportItems ";" { map (uncurry Import) $2 } | "export" PackageImportItems ";" { map (uncurry Export) $2 } | "export" "*" "::" "*" ";" { [Export "" ""] } +BlockItemDecls :: { [Decl] } + : {- empty -} { [] } + | ";" BlockItemDecls { $2 } + | BlockItemDecl BlockItemDecls { $1 ++ $2 } +BlockItemDecl :: { [Decl] } + : DataDecl { $1 } +DataDecl :: { [Decl] } + : Typedef { [$1] } TaskOrFunction :: { PackageItem } - : "function" Lifetime FuncRetAndName TFItems DeclsAndStmts endfunction StrTag {% checkTag (snd $3) $7 $ Function $2 (fst $3) (snd $3) (map makeInput $4 ++ fst $5) (snd $5) } - | "task" Lifetime Identifier TFItems DeclsAndStmts endtask StrTag {% checkTag $3 $7 $ Task $2 $3 ($4 ++ fst $5) (snd $5) } + : "function" Lifetime FuncRetAndName TFItems BlockItemDecls DeclsAndStmts endfunction StrTag {% checkTag (snd $3) $8 $ Function $2 (fst $3) (snd $3) (map makeInput $4 ++ $5 ++ fst $6) (snd $6) } + | "task" Lifetime Identifier TFItems BlockItemDecls DeclsAndStmts endtask StrTag {% checkTag $3 $8 $ Task $2 $3 ($4 ++ $5 ++ fst $6) (snd $6) } Typedef :: { Decl } : "typedef" Type Identifier ";" { ParamType Localparam $3 $2 } | "typedef" Type Identifier DimensionsNonEmpty ";" { ParamType Localparam $3 (UnpackedType $2 $4) } diff --git a/test/core/tf_typedef.sv b/test/core/tf_typedef.sv new file mode 100644 index 0000000..025904f --- /dev/null +++ b/test/core/tf_typedef.sv @@ -0,0 +1,12 @@ +module top; + task t; + typedef bit u; + $display("t = %d", u'(0)); + endtask + function f; + typedef bit u; + return u'(1); + endfunction + initial t(); + initial $display("f = %d", f()); +endmodule diff --git a/test/core/tf_typedef.v b/test/core/tf_typedef.v new file mode 100644 index 0000000..b73504f --- /dev/null +++ b/test/core/tf_typedef.v @@ -0,0 +1,11 @@ +module top; + task t; + $display("t = %d", 1'd0); + endtask + function f; + input reg _sv2v_unused; + f = 1'd1; + endfunction + initial t; + initial $display("f = %d", f(0)); +endmodule From 6404cbb2f10ef20ed16b7e3c369695dd7f7e4373 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Sat, 1 Nov 2025 23:31:52 -0400 Subject: [PATCH 2/2] pursue a different approach and update test case --- src/Language/SystemVerilog/Parser/Parse.y | 15 ++++--------- test/core/tf_typedef.sv | 19 +++++++++++------ test/core/tf_typedef.v | 26 +++++++++++++++-------- 3 files changed, 33 insertions(+), 27 deletions(-) diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index da7124c..bfb1551 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -33,7 +33,7 @@ import Language.SystemVerilog.Parser.Tokens %tokentype { Token } %error { parseErrorTok } -%expect 4 +%expect 0 %token @@ -947,17 +947,9 @@ ImportOrExport :: { [PackageItem] } : "import" PackageImportItems ";" { map (uncurry Import) $2 } | "export" PackageImportItems ";" { map (uncurry Export) $2 } | "export" "*" "::" "*" ";" { [Export "" ""] } -BlockItemDecls :: { [Decl] } - : {- empty -} { [] } - | ";" BlockItemDecls { $2 } - | BlockItemDecl BlockItemDecls { $1 ++ $2 } -BlockItemDecl :: { [Decl] } - : DataDecl { $1 } -DataDecl :: { [Decl] } - : Typedef { [$1] } TaskOrFunction :: { PackageItem } - : "function" Lifetime FuncRetAndName TFItems BlockItemDecls DeclsAndStmts endfunction StrTag {% checkTag (snd $3) $8 $ Function $2 (fst $3) (snd $3) (map makeInput $4 ++ $5 ++ fst $6) (snd $6) } - | "task" Lifetime Identifier TFItems BlockItemDecls DeclsAndStmts endtask StrTag {% checkTag $3 $8 $ Task $2 $3 ($4 ++ $5 ++ fst $6) (snd $6) } + : "function" Lifetime FuncRetAndName TFItems DeclsAndStmts endfunction StrTag {% checkTag (snd $3) $7 $ Function $2 (fst $3) (snd $3) (map makeInput $4 ++ fst $5) (snd $5) } + | "task" Lifetime Identifier TFItems DeclsAndStmts endtask StrTag {% checkTag $3 $7 $ Task $2 $3 ($4 ++ fst $5) (snd $5) } Typedef :: { Decl } : "typedef" Type Identifier ";" { ParamType Localparam $3 $2 } | "typedef" Type Identifier DimensionsNonEmpty ";" { ParamType Localparam $3 (UnpackedType $2 $4) } @@ -1234,6 +1226,7 @@ DeclsAndStmts :: { ([Decl], [Stmt]) } DeclOrStmt :: { ([Decl], [Stmt]) } : DeclTokens(";") { parseDTsAsDeclOrStmt $1 } | ParameterDecl(";") { ($1, []) } + | Typedef { ([$1], []) } ParameterDecl(delim) :: { [Decl] } : ParameterDeclKW DeclAsgns delim { makeParamDecls $1 (Implicit Unspecified []) $2 } diff --git a/test/core/tf_typedef.sv b/test/core/tf_typedef.sv index 025904f..8619b47 100644 --- a/test/core/tf_typedef.sv +++ b/test/core/tf_typedef.sv @@ -1,12 +1,17 @@ module top; task t; - typedef bit u; - $display("t = %d", u'(0)); + typedef byte u; + $display("t %b", u'('1)); endtask - function f; - typedef bit u; - return u'(1); + function integer f; + input reg signed i; + typedef shortint v; + $display("i %b", v'(i)); + return $bits(v); endfunction - initial t(); - initial $display("f = %d", f()); + initial begin + t(); + $display("f %b", f(0)); + $display("f %b", f(1)); + end endmodule diff --git a/test/core/tf_typedef.v b/test/core/tf_typedef.v index b73504f..3526567 100644 --- a/test/core/tf_typedef.v +++ b/test/core/tf_typedef.v @@ -1,11 +1,19 @@ module top; - task t; - $display("t = %d", 1'd0); - endtask - function f; - input reg _sv2v_unused; - f = 1'd1; - endfunction - initial t; - initial $display("f = %d", f(0)); + task t; + $display("t %b", 8'hFF); + endtask + function integer f; + input reg signed i; + reg [15:0] j; + begin + j = i; + $display("i %b", j); + f = 16; + end + endfunction + initial begin + t; + $display("f %b", f(0)); + $display("f %b", f(1)); + end endmodule