Name		Name	Last commit message	Last commit date
parent directory ..
bin		bin
Makefile		Makefile
README.md		README.md
bibliography.md		bibliography.md
clean		clean
common.hpp		common.hpp
counter.cpp		counter.cpp
counter.params		counter.params
counter.v		counter.v
counter_syn.v		counter_syn.v
counter_tb.v		counter_tb.v
display_tb.v		display_tb.v
error_tb.v		error_tb.v
getting-started.md		getting-started.md
icarus.md		icarus.md
language.md		language.md
monitor_tb.v		monitor_tb.v
negator.cpp		negator.cpp
negator.params		negator.params
negator.v		negator.v
negator_tb.v		negator_tb.v
ram.v		ram.v
ram_dual.v		ram_dual.v
ram_dual_tb.v		ram_dual_tb.v
ram_tb.v		ram_tb.v
run		run
run-icarus-one		run-icarus-one
run-many		run-many
run-verilator-one		run-verilator-one
standards.md		standards.md
subleq.cpp		subleq.cpp
subleq.params		subleq.params
subleq.v		subleq.v
synthesis.md		synthesis.md
two_modules.v		two_modules.v
two_modules_tb.v		two_modules_tb.v
verilator.md		verilator.md
versions.md		versions.md
vs-vhdl.md		vs-vhdl.md

README.md

Verilog

Getting started
Theory
1. Standards
2. Vs VHDL
3. Simulators
  1. Verilator
  2. Icarus
4. Synthesis
5. Versions
Examples
1. Negator
  1. src
  2. tb
  3. tb verilator
2. Two modules
  1. src
  2. tb
3. Counter
  1. src
  2. tb
  3. tb verilator
4. RAM
  1. src
  2. tb
5. RAM dual
  1. src
  2. tb
6. Stdout
  1. display
  2. monitor
  3. error
Bibliography