{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":713309891,"defaultBranch":"master","name":"xen","ownerLogin":"xcp-ng","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2023-11-02T09:07:22.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/34775376?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1724764779.0","currentOid":""},"activityList":{"items":[{"before":"65ca7062d51c7e4d8b137624f6913184eb2d6dca","after":"64213819bc49d864e27aea21e8983419adbd529f","ref":"refs/heads/hyper_sev_4.19","pushedAt":"2024-09-04T08:51:26.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"Fix the errors reported by clang\n\n__read_mostly is mostly useful for definitions and\nunnecessary for the declarations. Silent the clang\nerrors by removing it from sev.h\n\nSigned-off-by: Vaishali Thakkar ","shortMessageHtmlLink":"Fix the errors reported by clang"}},{"before":"427d0841a2cb8297da1f8f750ca33e9cf87f088b","after":"65ca7062d51c7e4d8b137624f6913184eb2d6dca","ref":"refs/heads/hyper_sev_4.19","pushedAt":"2024-08-29T15:57:32.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"andSmv","name":null,"path":"/andSmv","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/97741779?s=80&v=4"},"commit":{"message":"Add an hypercall to manage SEV guest from dom0 toolstack\n\nSigned-off-by: andSmv ","shortMessageHtmlLink":"Add an hypercall to manage SEV guest from dom0 toolstack"}},{"before":"7ee8329d90ea1052ea838449083ea18c4427c13a","after":"427d0841a2cb8297da1f8f750ca33e9cf87f088b","ref":"refs/heads/hyper_sev_4.19","pushedAt":"2024-08-29T15:55:40.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"andSmv","name":null,"path":"/andSmv","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/97741779?s=80&v=4"},"commit":{"message":"Signed-off-by: andSmv \n\nAvoid to be too verbose in PCI passthrough driver","shortMessageHtmlLink":"Signed-off-by: andSmv <andrei.semenov@vates.tech>"}},{"before":"82f99252fa9b662885e067cd8e079de5c54db136","after":"7ee8329d90ea1052ea838449083ea18c4427c13a","ref":"refs/heads/hyper_sev_4.19","pushedAt":"2024-08-29T15:51:53.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"andSmv","name":null,"path":"/andSmv","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/97741779?s=80&v=4"},"commit":{"message":"Resolve merging conflict (ASID __test_and_set_bit)\n\nSigned-off-by: andSmv ","shortMessageHtmlLink":"Resolve merging conflict (ASID __test_and_set_bit)"}},{"before":null,"after":"82f99252fa9b662885e067cd8e079de5c54db136","ref":"refs/heads/hyper_sev_4.19","pushedAt":"2024-08-27T13:19:39.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"Implemented Amd Secure Processor device driver\n\nSigned-off-by: Andrei Semenov ","shortMessageHtmlLink":"Implemented Amd Secure Processor device driver"}},{"before":"36e4b2d19637b5609a162b7bc9911f12af83bd12","after":"566b12ff88afff6a5aea2369c3cd04e94afc5c01","ref":"refs/heads/hyper_sev","pushedAt":"2024-08-21T09:22:59.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"Implemented Amd Secure Processor device driver\n\nSigned-off-by: Andrei Semenov ","shortMessageHtmlLink":"Implemented Amd Secure Processor device driver"}},{"before":null,"after":"5501213feab0c063067de49d5c7d90586a90d487","ref":"refs/heads/asp-driver","pushedAt":"2024-08-21T09:00:10.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"andSmv","name":null,"path":"/andSmv","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/97741779?s=80&v=4"},"commit":{"message":"Implemented Amd Secure Processor device driver\n\nSigned-off-by: Andrei Semenov ","shortMessageHtmlLink":"Implemented Amd Secure Processor device driver"}},{"before":"98a462f8b169f93ab7463023f0ed94575f8225b4","after":"1e2a5f991f86979b89aa9a60ca3ba8106ee7d987","ref":"refs/heads/master","pushedAt":"2024-08-19T07:29:47.000Z","pushType":"push","commitsCount":20,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"automation: add default QEMU_TIMEOUT value if not already set\n\nThe expectation is that QEMU_TIMEOUT should be set as a Gitlab CI/CD\nvariable but if not we should be able to run the pipeline anyway.\n\nSigned-off-by: Stefano Stabellini \nReviewed-by: Michal Orzel ","shortMessageHtmlLink":"automation: add default QEMU_TIMEOUT value if not already set"}},{"before":"c23d4c2afbf8831d51a9a4ee7c30f8bdf6d86d71","after":"36e4b2d19637b5609a162b7bc9911f12af83bd12","ref":"refs/heads/hyper_sev","pushedAt":"2024-08-16T12:26:35.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"IRQ: Drop regs parameter from sp_interrupt_handler\n\nIn February, 2024 Xen moved away from using regs parameter from handler functions. Adapt this change in out ASP driver.\n\nReference commit: 4da40a267a236d785d70ce6de88bb86846b64ccc\n\nSigned-off-by: Vaishali Thakkar ","shortMessageHtmlLink":"IRQ: Drop regs parameter from sp_interrupt_handler"}},{"before":null,"after":"c23d4c2afbf8831d51a9a4ee7c30f8bdf6d86d71","ref":"refs/heads/hyper_sev","pushedAt":"2024-08-16T08:44:54.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"Implemented AMD Secure Processor Driver.\n\nSigned-off-by: Andrei Semenov ","shortMessageHtmlLink":"Implemented AMD Secure Processor Driver."}},{"before":"8512ff4c4d78fcd59e6f3185d8a5abd9ef3168b8","after":"b1609d57f098515e24bbad40cf24bb3d714dc9ac","ref":"refs/heads/global_allocator_upstream_rfcv2","pushedAt":"2024-08-14T14:53:20.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"x86/hvm: Introduce Xen-wide ASID allocator\n\nCurrently ASID generation and management is done per-PCPU. This\nscheme is incompatible with SEV technologies as SEV VMs need to\nhave a fixed ASID associated with all vcpus of the VM throughout\nit's lifetime.\n\nThis commit introduces a Xen-wide allocator which initializes\nthe asids at the start of xen and allows to have a fixed asids\nthroughout the lifecycle of all domains. Having a fixed asid\nfor non-SEV domains also presents us with the opportunity to\nfurther take use of AMD instructions like TLBSYNC and INVLPGB\nfor broadcasting the TLB invalidations.\n\nSigned-off-by: Vaishali Thakkar \n---\nChanges since v1:\n - Introudce hvm_asid_bitmap as discussed at Xen-summit\n - Introduce hvm_reclaim_bitmap for reusing ASIDs\n - Assign the asid to the domain at the domain creation via\n hvm_asid_domain_create\n - Corrected the use of CPUID in the svm_asid_init function\n - Adjusted the code in nested virtualization related files\n to use new scheme. As discussed at the Xen-summit, this\n is not tested.\n - Addressed Jan's comments about using uniform style for\n accessing domains via v->domain\n - Allow to flush at the vcpu level in HAP code\n - Documented the sketch of implementation for the new scheme\n - Remove min_asid as for this patch, we are not demonstarting\n it's usecase\n - Arrange includes in multiple files as per Jan's feedback","shortMessageHtmlLink":"x86/hvm: Introduce Xen-wide ASID allocator"}},{"before":"ded5474718a84366dac80aae039a693b66fa7e2e","after":"98a462f8b169f93ab7463023f0ed94575f8225b4","ref":"refs/heads/master","pushedAt":"2024-08-14T08:40:53.000Z","pushType":"push","commitsCount":21,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"automation: add \"expect\" to containers used to run QEMU tests\n\nIt will be used for QEMU tests.\n\nSigned-off-by: Stefano Stabellini \nReviewed-by: Michal Orzel ","shortMessageHtmlLink":"automation: add \"expect\" to containers used to run QEMU tests"}},{"before":null,"after":"8512ff4c4d78fcd59e6f3185d8a5abd9ef3168b8","ref":"refs/heads/global_allocator_upstream_rfcv2","pushedAt":"2024-08-14T08:40:02.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"x86/hvm: Introduce Xen-wide ASID allocator\n\nCurrently ASID generation and management is done per-PCPU. This\nscheme is incompatible with SEV technologies as SEV VMs need to\nhave a fixed ASID associated with all vcpus of the VM throughout\nit's lifetime.\n\nThis commit introduces a Xen-wide allocator which initializes\nthe asids at the start of xen and allows to have a fixed asids\nthroughout the lifecycle of all domains. Having a fixed asid\nfor non-SEV domains also presents us with the opportunity to\nfurther take use of AMD instructions like TLBSYNC and INVLPGB\nfor broadcasting the TLB invalidations.\n\nSigned-off-by: Vaishali Thakkar \n---\nChanges since v1:\n - Introudce hvm_asid_bitmap as discussed at Xen-summit\n - Introduce hvm_reclaim_bitmap for reusing ASIDs\n - Assign the asid to the domain at the domain creation via\n hvm_asid_domain_create\n - Corrected the use of CPUID in the svm_asid_init function\n - Adjusted the code in nested virtualization related files\n to use new scheme. As discussed at the Xen-summit, this\n is not tested.\n - Addressed Jan's comments about using uniform style for\n accessing domains via v->domain\n - Allow to flush at the vcpu level in HAP code\n - Documented the sketch of implementation for the new scheme\n - Remove min_asid as for this patch, we are not demonstarting\n it's usecase\n - Arrange includes in multiple files as per Jan's feedback","shortMessageHtmlLink":"x86/hvm: Introduce Xen-wide ASID allocator"}},{"before":"c2d5e63c7380c7cb435d00211b512c53accb528e","after":"ded5474718a84366dac80aae039a693b66fa7e2e","ref":"refs/heads/master","pushedAt":"2024-08-04T13:30:16.000Z","pushType":"push","commitsCount":266,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"docs/misra: add R13.2 and R18.2 to rules.rst\n\nAdd MISRA C rules 13.2 and 18.2 to rules.rst. Both rules have zero\nviolations reported by Eclair but they have some cautions. We accept\nboth rules and for now we'll enable scanning for them in Eclair but only\nviolations will cause the Gitlab CI job to fail (cautions will not.)\n\nSigned-off-by: Stefano Stabellini \nAcked-by: Bertrand Marquis ","shortMessageHtmlLink":"docs/misra: add R13.2 and R18.2 to rules.rst"}},{"before":null,"after":"d63add7e86b6131826d1d40d28068988ef8c10cb","ref":"refs/heads/global_allocator_upstream_rfcv1","pushedAt":"2024-07-10T09:44:09.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"x86/hvm: Introduce Xen-wide ASID Allocator\n\nCurrently ASID generation and management is done per-PCPU. This\nscheme is incompatible with SEV technologies as SEV VMs need to\nhave a fixed ASID associated with all vcpus of the VM throughout\nit's lifetime.\n\nThis commit introduces a Xen-wide allocator which initializes\nthe asids at the start of xen and allows to have a fixed asids\nthroughout the lifecycle of all domains. Having a fixed asid\nfor non-SEV domains also presents us with the opportunity to\nfurther take use of AMD instructions like TLBSYNC and INVLPGB\nfor broadcasting the TLB invalidations.\n\nSigned-off-by: Vaishali Thakkar ","shortMessageHtmlLink":"x86/hvm: Introduce Xen-wide ASID Allocator"}},{"before":"21611c68702dae2e18cb519a6e166cdceeaff4ca","after":"c2d5e63c7380c7cb435d00211b512c53accb528e","ref":"refs/heads/master","pushedAt":"2024-06-03T11:40:44.000Z","pushType":"push","commitsCount":88,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"xen: fix MISRA regressions on rule 20.9 and 20.12\n\nCommit ea59e7d780d9 (\"xen/bitops: Cleanup and new infrastructure ahead of\nrearrangements\") introduced new violations on previously clean rules 20.9 and\n20.12 (clean on ARM only, right now).\n\nThe first is introduced because CONFIG_CC_IS_CLANG in xen/self-tests.h is not\ndefined in the configuration under analysis. Using \"defined()\" instead avoids\nrelying on the preprocessor's behaviour upon encountering an undedfined identifier\nand addresses the violation.\n\nThe violation of Rule 20.12 is due to \"val\" being used both as an ordinary argument\nin macro RUNTIME_CHECK, and as a stringification operator.\n\nNo functional change.\n\nFixes: ea59e7d780d9 (\"xen/bitops: Cleanup and new infrastructure ahead of rearrangements\")\nSigned-off-by: Nicola Vetrini \nAcked-by: Andrew Cooper ","shortMessageHtmlLink":"xen: fix MISRA regressions on rule 20.9 and 20.12"}},{"before":"9e30bd8f4a8cee83368276c5149c7e2304efe5a2","after":"21611c68702dae2e18cb519a6e166cdceeaff4ca","ref":"refs/heads/master","pushedAt":"2024-05-19T07:24:07.000Z","pushType":"push","commitsCount":82,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"include/ctype.h: fix MISRA R10.2 violation\n\nThe value returned by __toupper is used in arithmetic operations causing\nMISRA C 10.2 violations. Cast to plain char in the toupper macro. Also\ndo the same in tolower for consistency.\n\nSigned-off-by: Stefano Stabellini \nAcked-by: Jan Beulich ","shortMessageHtmlLink":"include/ctype.h: fix MISRA R10.2 violation"}},{"before":"09cb855f33fb619c87d8d4250d3a980f568f151b","after":"9e30bd8f4a8cee83368276c5149c7e2304efe5a2","ref":"refs/heads/master","pushedAt":"2024-05-02T08:51:28.000Z","pushType":"push","commitsCount":69,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"x86/cpu-policy: Annotate the accumulated features\n\nSome features need accumulating rather than intersecting to make migration\nsafe. Introduce the new '|' attribute for this purpose.\n\nRight now, it's only used by the Xapi toolstack, but it will be used by\nxl/libxl when the full policy-object work is complete, and until then it's\nstill a useful hint for hand-crafted cpuid= lines in vm.cfg files.\n\nSigned-off-by: Andrew Cooper \nReviewed-by: Jan Beulich ","shortMessageHtmlLink":"x86/cpu-policy: Annotate the accumulated features"}},{"before":"402c2d3e66a6bc9481dcabfc8697750dc4beabed","after":"09cb855f33fb619c87d8d4250d3a980f568f151b","ref":"refs/heads/master","pushedAt":"2024-04-22T11:35:53.000Z","pushType":"push","commitsCount":82,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"x86/svm: Add flushbyasid in the supported features\n\nTLB Flush by ASID is missing in the list of supported features\nhere. So, add it.\n\nSigned-off-by: Vaishali Thakkar \nAcked-by: Andrew Cooper ","shortMessageHtmlLink":"x86/svm: Add flushbyasid in the supported features"}},{"before":"9fd06fe4a68f9135c7373369588e4619a7b2a310","after":"1ebf32a8d7aa3618db92661d52b369f97e83221d","ref":"refs/heads/asid_hyperopenx","pushedAt":"2024-04-22T08:42:47.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"x86/hvm/svm: Asid fixes for the encrypted VMs\n\nTemporary solution until new global ASID allocator is merged\nin upstream. This commit also adds a change that allows the\ndynamic start of ASID allocation via min_asid. This is\nuseful for the SEV domains.\n\nSigned-off-by: Vaishali Thakkar ","shortMessageHtmlLink":"x86/hvm/svm: Asid fixes for the encrypted VMs"}},{"before":"ff7cf7af8b09dc6353388f9f7d18e0e1a0cd9724","after":"9fd06fe4a68f9135c7373369588e4619a7b2a310","ref":"refs/heads/asid_hyperopenx","pushedAt":"2024-04-22T08:40:12.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"x86/hvm/svm: Asid fixes for the encrypted VMs\n\nTemporary solution until new global ASID allocator is merged\nin upstream. This commit also adds a change that allows the\ndynamic start of ASID allocation via min_asid. This is\nuseful for the SEV domains.\n\nSigned-off-by: Vaishali Thakkar ","shortMessageHtmlLink":"x86/hvm/svm: Asid fixes for the encrypted VMs"}},{"before":null,"after":"ff7cf7af8b09dc6353388f9f7d18e0e1a0cd9724","ref":"refs/heads/asid_hyperopenx","pushedAt":"2024-04-22T07:22:03.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"x86/hvm: Allow supplying a dynamic start ASID\n\nCurrently, Xen always starts the ASID allocation at 1. But\nfor SEV technologies the ASID space is divided. This is\nbecause it's a security issue if a guest is started as\nES/SNP and is migrated to SEV-only. So, the types are\ntracked explicitly.\n\nThus, in preparation of SEV support in Xen, add min_asid\nto allow supplying the dynamic start ASID during the\nallocation process.\n\nSigned-off-by: Vaishali Thakkar ","shortMessageHtmlLink":"x86/hvm: Allow supplying a dynamic start ASID"}},{"before":"7a09966e7b2823b70f6d56d0cf66c11124f4a3c1","after":"402c2d3e66a6bc9481dcabfc8697750dc4beabed","ref":"refs/heads/master","pushedAt":"2024-04-08T20:31:37.000Z","pushType":"push","commitsCount":30,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"MISRA C Rule 17.1 states: \"The features of `' shall not be used\"\n\nThe Xen community wants to avoid using variadic functions except for\nspecific circumstances where it feels appropriate by strict code review.\n\nFunctions hypercall_create_continuation and hypercall_xlat_continuation\nare internal helper functions made to break long running hypercalls into\nmultiple calls. They take a variable number of arguments depending on the\noriginal hypercall they are trying to continue.\n\nAdd SAF deviations for the aforementioned functions.\n\nSigned-off-by: Simone Ballarin \nReviewed-by: Stefano Stabellini ","shortMessageHtmlLink":"MISRA C Rule 17.1 states: \"The features of `<stdarg.h>' shall not be …"}},{"before":"6f6de10ade5ade907f9e3f3c72b7b18f7852d9ff","after":"7a09966e7b2823b70f6d56d0cf66c11124f4a3c1","ref":"refs/heads/master","pushedAt":"2024-04-03T18:45:08.000Z","pushType":"push","commitsCount":15,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"x86/spec-ctrl: Move __read_mostly data into __ro_after_init\n\nThese variables predate the introduction of __ro_after_init, but all qualify.\nUpdate them to be consistent with the rest of the file.\n\nNo functional change.\n\nSigned-off-by: Andrew Cooper \nReviewed-by: Jan Beulich ","shortMessageHtmlLink":"x86/spec-ctrl: Move __read_mostly data into __ro_after_init"}},{"before":"78398afae10bfb4ab94e8af17b7ed58510a57d96","after":"6f6de10ade5ade907f9e3f3c72b7b18f7852d9ff","ref":"refs/heads/master","pushedAt":"2024-03-26T13:54:32.000Z","pushType":"push","commitsCount":215,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"xen/xsm: add parentheses to comply with MISRA C Rule 20.7\n\nMISRA C Rule 20.7 states: \"Expressions resulting from the expansion\nof macro parameters shall be enclosed in parentheses\". Therefore, some\nmacro definitions should gain additional parentheses to ensure that all\ncurrent and future users will be safe with respect to expansions that\ncan possibly alter the semantics of the passed-in macro parameter.\n\nNo functional change.\n\nSigned-off-by: Nicola Vetrini \nReviewed-by: Stefano Stabellini \nAcked-by: Daniel P. Smith ","shortMessageHtmlLink":"xen/xsm: add parentheses to comply with MISRA C Rule 20.7"}},{"before":"2d1d8c7b224d65f1733392d255460c8e26b9c2bd","after":"022512fe9523145ba17966902e760712c032a48a","ref":"refs/heads/amd_sev_xen","pushedAt":"2024-03-15T16:13:52.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"andSmv","name":null,"path":"/andSmv","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/97741779?s=80&v=4"},"commit":{"message":"Implemented AMD Secure Processor Driver.\n\nSigned-off-by: Andrei Semenov ","shortMessageHtmlLink":"Implemented AMD Secure Processor Driver."}},{"before":"f3f6c500e2dbd23af77c207e2cf4b496fffa1b0d","after":"78398afae10bfb4ab94e8af17b7ed58510a57d96","ref":"refs/heads/master","pushedAt":"2024-02-17T09:07:27.000Z","pushType":"push","commitsCount":148,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"tools/xen-9pfsd: add 9pfs read request support\n\nAdd the read request of the 9pfs protocol.\n\nSigned-off-by: Juergen Gross \nReviewed-by: Jason Andryuk \nAcked-by: Anthony PERARD ","shortMessageHtmlLink":"tools/xen-9pfsd: add 9pfs read request support"}},{"before":"49818cde637b5ec20383e46b71f93b2e7d867686","after":"f3f6c500e2dbd23af77c207e2cf4b496fffa1b0d","ref":"refs/heads/master","pushedAt":"2024-01-17T14:26:23.000Z","pushType":"push","commitsCount":29,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"xen/arm64: head: Allow to use early printk while on 1:1 mapping\n\nTake an example from commit 1ec3fe1f664f (\"xen/arm32: head: Improve\nlogging in head.S\") to add support for printing early boot messages\nwhile running on identity mapping:\n - define PRINT_SECT() macro to be able to specify a section for storing\n a string. PRINT() will use .rodata.str and PRINT_ID() - .rodata.idmap.\n This is necessary, because when running on identity mapping, the\n strings need to be part of the first page that is mapped,\n - move loading a runtime virtual UART address right after enabling MMU\n (the corresponding steps repeated in {primary,secondary}_switched are\n now consolidated in a single place),\n - move early printk 'hex' string into .rodata.idmap and replace 'adr'\n instruction in asm_putn with 'adr_l' to extend the addressable range,\n - remove RODATA_STR() macro given no use.\n\nSigned-off-by: Michal Orzel ","shortMessageHtmlLink":"xen/arm64: head: Allow to use early printk while on 1:1 mapping"}},{"before":null,"after":"2d1d8c7b224d65f1733392d255460c8e26b9c2bd","ref":"refs/heads/amd_sev_xen","pushedAt":"2024-01-16T15:07:56.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"Xen: Add AMD SME and SEV initialization\n\nSigned-off-by: Vaishali Thakkar ","shortMessageHtmlLink":"Xen: Add AMD SME and SEV initialization"}},{"before":"7befef87cc9b1bb8ca15d866ce1ecd9165ccb58c","after":"49818cde637b5ec20383e46b71f93b2e7d867686","ref":"refs/heads/master","pushedAt":"2024-01-02T08:56:10.000Z","pushType":"push","commitsCount":349,"pusher":{"login":"v-thakkar","name":"Vaishali Thakkar","path":"/v-thakkar","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7105009?s=80&v=4"},"commit":{"message":"xen: remove asm/unaligned.h\n\nWith include/xen/unaligned.h now dealing properly with unaligned\naccesses for all architectures, asm/unaligned.h can be removed and\nusers can be switched to include xen/unaligned.h instead.\n\nSigned-off-by: Juergen Gross \nReviewed-by: Jan Beulich ","shortMessageHtmlLink":"xen: remove asm/unaligned.h"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAErHcU5QA","startCursor":null,"endCursor":null}},"title":"Activity · xcp-ng/xen"}