diff --git a/IDE/STM32CUBE/wolftpm_test.c b/IDE/STM32CUBE/wolftpm_test.c
index fc2c89a4..10f1e768 100644
--- a/IDE/STM32CUBE/wolftpm_test.c
+++ b/IDE/STM32CUBE/wolftpm_test.c
@@ -18,6 +18,9 @@
* along with wolfTPM. If not, see .
*/
+#ifdef HAVE_CONFIG_H
+ #include
+#endif
#include "wolftpm_test.h"
#ifndef SINGLE_THREADED
@@ -45,7 +48,7 @@ void wolfTPMTest(const void* argument)
printf("Running wolfTPM Wrap Test...\n");
/* Run wolfTPM wrap test */
- ret = TPM2_Wrapper_Test(NULL);
+ ret = TPM2_Wrapper_Test(argument);
printf("wolfTPM wrap test: Return code %d\n", ret);
diff --git a/IDE/STM32CUBE/wolftpm_test.h b/IDE/STM32CUBE/wolftpm_test.h
index 7e466660..c2a1a077 100644
--- a/IDE/STM32CUBE/wolftpm_test.h
+++ b/IDE/STM32CUBE/wolftpm_test.h
@@ -21,9 +21,7 @@
#ifndef WOLFTPM_TEST_H_
#define WOLFTPM_TEST_H_
-#ifdef HAVE_CONFIG_H
- #include
-#endif
+#include
#ifndef SINGLE_THREADED
#include
diff --git a/hal/tpm_io.h b/hal/tpm_io.h
index 3cc8b25a..411b747a 100644
--- a/hal/tpm_io.h
+++ b/hal/tpm_io.h
@@ -66,7 +66,7 @@
#ifdef WOLFTPM_EXAMPLE_HAL
#ifdef WOLFTPM_ADV_IO
-WOLFTPM_API int TPM2_IoCb(TPM2_CTX*, int isRead, word32 addr, byte* buf, word16 size,
+WOLFTPM_API int TPM2_IoCb(TPM2_CTX* ctx, int isRead, word32 addr, byte* buf, word16 size,
void* userCtx);
#else
WOLFTPM_API int TPM2_IoCb(TPM2_CTX* ctx, const byte* txBuf, byte* rxBuf,
diff --git a/hal/tpm_io_linux.c b/hal/tpm_io_linux.c
index cc5bd962..5ca01e89 100644
--- a/hal/tpm_io_linux.c
+++ b/hal/tpm_io_linux.c
@@ -109,7 +109,7 @@
int rc;
struct i2c_rdwr_ioctl_data rdwr;
struct i2c_msg msgs[2];
- unsigned char buf[2];
+ unsigned char buf[1];
int timeout = TPM_I2C_TRIES;
rdwr.msgs = msgs;
diff --git a/hal/tpm_io_st.c b/hal/tpm_io_st.c
index 053c808a..1764b27d 100644
--- a/hal/tpm_io_st.c
+++ b/hal/tpm_io_st.c
@@ -38,54 +38,93 @@
defined(WOLFTPM_WINAPI) )
#if defined(WOLFSSL_STM32_CUBEMX)
- #ifdef WOLFTPM_I2C
+#ifdef WOLFTPM_I2C
+ #ifndef TPM_I2C_TRIES
+ #define TPM_I2C_TRIES 10
+ #endif
+ #ifndef TPM2_I2C_ADDR
#define TPM2_I2C_ADDR 0x2e
+ #endif
+ #ifndef STM32_CUBEMX_I2C_TIMEOUT
+ #define STM32_CUBEMX_I2C_TIMEOUT 250 /* ticks/ms */
+ #endif
+
/* STM32 CubeMX HAL I2C */
- #define STM32_CUBEMX_I2C_TIMEOUT 250
static int i2c_read(void* userCtx, word32 reg, byte* data, int len)
{
- int rc;
- int i2cAddr = (TPM2_I2C_ADDR << 1) | 0x01; /* For I2C read LSB is 1 */
- byte buf[MAX_SPI_FRAMESIZE+1];
+ int ret = TPM_RC_FAILURE;
+ HAL_StatusTypeDef status;
I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)userCtx;
+ int i2cAddr = (TPM2_I2C_ADDR << 1) | 0x01; /* For I2C read LSB is 1 */
+ int timeout = TPM_I2C_TRIES;
+ byte buf[1];
/* TIS layer should never provide a buffer larger than this,
but double check for good coding practice */
if (len > MAX_SPI_FRAMESIZE)
return BAD_FUNC_ARG;
- buf[0] = (reg & 0xFF);
- rc = HAL_I2C_Master_Receive(&hi2c, i2cAddr, data, len, STM32_CUBEMX_I2C_TIMEOUT);
-
- if (rc != -1) {
- XMEMCPY(data, buf+1, len);
- return TPM_RC_SUCCESS;
+ buf[0] = (reg & 0xFF); /* convert to simple 8-bit address for I2C */
+
+ /* The I2C takes about 80us to wake up and will NAK until it is ready */
+ do {
+ /* Write address to read from - retry until ack */
+ status = HAL_I2C_Master_Transmit(hi2c, i2cAddr, buf, sizeof(buf),
+ STM32_CUBEMX_I2C_TIMEOUT);
+ HAL_Delay(1); /* guard time - should be 250us */
+ } while (status != HAL_OK && --timeout > 0);
+ if (status == HAL_OK) {
+ timeout = TPM_I2C_TRIES;
+ /* Perform read with retry */
+ do {
+ status = HAL_I2C_Master_Receive(hi2c, i2cAddr, data, len,
+ STM32_CUBEMX_I2C_TIMEOUT);
+ if (status != HAL_OK)
+ HAL_Delay(1); /* guard time - should be 250us */
+ } while (status != HAL_OK && --timeout > 0);
}
-
- return TPM_RC_FAILURE;
+ if (status == HAL_OK) {
+ ret = TPM_RC_SUCCESS;
+ }
+ else {
+ printf("I2C Read failure %d (tries %d)\n",
+ status, TPM_I2C_TRIES - timeout);
+ }
+ return ret;
}
static int i2c_write(void* userCtx, word32 reg, byte* data, int len)
{
- int rc;
+ int ret = TPM_RC_FAILURE;
+ HAL_StatusTypeDef status;
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)userCtx;
int i2cAddr = (TPM2_I2C_ADDR << 1); /* I2C write operation, LSB is 0 */
+ int timeout = TPM_I2C_TRIES;
byte buf[MAX_SPI_FRAMESIZE+1];
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)userCtx;
/* TIS layer should never provide a buffer larger than this,
but double check for good coding practice */
if (len > MAX_SPI_FRAMESIZE)
return BAD_FUNC_ARG;
- buf[0] = (reg & 0xFF); /* TPM register address */
+ /* Build packet with TPM register and data */
+ buf[0] = (reg & 0xFF); /* convert to simple 8-bit address for I2C */
XMEMCPY(buf + 1, data, len);
- rc = HAL_I2C_Master_Transmit(&hi2c, TPM2_I2C_ADDR << 1, buf, len);
- if (rc != -1) {
- return TPM_RC_SUCCESS;
+ /* The I2C takes about 80us to wake up and will NAK until it is ready */
+ do {
+ status = HAL_I2C_Master_Transmit(hi2c, i2cAddr, buf, len+1,
+ STM32_CUBEMX_I2C_TIMEOUT);
+ if (status != HAL_OK)
+ HAL_Delay(1); /* guard time - should be 250us */
+ } while (status != HAL_OK && --timeout > 0);
+ if (status == HAL_OK) {
+ ret = TPM_RC_SUCCESS;
}
-
- return TPM_RC_FAILURE;
+ else {
+ printf("I2C Write failure %d\n", status);
+ }
+ return ret;
}
int TPM2_IoCb_STCubeMX_I2C(TPM2_CTX* ctx, int isRead, word32 addr,
@@ -105,7 +144,7 @@
return ret;
}
- #else /* STM32 CubeMX Hal SPI */
+#else /* STM32 CubeMX Hal SPI */
#define STM32_CUBEMX_SPI_TIMEOUT 250
int TPM2_IoCb_STCubeMX_SPI(TPM2_CTX* ctx, const byte* txBuf, byte* rxBuf,
word16 xferSz, void* userCtx)
@@ -178,7 +217,7 @@
return ret;
}
- #endif /* WOLFTPM_I2C */
+#endif /* WOLFTPM_I2C */
#endif
#endif /* !(WOLFTPM_LINUX_DEV || WOLFTPM_SWTPM || WOLFTPM_WINAPI) */
#endif /* WOLFTPM_INCLUDE_IO_FILE */