fairly large reconstruction

Author: rondelion

README.md

@@ -32,13 +32,13 @@ Import libraries:
 
 Instantiate brical.NetworkBuilder.
 
-	>>>> nb=brical.NetworkBuilder()
+	>>> nb=brical.NetworkBuilder()
 
 Load JSON files:
 
 In this example, you load six files from 'test/n001' directory.
 
-	>>>> f = open("[YOUR GIT DIRECTORY]/brical/test/n001/01InputComponent.json")
+	>>> f = open("[YOUR GIT DIRECTORY]/brical/test/n001/01InputComponent.json")
 	>>> nb.load_file(f)
 	True
 	>>> f = open("[YOUR GIT DIRECTORY]/brical/test/n001/02MainComponent.json")
@@ -76,11 +76,11 @@ BriCA modules are accessed via the module dictionary obtained with agent_builder
 Setting non-zero values to the input module:
 
 	>>> v = np.array([1, 2, 3], dtype=np.int16)
-	>>> modules["BriCA1.InputModule"].get_component("BriCA1.InputModule").set_state("InputModulePort", v)
+	>>> modules["BriCA1.InputModule"].set_state("InputModulePort", v)
 
 Setting a map for PipeComponent (see BriCA1 tutorial for explanation):
 
-	>>>> modules["BriCA1.MainModule"].get_component("BriCA1.MainModule").set_map("Port1", "Port2")
+	>>> modules["BriCA1.MainModule"].set_map("Port1", "Port2")
 
 Now run the network step by step and see if values are transmitted to the ports:
 

test.py

@@ -46,7 +46,6 @@ def print_network(network):
 
 agent_builder = brical.AgentBuilder()
 agent = agent_builder.create_agent(network_builder)
-scheduler = brica1.VirtualTimeSyncScheduler(agent)
 if agent == agent_builder.INCONSISTENT:
     sys.stderr.write("ERROR: INCONSISTENT!\n")
 elif agent == agent_builder.NOT_GROUNDED:
@@ -67,7 +66,7 @@ def print_network(network):
     impl = v["ImplClass"]
     if impl == "":
         continue
-    component = modules[module].get_component(module)
+    component = modules[module]
     ports = v["Ports"]
     buffers.append([module, component, ports])
     if "InputModule" in module:  # Setting of initial data
@@ -98,6 +97,7 @@ def print_network(network):
 
 # Run
 print("--- Run ---")
+scheduler = brica1.VirtualTimeSyncScheduler(agent)
 for i in range(len(buffers)):
     print(scheduler.step())
     for b in buffers:

test/n001/01InputComponent.json

@@ -3,7 +3,7 @@
 "Type" : "C",
 "Name" : "InputComponent",
 "Base" : "BriCA1",
-"Comment" : "正常系：サンプルデータが正常に動作することを確認"
+"Comment" : "Normal case: to confirm BriCAL works with test case n001"
 },
 
 "Modules" : [{