From 9d200e591985139539ff9cddc9d2ab6f25120134 Mon Sep 17 00:00:00 2001 From: wagiminator Date: Fri, 19 May 2023 17:26:34 +0200 Subject: [PATCH] Initial commit --- LICENSE | 3 + README.md | 66 +- documentation/DAPLink_CMSIS-DAP.png | Bin 0 -> 89005 bytes documentation/DAPLink_pic1.jpg | Bin 0 -> 96458 bytes documentation/DAPLink_pic2.jpg | Bin 0 -> 113271 bytes documentation/DAPLink_pic3.jpg | Bin 0 -> 95825 bytes documentation/DAPLink_pic4.jpg | Bin 0 -> 145706 bytes hardware/DAPLink_BOM.tsv | Bin 0 -> 2326 bytes hardware/DAPLink_gerber.zip | Bin 0 -> 44330 bytes hardware/DAPLink_schematic.pdf | Bin 0 -> 105207 bytes software/daplink.bin | Bin 0 -> 11256 bytes software/daplink.c | 102 ++ software/makefile | 88 ++ software/src/ch554.h | 758 ++++++++++++++ software/src/config.h | 31 + software/src/dap.c | 1504 +++++++++++++++++++++++++++ software/src/dap.h | 204 ++++ software/src/dap_io.h | 145 +++ software/src/delay.c | 86 ++ software/src/delay.h | 161 +++ software/src/gpio.h | 288 +++++ software/src/system.h | 200 ++++ software/src/uart.c | 28 + software/src/uart.h | 57 + software/src/usb.h | 332 ++++++ software/src/usb_cdc.c | 184 ++++ software/src/usb_cdc.h | 32 + software/src/usb_descr.c | 212 ++++ software/src/usb_descr.h | 92 ++ software/src/usb_handler.c | 465 +++++++++ software/src/usb_handler.h | 52 + software/src/usb_hid.c | 61 ++ software/src/usb_hid.h | 8 + software/tools/chprog.py | 327 ++++++ 34 files changed, 5484 insertions(+), 2 deletions(-) create mode 100644 LICENSE create mode 100644 documentation/DAPLink_CMSIS-DAP.png create mode 100644 documentation/DAPLink_pic1.jpg create mode 100644 documentation/DAPLink_pic2.jpg create mode 100644 documentation/DAPLink_pic3.jpg create mode 100644 documentation/DAPLink_pic4.jpg create mode 100644 hardware/DAPLink_BOM.tsv create mode 100644 hardware/DAPLink_gerber.zip create mode 100644 hardware/DAPLink_schematic.pdf create mode 100644 software/daplink.bin create mode 100644 software/daplink.c create mode 100755 software/makefile create mode 100755 software/src/ch554.h create mode 100755 software/src/config.h create mode 100644 software/src/dap.c create mode 100644 software/src/dap.h create mode 100644 software/src/dap_io.h create mode 100755 software/src/delay.c create mode 100755 software/src/delay.h create mode 100644 software/src/gpio.h create mode 100644 software/src/system.h create mode 100644 software/src/uart.c create mode 100644 software/src/uart.h create mode 100755 software/src/usb.h create mode 100755 software/src/usb_cdc.c create mode 100755 software/src/usb_cdc.h create mode 100755 software/src/usb_descr.c create mode 100755 software/src/usb_descr.h create mode 100755 software/src/usb_handler.c create mode 100755 software/src/usb_handler.h create mode 100644 software/src/usb_hid.c create mode 100644 software/src/usb_hid.h create mode 100755 software/tools/chprog.py diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..373df33 --- /dev/null +++ b/LICENSE @@ -0,0 +1,3 @@ +This work is licensed under the Creative Commons Attribution-ShareAlike 3.0 Unported License. +To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/3.0/ or send +a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA. diff --git a/README.md b/README.md index e16a228..83bf7a1 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,64 @@ -# CH552-DAPLink -CMSIS-DAP compliant debugging probe with SWD, JTAG, and VCP support +# CH552 DAPLink +The DAPLink, based on the CH552 microcontroller, is a debugging probe that follows the CMSIS-DAP standard. It supports both SWD and JTAG protocols, making it suitable for programming Microchip SAM and other ARM-based microcontrollers. In addition, it includes a Virtual COM Port (VCP) which adds an extra debugging capability. The SWD firmware is derived from [Ralph Doncaster's](https://github.com/nerdralph/ch554_sdcc/tree/master/examples/CMSIS_DAP) DAPLink implementation for CH55x microcontrollers, along with Deqing Sun's [CH55xduino](https://github.com/DeqingSun/ch55xduino) port. + +![DAPLink_pic1.jpg](https://raw.githubusercontent.com/wagiminator/CH552-DAPLink/main/documentation/DAPLink_pic1.jpg) + +# CMSIS-DAP +CMSIS-DAP provides a standardized way to access the Coresight Debug Access Port (DAP) of an ARM Cortex microcontroller via USB. CMSIS-DAP is generally implemented as an on-board interface chip, providing direct USB connection from a development board to a debugger running on a host computer on one side, and over JTAG (Joint Test Action Group) or SWD (Serial Wire Debug) to the target device to access the Coresight DAP on the other. As a USB HID compliant device, it typically does not require any drivers for the operating system. For more information refer to the [CMSIS-DAP Handbook](https://os.mbed.com/handbook/CMSIS-DAP). + +![CMSIS-DAP.png](https://raw.githubusercontent.com/wagiminator/CH552-DAPLink/main/documentation/DAPLink_CMSIS-DAP.png) + +# Compiling and Installing Firmware +## Preparing the CH55x Bootloader +### Installing Drivers for the CH55x Bootloader +On Linux you do not need to install a driver. However, by default Linux will not expose enough permission to upload your code with the USB bootloader. In order to fix this, open a terminal and run the following commands: + +``` +echo 'SUBSYSTEM=="usb", ATTR{idVendor}=="4348", ATTR{idProduct}=="55e0", MODE="666"' | sudo tee /etc/udev/rules.d/99-ch55x.rules +sudo service udev restart +``` + +For Windows, you need the [CH372 driver](http://www.wch-ic.com/downloads/CH372DRV_EXE.html). Alternatively, you can also use the [Zadig Tool](https://zadig.akeo.ie/) to install the correct driver. Here, click "Options" and "List All Devices" to select the USB module, and then install the libusb-win32 driver. To do this, the board must be connected and the CH55x must be in bootloader mode. + +### Entering CH55x Bootloader Mode +A brand new chip starts automatically in bootloader mode as soon as it is connected to the PC via USB. Once firmware has been uploaded, the bootloader must be started manually for new uploads. To do this, the board must first be disconnected from the USB port and all voltage sources. Now press the BOOT button and keep it pressed while reconnecting the board to the USB port of your PC. The chip now starts again in bootloader mode, the BOOT button can be released and new firmware can be uploaded within the next couple of seconds. + +## Compiling and Uploading using the makefile +### Installing SDCC Toolchain for CH55x +Install the [SDCC Compiler](https://sdcc.sourceforge.net/). In order for the programming tool to work, Python3 must be installed on your system. To do this, follow these [instructions](https://www.pythontutorial.net/getting-started/install-python/). In addition [pyusb](https://github.com/pyusb/pyusb) must be installed. On Linux (Debian-based), all of this can be done with the following commands: + +``` +sudo apt install build-essential sdcc python3 python3-pip +sudo pip install pyusb +``` + +### Compiling and Uploading Firmware +- Open a terminal. +- Navigate to the folder with the makefile. +- Connect the board and make sure the CH552 is in bootloader mode. +- Run ```make flash``` to compile and upload the firmware. +- If you don't want to compile the firmware yourself, you can also upload the precompiled binary. To do this, just run ```python3 ./tools/chprog.py daplink.bin```. + +# Operating Instructions +Connect the DAPLink to the target board via the pin header. You can supply power via the 3V3 pin or the 5V pin (max 400 mA). Plug the DAPLink into a USB port on your PC. Since it is recognized as a Human Interface Device (HID), no driver installation is required. However, Windows users may need to install a CDC driver for the Virtual COM Port (VCP) using the [Zadig Tool](https://zadig.akeo.ie/). The DAPLink should work with any debugging software that supports CMSIS-DAP (e.g. OpenOCD or PyOCD). Of course, it also works with the [SAMD DevBoards](https://github.com/wagiminator/SAMD-Development-Boards) in the Arduino IDE (Tools -> Programmer -> Generic CMSIS-DAP). The virtual COM port (8N1 only) can be used with any serial monitor. + +# References, Links and Notes +1. [EasyEDA Design Files](https://oshwlab.com/wagiminator/ch552-swd-programmer) +2. [ARMmbed DAPLink](https://github.com/ARMmbed/DAPLink) +3. [CH55xduino](https://github.com/DeqingSun/ch55xduino) +4. [Ralph Doncaster's Implementation](https://github.com/nerdralph/ch554_sdcc/tree/master/examples/CMSIS_DAP) +5. [CMSIS-DAP Handbook](https://os.mbed.com/handbook/CMSIS-DAP) +6. [SDCC Compiler](https://sdcc.sourceforge.net/) +7. [CH55x SDK for SDCC](https://github.com/Blinkinlabs/ch554_sdcc) +8. [OpenOCD](http://openocd.org/) +9. [SAMD DevBoards](https://github.com/wagiminator/SAMD-Development-Boards) +10. [picoDAP](https://github.com/wagiminator/CH552-picoDAP) + +![DAPLink_pic2.jpg](https://raw.githubusercontent.com/wagiminator/CH552-DAPLink/main/documentation/DAPLink_pic2.jpg) +![DAPLink_pic3.jpg](https://raw.githubusercontent.com/wagiminator/CH552-DAPLink/main/documentation/DAPLink_pic3.jpg) + +# License +![license.png](https://i.creativecommons.org/l/by-sa/3.0/88x31.png) + +This work is licensed under Creative Commons Attribution-ShareAlike 3.0 Unported License. +(http://creativecommons.org/licenses/by-sa/3.0/) diff --git a/documentation/DAPLink_CMSIS-DAP.png b/documentation/DAPLink_CMSIS-DAP.png new file mode 100644 index 0000000000000000000000000000000000000000..9c1c8f7496179ba446ce56ae95b567b682b51736 GIT binary patch literal 89005 zcmb5WbzBu%^e+g~jUZA=NQ!iWgrov0h%`udNJ)1J0-`i1DF{d--HkK|BGTR6&8&0Z zdo#b8|K@&fayhm4+G~AlpHQWjPw}uRu#u3E@Z_FJDR9LMa7Hp$xjX*P>E9DomFINSTaovOe`PRD$WW!5lke?j;NKEWlYSaCXPlf5v9P*se zibkC!R;sK3^M5Q6s>H4mOKiX*cVd2W1qto{d_GJn?!;aN{Ir_?@6T`l=!ucfy5*}g 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+flash: $(TARGET).bin size removetemp + @echo "Uploading to CH55x ..." + @$(WCHISP) $(TARGET).bin + +all: $(TARGET).bin $(TARGET).hex size + +hex: $(TARGET).hex size removetemp + +bin: $(TARGET).bin size removetemp + +bin-hex: $(TARGET).bin $(TARGET).hex size removetemp + +install: flash + +size: + @echo "------------------" + @echo "FLASH: $(shell awk '$$1 == "ROM/EPROM/FLASH" {print $$4}' $(TARGET).mem) bytes" + @echo "IRAM: $(shell awk '$$1 == "Stack" {print 248-$$10}' $(TARGET).mem) bytes" + @echo "XRAM: $(shell awk '$$1 == "EXTERNAL" {print $(XRAM_LOC)+$$5}' $(TARGET).mem) bytes" + @echo "------------------" + +removetemp: + @echo "Removing temporary files ..." + @$(CLEAN) + +clean: + @echo "Cleaning all up ..." + @$(CLEAN) + @rm -f $(TARGET).hex $(TARGET).bin diff --git a/software/src/ch554.h b/software/src/ch554.h new file mode 100755 index 0000000..8157295 --- /dev/null +++ b/software/src/ch554.h @@ -0,0 +1,758 @@ +/*-------------------------------------------------------------------------- +CH554.H +Header file for CH554 microcontrollers. +**************************************** +** Copyright (C) W.ch 1999-2014 ** +** Web: http://wch.cn ** +**************************************** +--------------------------------------------------------------------------*/ + +#ifndef __CH554_H__ +#define __CH554_H__ + +#define SBIT(name, addr, bit) __sbit __at(addr+bit) name +#define SFR(name, addr) __sfr __at(addr) name +#define SFRX(name, addr) __xdata volatile unsigned char __at(addr) name +#define SFR16(name, addr) __sfr16 __at(((addr+1U)<<8) | addr) name +#define SFR16E(name, fulladdr) __sfr16 __at(fulladdr) name +#define SFR32(name, addr) __sfr32 __at(((addr+3UL)<<24) | ((addr+2UL)<<16) | ((addr+1UL)<<8) | addr) name +#define SFR32E(name, fulladdr) __sfr32 __at(fulladdr) name + +/*----- SFR --------------------------------------------------------------*/ +/* sbit are bit addressable, others are byte addressable */ + +/* System Registers */ +SFR(PSW, 0xD0); // program status word + SBIT(CY, 0xD0, 7); // carry flag + SBIT(AC, 0xD0, 6); // auxiliary carry flag + SBIT(F0, 0xD0, 5); // bit addressable general purpose flag 0 + SBIT(RS1, 0xD0, 4); // register R0-R7 bank selection high bit + SBIT(RS0, 0xD0, 3); // register R0-R7 bank selection low bit +#define MASK_PSW_RS 0x18 // bit mask of register R0-R7 bank selection +// RS1 & RS0: register R0-R7 bank selection +// 00 - bank 0, R0-R7 @ address 0x00-0x07 +// 01 - bank 1, R0-R7 @ address 0x08-0x0F +// 10 - bank 2, R0-R7 @ address 0x10-0x17 +// 11 - bank 3, R0-R7 @ address 0x18-0x1F + SBIT(OV, 0xD0, 2); // overflow flag + SBIT(F1, 0xD0, 1); // bit addressable general purpose flag 1 + SBIT(P, 0xD0, 0); // ReadOnly: parity flag +SFR(ACC, 0xE0); // accumulator +SFR(B, 0xF0); // general purpose register B +SFR(SP, 0x81); // stack pointer +//sfr16 DPTR = 0x82; // DPTR pointer, little-endian +SFR(DPL, 0x82); // data pointer low +SFR(DPH, 0x83); // data pointer high +SFR(SAFE_MOD, 0xA1); // WriteOnly: writing safe mode +//sfr CHIP_ID = 0xA1; // ReadOnly: reading chip ID +#define CHIP_ID SAFE_MOD +SFR(GLOBAL_CFG, 0xB1); // global config, Write@SafeMode +#define bBOOT_LOAD 0x20 // ReadOnly: boot loader status for discriminating BootLoader or Application: set 1 by power on reset, clear 0 by software reset +#define bSW_RESET 0x10 // software reset bit, auto clear by hardware +#define bCODE_WE 0x08 // enable flash-ROM (include code & Data-Flash) being program or erasing: 0=writing protect, 1=enable program and erase +#define bDATA_WE 0x04 // enable Data-Flash (flash-ROM data area) being program or erasing: 0=writing protect, 1=enable program and erase +#define bLDO3V3_OFF 0x02 // disable 5V->3.3V LDO: 0=enable LDO for USB and internal oscillator under 5V power, 1=disable LDO, V33 pin input external 3.3V power +#define bWDOG_EN 0x01 // enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow + +/* Clock and Sleep and Power Registers */ +SFR(PCON, 0x87); // power control and reset flag +#define SMOD 0x80 // baud rate selection for UART0 mode 1/2/3: 0=slow(Fsys/128 @mode2, TF1/32 @mode1/3, no effect for TF2), + // 1=fast(Fsys/32 @mode2, TF1/16 @mode1/3, no effect for TF2) +#define bRST_FLAG1 0x20 // ReadOnly: recent reset flag high bit +#define bRST_FLAG0 0x10 // ReadOnly: recent reset flag low bit +#define MASK_RST_FLAG 0x30 // ReadOnly: bit mask of recent reset flag +#define RST_FLAG_SW 0x00 +#define RST_FLAG_POR 0x10 +#define RST_FLAG_WDOG 0x20 +#define RST_FLAG_PIN 0x30 +// bPC_RST_FLAG1 & bPC_RST_FLAG0: recent reset flag +// 00 - software reset, by bSW_RESET=1 @(bBOOT_LOAD=0 or bWDOG_EN=1) +// 01 - power on reset +// 10 - watch-dog timer overflow reset +// 11 - external input manual reset by RST pin +#define GF1 0x08 // general purpose flag bit 1 +#define GF0 0x04 // general purpose flag bit 0 +#define PD 0x02 // power-down enable bit, auto clear by wake-up hardware +SFR(CLOCK_CFG, 0xB9); // system clock config: lower 3 bits for system clock Fsys, Write@SafeMode +#define bOSC_EN_INT 0x80 // internal oscillator enable and original clock selection: 1=enable & select internal clock, 0=disable & select external clock +#define bOSC_EN_XT 0x40 // external oscillator enable, need quartz crystal or ceramic resonator between XI and XO pins +#define bWDOG_IF_TO 0x20 // ReadOnly: watch-dog timer overflow interrupt flag, cleared by reload watch-dog count or auto cleared when MCU enter interrupt routine +#define bROM_CLK_FAST 0x10 // flash-ROM clock frequency selection: 0=normal(for Fosc>=16MHz), 1=fast(for Fosc<16MHz) +#define bRST 0x08 // ReadOnly: pin RST input +#define bT2EX_ 0x08 // alternate pin for T2EX +#define bCAP2_ 0x08 // alternate pin for CAP2 +#define MASK_SYS_CK_SEL 0x07 // bit mask of system clock Fsys selection +/* + Fxt = 24MHz(8MHz~25MHz for non-USB application), from external oscillator @XI&XO + Fosc = bOSC_EN_INT ? 24MHz : Fxt + Fpll = Fosc * 4 => 96MHz (32MHz~100MHz for non-USB application) + Fusb4x = Fpll / 2 => 48MHz (Fixed) + MASK_SYS_CK_SEL[2] [1] [0] + Fsys = Fpll/3 = 32MHz: 1 1 1 + Fsys = Fpll/4 = 24MHz: 1 1 0 + Fsys = Fpll/6 = 16MHz: 1 0 1 + Fsys = Fpll/8 = 12MHz: 1 0 0 + Fsys = Fpll/16 = 6MHz: 0 1 1 + Fsys = Fpll/32 = 3MHz: 0 1 0 + Fsys = Fpll/128 = 750KHz: 0 0 1 + Fsys = Fpll/512 =187.5KHz: 0 0 0 +*/ +SFR(WAKE_CTRL, 0xA9); // wake-up control, Write@SafeMode +#define bWAK_BY_USB 0x80 // enable wake-up by USB event +#define bWAK_RXD1_LO 0x40 // enable wake-up by RXD1 low level +#define bWAK_P1_5_LO 0x20 // enable wake-up by pin P1.5 low level +#define bWAK_P1_4_LO 0x10 // enable wake-up by pin P1.4 low level +#define bWAK_P1_3_LO 0x08 // enable wake-up by pin P1.3 low level +#define bWAK_RST_HI 0x04 // enable wake-up by pin RST high level +#define bWAK_P3_2E_3L 0x02 // enable wake-up by pin P3.2 (INT0) edge or pin P3.3 (INT1) low level +#define bWAK_RXD0_LO 0x01 // enable wake-up by RXD0 low level +SFR(RESET_KEEP, 0xFE); // value keeper during reset +SFR(WDOG_COUNT, 0xFF); // watch-dog count, count by clock frequency Fsys/65536 + +/* Interrupt Registers */ +SFR(IE, 0xA8); // interrupt enable + SBIT(EA, 0xA8, 7); // enable global interrupts: 0=disable, 1=enable if E_DIS=0 + SBIT(E_DIS, 0xA8, 6); // disable global interrupts, intend to inhibit interrupt during some flash-ROM operation: 0=enable if EA=1, 1=disable + SBIT(ET2, 0xA8, 5); // enable timer2 interrupt + SBIT(ES, 0xA8, 4); // enable UART0 interrupt + SBIT(ET1, 0xA8, 3); // enable timer1 interrupt + SBIT(EX1, 0xA8, 2); // enable external interrupt INT1 + SBIT(ET0, 0xA8, 1); // enable timer0 interrupt + SBIT(EX0, 0xA8, 0); // enable external interrupt INT0 +SFR(IP, 0xB8); // interrupt priority and current priority + SBIT(PH_FLAG, 0xB8, 7); // ReadOnly: high level priority action flag + SBIT(PL_FLAG, 0xB8, 6); // ReadOnly: low level priority action flag +// PH_FLAG & PL_FLAG: current interrupt priority +// 00 - no interrupt now +// 01 - low level priority interrupt action now +// 10 - high level priority interrupt action now +// 11 - unknown error + SBIT(PT2, 0xB8, 5); // timer2 interrupt priority level + SBIT(PS, 0xB8, 4); // UART0 interrupt priority level + SBIT(PT1, 0xB8, 3); // timer1 interrupt priority level + SBIT(PX1, 0xB8, 2); // external interrupt INT1 priority level + SBIT(PT0, 0xB8, 1); // timer0 interrupt priority level + SBIT(PX0, 0xB8, 0); // external interrupt INT0 priority level +SFR(IE_EX, 0xE8); // extend interrupt enable + SBIT(IE_WDOG, 0xE8, 7); // enable watch-dog timer interrupt + SBIT(IE_GPIO, 0xE8, 6); // enable GPIO input interrupt + SBIT(IE_PWMX, 0xE8, 5); // enable PWM1/2 interrupt + SBIT(IE_UART1, 0xE8, 4); // enable UART1 interrupt + SBIT(IE_ADC, 0xE8, 3); // enable ADC interrupt + SBIT(IE_USB, 0xE8, 2); // enable USB interrupt + SBIT(IE_TKEY, 0xE8, 1); // enable touch-key timer interrupt + SBIT(IE_SPI0, 0xE8, 0); // enable SPI0 interrupt +SFR(IP_EX, 0xE9); // extend interrupt priority +#define bIP_LEVEL 0x80 // ReadOnly: current interrupt nested level: 0=no interrupt or two levels, 1=one level +#define bIP_GPIO 0x40 // GPIO input interrupt priority level +#define bIP_PWMX 0x20 // PWM1/2 interrupt priority level +#define bIP_UART1 0x10 // UART1 interrupt priority level +#define bIP_ADC 0x08 // ADC interrupt priority level +#define bIP_USB 0x04 // USB interrupt priority level +#define bIP_TKEY 0x02 // touch-key timer interrupt priority level +#define bIP_SPI0 0x01 // SPI0 interrupt priority level +SFR(GPIO_IE, 0xC7); // GPIO interrupt enable +#define bIE_IO_EDGE 0x80 // enable GPIO edge interrupt: 0=low/high level, 1=falling/rising edge +#define bIE_RXD1_LO 0x40 // enable interrupt by RXD1 low level / falling edge +#define bIE_P1_5_LO 0x20 // enable interrupt by pin P1.5 low level / falling edge +#define bIE_P1_4_LO 0x10 // enable interrupt by pin P1.4 low level / falling edge +#define bIE_P1_3_LO 0x08 // enable interrupt by pin P1.3 low level / falling edge +#define bIE_RST_HI 0x04 // enable interrupt by pin RST high level / rising edge +#define bIE_P3_1_LO 0x02 // enable interrupt by pin P3.1 low level / falling edge +#define bIE_RXD0_LO 0x01 // enable interrupt by RXD0 low level / falling edge + +/* FlashROM and Data-Flash Registers */ +SFR16(ROM_ADDR, 0x84); // address for flash-ROM, little-endian +SFR(ROM_ADDR_L, 0x84); // address low byte for flash-ROM +SFR(ROM_ADDR_H, 0x85); // address high byte for flash-ROM +SFR16(ROM_DATA, 0x8E); // data for flash-ROM writing, little-endian +SFR(ROM_DATA_L, 0x8E); // data low byte for flash-ROM writing, data byte for Data-Flash reading/writing +SFR(ROM_DATA_H, 0x8F); // data high byte for flash-ROM writing +SFR(ROM_CTRL, 0x86); // WriteOnly: flash-ROM control +#define ROM_CMD_WRITE 0x9A // WriteOnly: flash-ROM word or Data-Flash byte write operation command +#define ROM_CMD_READ 0x8E // WriteOnly: Data-Flash byte read operation command +//sfr ROM_STATUS = 0x86; // ReadOnly: flash-ROM status +#define ROM_STATUS ROM_CTRL +#define bROM_ADDR_OK 0x40 // ReadOnly: flash-ROM writing operation address valid flag, can be reviewed before or after operation: 0=invalid parameter, 1=address valid +#define bROM_CMD_ERR 0x02 // ReadOnly: flash-ROM operation command error flag: 0=command accepted, 1=unknown command + +/* Port Registers */ +SFR(P1, 0x90); // port 1 input & output + SBIT(SCK, 0x90, 7); // serial clock for SPI0 + SBIT(TXD1, 0x90, 7); // TXD output for UART1 + SBIT(TIN5, 0x90, 7); // TIN5 for Touch-Key + SBIT(MISO, 0x90, 6); // master serial data input or slave serial data output for SPI0 + SBIT(RXD1, 0x90, 6); // RXD input for UART1 + SBIT(TIN4, 0x90, 6); // TIN4 for Touch-Key + SBIT(MOSI, 0x90, 5); // master serial data output or slave serial data input for SPI0 + SBIT(PWM1, 0x90, 5); // PWM output for PWM1 + SBIT(TIN3, 0x90, 5); // TIN3 for Touch-Key + SBIT(UCC2, 0x90, 5); // CC2 for USB type-C + SBIT(AIN2, 0x90, 5); // AIN2 for ADC + SBIT(T2_, 0x90, 4); // alternate pin for T2 + SBIT(CAP1_, 0x90, 4); // alternate pin for CAP1 + SBIT(SCS, 0x90, 4); // slave chip-selection input for SPI0 + SBIT(TIN2, 0x90, 4); // TIN2 for Touch-Key + SBIT(UCC1, 0x90, 4); // CC1 for USB type-C + SBIT(AIN1, 0x90, 4); // AIN1 for ADC + SBIT(TXD_, 0x90, 3); // alternate pin for TXD of UART0 + SBIT(RXD_, 0x90, 2); // alternate pin for RXD of UART0 + SBIT(T2EX, 0x90, 1); // external trigger input for timer2 reload & capture + SBIT(CAP2, 0x90, 1); // capture2 input for timer2 + SBIT(TIN1, 0x90, 1); // TIN1 for Touch-Key + SBIT(VBUS2, 0x90, 1); // VBUS2 for USB type-C + SBIT(AIN0, 0x90, 1); // AIN0 for ADC + SBIT(T2, 0x90, 0); // external count input + SBIT(CAP1, 0x90, 0); // capture1 input for timer2 + SBIT(TIN0, 0x90, 0); // TIN0 for Touch-Key +SFR(P1_MOD_OC, 0x92); // port 1 output mode: 0=push-pull, 1=open-drain +SFR(P1_DIR_PU, 0x93); // port 1 direction for push-pull or pullup enable for open-drain +// Pn_MOD_OC & Pn_DIR_PU: pin input & output configuration for Pn (n=1/3) +// 0 0: float input only, without pullup resistance +// 0 1: push-pull output, strong driving high level and low level +// 1 0: open-drain output and input without pullup resistance +// 1 1: quasi-bidirectional (standard 8051 mode), open-drain output and input with pullup resistance, just driving high level strongly for 2 clocks if turning output level from low to high +#define bSCK 0x80 // serial clock for SPI0 +#define bTXD1 0x80 // TXD output for UART1 +#define bMISO 0x40 // master serial data input or slave serial data output for SPI0 +#define bRXD1 0x40 // RXD input for UART1 +#define bMOSI 0x20 // master serial data output or slave serial data input for SPI0 +#define bPWM1 0x20 // PWM output for PWM1 +#define bUCC2 0x20 // CC2 for USB type-C +#define bAIN2 0x20 // AIN2 for ADC +#define bT2_ 0x10 // alternate pin for T2 +#define bCAP1_ 0x10 // alternate pin for CAP1 +#define bSCS 0x10 // slave chip-selection input for SPI0 +#define bUCC1 0x10 // CC1 for USB type-C +#define bAIN1 0x10 // AIN1 for ADC +#define bTXD_ 0x08 // alternate pin for TXD of UART0 +#define bRXD_ 0x04 // alternate pin for RXD of UART0 +#define bT2EX 0x02 // external trigger input for timer2 reload & capture +#define bCAP2 bT2EX // capture2 input for timer2 +#define bVBUS2 0x02 // VBUS2 for USB type-C +#define bAIN0 0x02 // AIN0 for ADC +#define bT2 0x01 // external count input or clock output for timer2 +#define bCAP1 bT2 // capture1 input for timer2 +SFR(P2, 0xA0); // port 2 +SFR(P3, 0xB0); // port 3 input & output + SBIT(UDM, 0xB0, 7); // ReadOnly: pin UDM input + SBIT(UDP, 0xB0, 6); // ReadOnly: pin UDP input + SBIT(T1, 0xB0, 5); // external count input for timer1 + SBIT(PWM2, 0xB0, 4); // PWM output for PWM2 + SBIT(RXD1_, 0xB0, 4); // alternate pin for RXD1 + SBIT(T0, 0xB0, 4); // external count input for timer0 + SBIT(INT1, 0xB0, 3); // external interrupt 1 input + SBIT(TXD1_, 0xB0, 2); // alternate pin for TXD1 + SBIT(INT0, 0xB0, 2); // external interrupt 0 input + SBIT(VBUS1, 0xB0, 2); // VBUS1 for USB type-C + SBIT(AIN3, 0xB0, 2); // AIN3 for ADC + SBIT(PWM2_, 0xB0, 1); // alternate pin for PWM2 + SBIT(TXD, 0xB0, 1); // TXD output for UART0 + SBIT(PWM1_, 0xB0, 0); // alternate pin for PWM1 + SBIT(RXD, 0xB0, 0); // RXD input for UART0 +SFR(P3_MOD_OC, 0x96); // port 3 output mode: 0=push-pull, 1=open-drain +SFR(P3_DIR_PU, 0x97); // port 3 direction for push-pull or pullup enable for open-drain +#define bUDM 0x80 // ReadOnly: pin UDM input +#define bUDP 0x40 // ReadOnly: pin UDP input +#define bT1 0x20 // external count input for timer1 +#define bPWM2 0x10 // PWM output for PWM2 +#define bRXD1_ 0x10 // alternate pin for RXD1 +#define bT0 0x10 // external count input for timer0 +#define bINT1 0x08 // external interrupt 1 input +#define bTXD1_ 0x04 // alternate pin for TXD1 +#define bINT0 0x04 // external interrupt 0 input +#define bVBUS1 0x04 // VBUS1 for USB type-C +#define bAIN3 0x04 // AIN3 for ADC +#define bPWM2_ 0x02 // alternate pin for PWM2 +#define bTXD 0x02 // TXD output for UART0 +#define bPWM1_ 0x01 // alternate pin for PWM1 +#define bRXD 0x01 // RXD input for UART0 +SFR(PIN_FUNC, 0xC6); // pin function selection +#define bUSB_IO_EN 0x80 // USB UDP/UDM I/O pin enable: 0=P3.6/P3.7 as GPIO, 1=P3.6/P3.7 as USB +#define bIO_INT_ACT 0x40 // ReadOnly: GPIO interrupt request action status +#define bUART1_PIN_X 0x20 // UART1 alternate pin enable: 0=RXD1/TXD1 on P1.6/P1.7, 1=RXD1/TXD1 on P3.4/P3.2 +#define bUART0_PIN_X 0x10 // UART0 alternate pin enable: 0=RXD0/TXD0 on P3.0/P3.1, 1=RXD0/TXD0 on P1.2/P1.3 +#define bPWM2_PIN_X 0x08 // PWM2 alternate pin enable: 0=PWM2 on P3.4, 1=PWM2 on P3.1 +#define bPWM1_PIN_X 0x04 // PWM1 alternate pin enable: 0=PWM1 on P1.5, 1=PWM1 on P3.0 +#define bT2EX_PIN_X 0x02 // T2EX/CAP2 alternate pin enable: 0=T2EX/CAP2 on P1.1, 1=T2EX/CAP2 on RST +#define bT2_PIN_X 0x01 // T2/CAP1 alternate pin enable: 0=T2/CAP1 on P1.1, 1=T2/CAP1 on P1.4 +SFR(XBUS_AUX, 0xA2); // xBUS auxiliary setting +#define bUART0_TX 0x80 // ReadOnly: indicate UART0 transmittal status +#define bUART0_RX 0x40 // ReadOnly: indicate UART0 receiving status +#define bSAFE_MOD_ACT 0x20 // ReadOnly: safe mode action status +#define GF2 0x08 // general purpose flag bit 2 +#define bDPTR_AUTO_INC 0x04 // enable DPTR auto increase if finished MOVX_@DPTR instruction +#define DPS 0x01 // dual DPTR selection: 0=DPTR0 selected, 1=DPTR1 selected + +/* Timer0/1 Registers */ +SFR(TCON, 0x88); // timer 0/1 control and external interrupt control + SBIT(TF1, 0x88, 7); // timer1 overflow & interrupt flag, auto cleared when MCU enter interrupt routine + SBIT(TR1, 0x88, 6); // timer1 run enable + SBIT(TF0, 0x88, 5); // timer0 overflow & interrupt flag, auto cleared when MCU enter interrupt routine + SBIT(TR0, 0x88, 4); // timer0 run enable + SBIT(IE1, 0x88, 3); // INT1 interrupt flag, auto cleared when MCU enter interrupt routine + SBIT(IT1, 0x88, 2); // INT1 interrupt type: 0=low level action, 1=falling edge action + SBIT(IE0, 0x88, 1); // INT0 interrupt flag, auto cleared when MCU enter interrupt routine + SBIT(IT0, 0x88, 0); // INT0 interrupt type: 0=low level action, 1=falling edge action +SFR(TMOD, 0x89); // timer 0/1 mode +#define bT1_GATE 0x80 // gate control of timer1: 0=timer1 run enable while TR1=1, 1=timer1 run enable while P3.3 (INT1) pin is high and TR1=1 +#define bT1_CT 0x40 // counter or timer mode selection for timer1: 0=timer, use internal clock, 1=counter, use P3.5 (T1) pin falling edge as clock +#define bT1_M1 0x20 // timer1 mode high bit +#define bT1_M0 0x10 // timer1 mode low bit +#define MASK_T1_MOD 0x30 // bit mask of timer1 mode +// bT1_M1 & bT1_M0: timer1 mode +// 00: mode 0, 13-bit timer or counter by cascaded TH1 and lower 5 bits of TL1, the upper 3 bits of TL1 are ignored +// 01: mode 1, 16-bit timer or counter by cascaded TH1 and TL1 +// 10: mode 2, TL1 operates as 8-bit timer or counter, and TH1 provide initial value for TL1 auto-reload +// 11: mode 3, stop timer1 +#define bT0_GATE 0x08 // gate control of timer0: 0=timer0 run enable while TR0=1, 1=timer0 run enable while P3.2 (INT0) pin is high and TR0=1 +#define bT0_CT 0x04 // counter or timer mode selection for timer0: 0=timer, use internal clock, 1=counter, use P3.4 (T0) pin falling edge as clock +#define bT0_M1 0x02 // timer0 mode high bit +#define bT0_M0 0x01 // timer0 mode low bit +#define MASK_T0_MOD 0x03 // bit mask of timer0 mode +// bT0_M1 & bT0_M0: timer0 mode +// 00: mode 0, 13-bit timer or counter by cascaded TH0 and lower 5 bits of TL0, the upper 3 bits of TL0 are ignored +// 01: mode 1, 16-bit timer or counter by cascaded TH0 and TL0 +// 10: mode 2, TL0 operates as 8-bit timer or counter, and TH0 provide initial value for TL0 auto-reload +// 11: mode 3, TL0 is 8-bit timer or counter controlled by standard timer0 bits, TH0 is 8-bit timer using TF1 and controlled by TR1, timer1 run enable if it is not mode 3 +SFR(TL0, 0x8A); // low byte of timer 0 count +SFR(TL1, 0x8B); // low byte of timer 1 count +SFR(TH0, 0x8C); // high byte of timer 0 count +SFR(TH1, 0x8D); // high byte of timer 1 count + +/* UART0 Registers */ +SFR(SCON, 0x98); // UART0 control (serial port control) + SBIT(SM0, 0x98, 7); // UART0 mode bit0, selection data bit: 0=8 bits data, 1=9 bits data + SBIT(SM1, 0x98, 6); // UART0 mode bit1, selection baud rate: 0=fixed, 1=variable +// SM0 & SM1: UART0 mode +// 00 - mode 0, shift Register, baud rate fixed at: Fsys/12 +// 01 - mode 1, 8-bit UART, baud rate = variable by timer1 or timer2 overflow rate +// 10 - mode 2, 9-bit UART, baud rate fixed at: Fsys/128@SMOD=0, Fsys/32@SMOD=1 +// 11 - mode 3, 9-bit UART, baud rate = variable by timer1 or timer2 overflow rate + SBIT(SM2, 0x98, 5); // enable multi-device communication in mode 2/3 +#define MASK_UART0_MOD 0xE0 // bit mask of UART0 mode + SBIT(REN, 0x98, 4); // enable UART0 receiving + SBIT(TB8, 0x98, 3); // the 9th transmitted data bit in mode 2/3 + SBIT(RB8, 0x98, 2); // 9th data bit received in mode 2/3, or stop bit received for mode 1 + SBIT(TI, 0x98, 1); // transmit interrupt flag, set by hardware after completion of a serial transmittal, need software clear + SBIT(RI, 0x98, 0); // receive interrupt flag, set by hardware after completion of a serial receiving, need software clear +SFR(SBUF, 0x99); // UART0 data buffer: reading for receiving, writing for transmittal + +/* Timer2/Capture2 Registers */ +SFR(T2CON, 0xC8); // timer 2 control + SBIT(TF2, 0xC8, 7); // timer2 overflow & interrupt flag, need software clear, the flag will not be set when either RCLK=1 or TCLK=1 + SBIT(CAP1F, 0xC8, 7); // timer2 capture 1 interrupt flag, set by T2 edge trigger if bT2_CAP1_EN=1, need software clear + SBIT(EXF2, 0xC8, 6); // timer2 external flag, set by T2EX edge trigger if EXEN2=1, need software clear + SBIT(RCLK, 0xC8, 5); // selection UART0 receiving clock: 0=timer1 overflow pulse, 1=timer2 overflow pulse + SBIT(TCLK, 0xC8, 4); // selection UART0 transmittal clock: 0=timer1 overflow pulse, 1=timer2 overflow pulse + SBIT(EXEN2, 0xC8, 3); // enable T2EX trigger function: 0=ignore T2EX, 1=trigger reload or capture by T2EX edge + SBIT(TR2, 0xC8, 2); // timer2 run enable + SBIT(C_T2, 0xC8, 1); // timer2 clock source selection: 0=timer base internal clock, 1=external edge counter base T2 falling edge + SBIT(CP_RL2, 0xC8, 0); // timer2 function selection (force 0 if RCLK=1 or TCLK=1): 0=timer and auto reload if count overflow or T2EX edge, 1=capture by T2EX edge +SFR(T2MOD, 0xC9); // timer 2 mode and timer 0/1/2 clock mode +#define bTMR_CLK 0x80 // fastest internal clock mode for timer 0/1/2 under faster clock mode: 0=use divided clock, 1=use original Fsys as clock without dividing +#define bT2_CLK 0x40 // timer2 internal clock frequency selection: 0=standard clock, Fsys/12 for timer mode, Fsys/4 for UART0 clock mode, + // 1=faster clock, Fsys/4 @bTMR_CLK=0 or Fsys @bTMR_CLK=1 for timer mode, Fsys/2 @bTMR_CLK=0 or Fsys @bTMR_CLK=1 for UART0 clock mode +#define bT1_CLK 0x20 // timer1 internal clock frequency selection: 0=standard clock, Fsys/12, 1=faster clock, Fsys/4 if bTMR_CLK=0 or Fsys if bTMR_CLK=1 +#define bT0_CLK 0x10 // timer0 internal clock frequency selection: 0=standard clock, Fsys/12, 1=faster clock, Fsys/4 if bTMR_CLK=0 or Fsys if bTMR_CLK=1 +#define bT2_CAP_M1 0x08 // timer2 capture mode high bit +#define bT2_CAP_M0 0x04 // timer2 capture mode low bit +// bT2_CAP_M1 & bT2_CAP_M0: timer2 capture point selection +// x0: from falling edge to falling edge +// 01: from any edge to any edge (level changing) +// 11: from rising edge to rising edge +#define T2OE 0x02 // enable timer2 generated clock output: 0=disable output, 1=enable clock output at T2 pin, frequency = TF2/2 +#define bT2_CAP1_EN 0x01 // enable T2 trigger function for capture 1 of timer2 if RCLK=0 & TCLK=0 & CP_RL2=1 & C_T2=0 & T2OE=0 +SFR16(RCAP2, 0xCA); // reload & capture value, little-endian +SFR(RCAP2L, 0xCA); // low byte of reload & capture value +SFR(RCAP2H, 0xCB); // high byte of reload & capture value +SFR16(T2COUNT, 0xCC); // counter, little-endian +SFR(TL2, 0xCC); // low byte of timer 2 count +SFR(TH2, 0xCD); // high byte of timer 2 count +SFR16(T2CAP1, 0xCE); // ReadOnly: capture 1 value for timer2 +SFR(T2CAP1L, 0xCE); // ReadOnly: capture 1 value low byte for timer2 +SFR(T2CAP1H, 0xCF); // ReadOnly: capture 1 value high byte for timer2 + +/* PWM1/2 Registers */ +SFR(PWM_DATA2, 0x9B); // PWM data for PWM2 +SFR(PWM_DATA1, 0x9C); // PWM data for PWM1 +SFR(PWM_CTRL, 0x9D); // PWM 1/2 control +#define bPWM_IE_END 0x80 // enable interrupt for PWM mode cycle end +#define bPWM2_POLAR 0x40 // PWM2 output polarity: 0=default low and high action, 1=default high and low action +#define bPWM1_POLAR 0x20 // PWM1 output polarity: 0=default low and high action, 1=default high and low action +#define bPWM_IF_END 0x10 // interrupt flag for cycle end, write 1 to clear or write PWM_CYCLE or load new data to clear +#define bPWM2_OUT_EN 0x08 // PWM2 output enable +#define bPWM1_OUT_EN 0x04 // PWM1 output enable +#define bPWM_CLR_ALL 0x02 // force clear FIFO and count of PWM1/2 +SFR(PWM_CK_SE, 0x9E); // clock divisor setting + +/* SPI0/Master0/Slave Registers */ +SFR(SPI0_STAT, 0xF8); // SPI 0 status + SBIT(S0_FST_ACT, 0xF8, 7); // ReadOnly: indicate first byte received status for SPI0 + SBIT(S0_IF_OV, 0xF8, 6); // interrupt flag for slave mode FIFO overflow, direct bit address clear or write 1 to clear + SBIT(S0_IF_FIRST, 0xF8, 5); // interrupt flag for first byte received, direct bit address clear or write 1 to clear + SBIT(S0_IF_BYTE, 0xF8, 4); // interrupt flag for a byte data exchanged, direct bit address clear or write 1 to clear or accessing FIFO to clear if bS0_AUTO_IF=1 + SBIT(S0_FREE, 0xF8, 3); // ReadOnly: SPI0 free status + SBIT(S0_T_FIFO, 0xF8, 2); // ReadOnly: tx FIFO count for SPI0 + SBIT(S0_R_FIFO, 0xF8, 0); // ReadOnly: rx FIFO count for SPI0 +SFR(SPI0_DATA, 0xF9); // FIFO data port: reading for receiving, writing for transmittal +SFR(SPI0_CTRL, 0xFA); // SPI 0 control +#define bS0_MISO_OE 0x80 // SPI0 MISO output enable +#define bS0_MOSI_OE 0x40 // SPI0 MOSI output enable +#define bS0_SCK_OE 0x20 // SPI0 SCK output enable +#define bS0_DATA_DIR 0x10 // SPI0 data direction: 0=out(master_write), 1=in(master_read) +#define bS0_MST_CLK 0x08 // SPI0 master clock mode: 0=mode 0 with default low, 1=mode 3 with default high +#define bS0_2_WIRE 0x04 // enable SPI0 two wire mode: 0=3 wire (SCK+MOSI+MISO), 1=2 wire (SCK+MISO) +#define bS0_CLR_ALL 0x02 // force clear FIFO and count of SPI0 +#define bS0_AUTO_IF 0x01 // enable FIFO accessing to auto clear S0_IF_BYTE interrupt flag +SFR(SPI0_CK_SE, 0xFB); // clock divisor setting +//sfr SPI0_S_PRE = 0xFB; // preset value for SPI slave +#define SPI0_S_PRE SPI0_CK_SE +SFR(SPI0_SETUP, 0xFC); // SPI 0 setup +#define bS0_MODE_SLV 0x80 // SPI0 slave mode: 0=master, 1=slave +#define bS0_IE_FIFO_OV 0x40 // enable interrupt for slave mode FIFO overflow +#define bS0_IE_FIRST 0x20 // enable interrupt for first byte received for SPI0 slave mode +#define bS0_IE_BYTE 0x10 // enable interrupt for a byte received +#define bS0_BIT_ORDER 0x08 // SPI0 bit data order: 0=MSB first, 1=LSB first +#define bS0_SLV_SELT 0x02 // ReadOnly: SPI0 slave mode chip selected status: 0=unselected, 1=selected +#define bS0_SLV_PRELOAD 0x01 // ReadOnly: SPI0 slave mode data pre-loading status just after chip-selection + +/* UART1 Registers */ +SFR(SCON1, 0xC0); // UART1 control (serial port control) + SBIT(U1SM0, 0xC0, 7); // UART1 mode, selection data bit: 0=8 bits data, 1=9 bits data + SBIT(U1SMOD, 0xC0, 5); // UART1 2X baud rate selection: 0=slow(Fsys/32/(256-SBAUD1)), 1=fast(Fsys/16/(256-SBAUD1)) + SBIT(U1REN, 0xC0, 4); // enable UART1 receiving + SBIT(U1TB8, 0xC0, 3); // the 9th transmitted data bit in 9 bits data mode + SBIT(U1RB8, 0xC0, 2); // 9th data bit received in 9 bits data mode, or stop bit received for 8 bits data mode + SBIT(U1TI, 0xC0, 1); // transmit interrupt flag, set by hardware after completion of a serial transmittal, need software clear + SBIT(U1RI, 0xC0, 0); // receive interrupt flag, set by hardware after completion of a serial receiving, need software clear +SFR(SBUF1, 0xC1); // UART1 data buffer: reading for receiving, writing for transmittal +SFR(SBAUD1, 0xC2); // UART1 baud rate setting + +/* ADC and comparator Registers */ +SFR(ADC_CTRL, 0x80); // ADC control + SBIT(CMPO, 0x80, 7); // ReadOnly: comparator result input + SBIT(CMP_IF, 0x80, 6); // flag for comparator result changed, direct bit address clear + SBIT(ADC_IF, 0x80, 5); // interrupt flag for ADC finished, direct bit address clear + SBIT(ADC_START, 0x80, 4); // set 1 to start ADC, auto cleared when ADC finished + SBIT(CMP_CHAN, 0x80, 3); // comparator IN- input channel selection: 0=AIN1, 1=AIN3 + SBIT(ADC_CHAN1, 0x80, 1); // ADC/comparator IN+ channel selection high bit + SBIT(ADC_CHAN0, 0x80, 0); // ADC/comparator IN+ channel selection low bit +// ADC_CHAN1 & ADC_CHAN0: ADC/comparator IN+ channel selection +// 00: AIN0(P1.1) +// 01: AIN1(P1.4) +// 10: AIN2(P1.5) +// 11: AIN3(P3.2) +SFR(ADC_CFG, 0x9A); // ADC config +#define bADC_EN 0x08 // control ADC power: 0=shut down ADC, 1=enable power for ADC +#define bCMP_EN 0x04 // control comparator power: 0=shut down comparator, 1=enable power for comparator +#define bADC_CLK 0x01 // ADC clock frequency selection: 0=slow clock, 384 Fosc cycles for each ADC, 1=fast clock, 96 Fosc cycles for each ADC +SFR(ADC_DATA, 0x9F); // ReadOnly: ADC data + +/* Touch-key timer Registers */ +SFR(TKEY_CTRL, 0xC3); // touch-key control +#define bTKC_IF 0x80 // ReadOnly: interrupt flag for touch-key timer, cleared by writing touch-key control or auto cleared when start touch-key checking +#define bTKC_2MS 0x10 // touch-key timer cycle selection: 0=1mS, 1=2mS +#define bTKC_CHAN2 0x04 // touch-key channel selection high bit +#define bTKC_CHAN1 0x02 // touch-key channel selection middle bit +#define bTKC_CHAN0 0x01 // touch-key channel selection low bit +// bTKC_CHAN2 & bTKC_CHAN1 & bTKC_CHAN0: touch-key channel selection +// 000: disable touch-key +// 001: TIN0(P1.0) +// 010: TIN1(P1.1) +// 011: TIN2(P1.4) +// 100: TIN3(P1.5) +// 101: TIN4(P1.6) +// 110: TIN5(P1.7) +// 111: enable touch-key but disable all channel +SFR16(TKEY_DAT, 0xC4); // ReadOnly: touch-key data, little-endian +SFR(TKEY_DATL, 0xC4); // ReadOnly: low byte of touch-key data +SFR(TKEY_DATH, 0xC5); // ReadOnly: high byte of touch-key data +#define bTKD_CHG 0x80 // ReadOnly: indicate control changed, current data maybe invalid + +/* USB/Host/Device Registers */ +SFR(USB_C_CTRL, 0x91); // USB type-C control +#define bVBUS2_PD_EN 0x80 // USB VBUS2 10K pulldown resistance: 0=disable, 1=enable pullup +#define bUCC2_PD_EN 0x40 // USB CC2 5.1K pulldown resistance: 0=disable, 1=enable pulldown +#define bUCC2_PU1_EN 0x20 // USB CC2 pullup resistance control high bit +#define bUCC2_PU0_EN 0x10 // USB CC2 pullup resistance control low bit +#define bVBUS1_PD_EN 0x08 // USB VBUS1 10K pulldown resistance: 0=disable, 1=enable pullup +#define bUCC1_PD_EN 0x04 // USB CC1 5.1K pulldown resistance: 0=disable, 1=enable pulldown +#define bUCC1_PU1_EN 0x02 // USB CC1 pullup resistance control high bit +#define bUCC1_PU0_EN 0x01 // USB CC1 pullup resistance control low bit +// bUCC?_PU1_EN & bUCC?_PU0_EN: USB CC pullup resistance selection +// 00: disable pullup resistance +// 01: enable 56K pullup resistance for default USB power +// 10: enable 22K pullup resistance for 1.5A USB power +// 11: enable 10K pullup resistance for 3A USB power +SFR(UDEV_CTRL, 0xD1); // USB device physical port control +#define bUD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define bUD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define bUD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define bUD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define bUD_GP_BIT 0x02 // general purpose bit +#define bUD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable +//sfr UHOST_CTRL = 0xD1; // USB host physical port control +#define UHOST_CTRL UDEV_CTRL +#define bUH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define bUH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define bUH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define bUH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define bUH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define bUH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached +SFR(UEP1_CTRL, 0xD2); // endpoint 1 control +#define bUEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define bUEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define bUEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define bUEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT) +#define bUEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT) +#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define UEP_R_RES_ACK 0x00 +#define UEP_R_RES_TOUT 0x04 +#define UEP_R_RES_NAK 0x08 +#define UEP_R_RES_STALL 0x0C +// bUEP_R_RES1 & bUEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +#define bUEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) +#define bUEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) +#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define UEP_T_RES_ACK 0x00 +#define UEP_T_RES_TOUT 0x01 +#define UEP_T_RES_NAK 0x02 +#define UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +SFR(UEP1_T_LEN, 0xD3); // endpoint 1 transmittal length +SFR(UEP2_CTRL, 0xD4); // endpoint 2 control +SFR(UEP2_T_LEN, 0xD5); // endpoint 2 transmittal length +SFR(UEP3_CTRL, 0xD6); // endpoint 3 control +SFR(UEP3_T_LEN, 0xD7); // endpoint 3 transmittal length +SFR(USB_INT_FG, 0xD8); // USB interrupt flag + SBIT(U_IS_NAK, 0xD8, 7); // ReadOnly: indicate current USB transfer is NAK received + SBIT(U_TOG_OK, 0xD8, 6); // ReadOnly: indicate current USB transfer toggle is OK + SBIT(U_SIE_FREE, 0xD8, 5); // ReadOnly: indicate USB SIE free status + SBIT(UIF_FIFO_OV, 0xD8, 4); // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear + SBIT(UIF_HST_SOF, 0xD8, 3); // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear + SBIT(UIF_SUSPEND, 0xD8, 2); // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear + SBIT(UIF_TRANSFER, 0xD8, 1); // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear + SBIT(UIF_DETECT, 0xD8, 0); // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear + SBIT(UIF_BUS_RST, 0xD8, 0); // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear +SFR(USB_INT_ST, 0xD9); // ReadOnly: USB interrupt status +#define bUIS_IS_NAK 0x80 // ReadOnly: indicate current USB transfer is NAK received for USB device mode +#define bUIS_TOG_OK 0x40 // ReadOnly: indicate current USB transfer toggle is OK +#define bUIS_TOKEN1 0x20 // ReadOnly: current token PID code bit 1 received for USB device mode +#define bUIS_TOKEN0 0x10 // ReadOnly: current token PID code bit 0 received for USB device mode +#define MASK_UIS_TOKEN 0x30 // ReadOnly: bit mask of current token PID code received for USB device mode +#define UIS_TOKEN_OUT 0x00 +#define UIS_TOKEN_SOF 0x10 +#define UIS_TOKEN_IN 0x20 +#define UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define MASK_UIS_ENDP 0x0F // ReadOnly: bit mask of current transfer endpoint number for USB device mode +#define MASK_UIS_H_RES 0x0F // ReadOnly: bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received +SFR(USB_MIS_ST, 0xDA); // ReadOnly: USB miscellaneous status +#define bUMS_SOF_PRES 0x80 // ReadOnly: indicate host SOF timer presage status +#define bUMS_SOF_ACT 0x40 // ReadOnly: indicate host SOF timer action status for USB host +#define bUMS_SIE_FREE 0x20 // ReadOnly: indicate USB SIE free status +#define bUMS_R_FIFO_RDY 0x10 // ReadOnly: indicate USB receiving FIFO ready status (not empty) +#define bUMS_BUS_RESET 0x08 // ReadOnly: indicate USB bus reset status +#define bUMS_SUSPEND 0x04 // ReadOnly: indicate USB suspend status +#define bUMS_DM_LEVEL 0x02 // ReadOnly: indicate UDM level saved at device attached to USB host +#define bUMS_DEV_ATTACH 0x01 // ReadOnly: indicate device attached status on USB host +SFR(USB_RX_LEN, 0xDB); // ReadOnly: USB receiving length +SFR(UEP0_CTRL, 0xDC); // endpoint 0 control +SFR(UEP0_T_LEN, 0xDD); // endpoint 0 transmittal length +SFR(UEP4_CTRL, 0xDE); // endpoint 4 control +SFR(UEP4_T_LEN, 0xDF); // endpoint 4 transmittal length +SFR(USB_INT_EN, 0xE1); // USB interrupt enable +#define bUIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define bUIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define bUIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define bUIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define bUIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define bUIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define bUIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define bUIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode +SFR(USB_CTRL, 0xE2); // USB base control +#define bUC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define bUC_LOW_SPEED 0x40 // enable USB low speed: 0=full speed, 1=low speed +#define bUC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define bUC_SYS_CTRL1 0x20 // USB system control high bit +#define bUC_SYS_CTRL0 0x10 // USB system control low bit +#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control +// bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control +// 0 00: disable USB device and disable internal pullup resistance +// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance +// 0 1x: enable USB device and enable internal pullup resistance +// 1 00: enable USB host and normal status +// 1 01: enable USB host and force UDP/UDM output SE0 state +// 1 10: enable USB host and force UDP/UDM output J state +// 1 11: enable USB host and force UDP/UDM output resume or K state +#define bUC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define bUC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define bUC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define bUC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB +SFR(USB_DEV_AD, 0xE3); // USB device address, lower 7 bits for USB device address +#define bUDA_GP_BIT 0x80 // general purpose bit +#define MASK_USB_ADDR 0x7F // bit mask for USB device address +SFR16(UEP2_DMA, 0xE4); // endpoint 2 buffer start address, little-endian +SFR(UEP2_DMA_L, 0xE4); // endpoint 2 buffer start address low byte +SFR(UEP2_DMA_H, 0xE5); // endpoint 2 buffer start address high byte +SFR16(UEP3_DMA, 0xE6); // endpoint 3 buffer start address, little-endian +SFR(UEP3_DMA_L, 0xE6); // endpoint 3 buffer start address low byte +SFR(UEP3_DMA_H, 0xE7); // endpoint 3 buffer start address high byte +SFR(UEP4_1_MOD, 0xEA); // endpoint 4/1 mode +#define bUEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define bUEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define bUEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define bUEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define bUEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes +SFR(UEP2_3_MOD, 0xEB); // endpoint 2/3 mode +#define bUEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define bUEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define bUEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define bUEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define bUEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define bUEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 +SFR16(UEP0_DMA, 0xEC); // endpoint 0 buffer start address, little-endian +SFR(UEP0_DMA_L, 0xEC); // endpoint 0 buffer start address low byte +SFR(UEP0_DMA_H, 0xED); // endpoint 0 buffer start address high byte +SFR16(UEP1_DMA, 0xEE); // endpoint 1 buffer start address, little-endian +SFR(UEP1_DMA_L, 0xEE); // endpoint 1 buffer start address low byte +SFR(UEP1_DMA_H, 0xEF); // endpoint 1 buffer start address high byte +//sfr UH_SETUP = 0xD2; // host aux setup +#define UH_SETUP UEP1_CTRL +#define bUH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub +#define bUH_SOF_EN 0x40 // USB host automatic SOF enable +//sfr UH_RX_CTRL = 0xD4; // host receiver endpoint control +#define UH_RX_CTRL UEP2_CTRL +#define bUH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define bUH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define bUH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions +//sfr UH_EP_PID = 0xD5; // host endpoint and token PID, lower 4 bits for endpoint number, upper 4 bits for token PID +#define UH_EP_PID UEP2_T_LEN +#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer +#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer +//sfr UH_TX_CTRL = 0xD6; // host transmittal endpoint control +#define UH_TX_CTRL UEP3_CTRL +#define bUH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define bUH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define bUH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions +//sfr UH_TX_LEN = 0xD7; // host transmittal endpoint transmittal length +#define UH_TX_LEN UEP3_T_LEN +//sfr UH_EP_MOD = 0xEB; // host endpoint mode +#define UH_EP_MOD UEP2_3_MOD +#define bUH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define bUH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define bUH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define bUH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes +//sfr16 UH_RX_DMA = 0xE4; // host rx endpoint buffer start address, little-endian +#define UH_RX_DMA UEP2_DMA +//sfr UH_RX_DMA_L = 0xE4; // host rx endpoint buffer start address low byte +#define UH_RX_DMA_L UEP2_DMA_L +//sfr UH_RX_DMA_H = 0xE5; // host rx endpoint buffer start address high byte +#define UH_RX_DMA_H UEP2_DMA_H +//sfr16 UH_TX_DMA = 0xE6; // host tx endpoint buffer start address, little-endian +#define UH_TX_DMA UEP3_DMA +//sfr UH_TX_DMA_L = 0xE6; // host tx endpoint buffer start address low byte +#define UH_TX_DMA_L UEP3_DMA_L +//sfr UH_TX_DMA_H = 0xE7; // host tx endpoint buffer start address high byte +#define UH_TX_DMA_H UEP3_DMA_H + +/*----- XDATA: xRAM ------------------------------------------*/ + +#define XDATA_RAM_SIZE 0x0400 // size of expanded xRAM, xdata SRAM embedded chip + +/*----- Reference Information --------------------------------------------*/ +#define ID_CH554 0x54 // chip ID + +/* Interrupt routine address and interrupt number */ +#define INT_ADDR_INT0 0x0003 // interrupt vector address for INT0 +#define INT_ADDR_TMR0 0x000B // interrupt vector address for timer0 +#define INT_ADDR_INT1 0x0013 // interrupt vector address for INT1 +#define INT_ADDR_TMR1 0x001B // interrupt vector address for timer1 +#define INT_ADDR_UART0 0x0023 // interrupt vector address for UART0 +#define INT_ADDR_TMR2 0x002B // interrupt vector address for timer2 +#define INT_ADDR_SPI0 0x0033 // interrupt vector address for SPI0 +#define INT_ADDR_TKEY 0x003B // interrupt vector address for touch-key timer +#define INT_ADDR_USB 0x0043 // interrupt vector address for USB +#define INT_ADDR_ADC 0x004B // interrupt vector address for ADC +#define INT_ADDR_UART1 0x0053 // interrupt vector address for UART1 +#define INT_ADDR_PWMX 0x005B // interrupt vector address for PWM1/2 +#define INT_ADDR_GPIO 0x0063 // interrupt vector address for GPIO +#define INT_ADDR_WDOG 0x006B // interrupt vector address for watch-dog timer +#define INT_NO_INT0 0 // interrupt number for INT0 +#define INT_NO_TMR0 1 // interrupt number for timer0 +#define INT_NO_INT1 2 // interrupt number for INT1 +#define INT_NO_TMR1 3 // interrupt number for timer1 +#define INT_NO_UART0 4 // interrupt number for UART0 +#define INT_NO_TMR2 5 // interrupt number for timer2 +#define INT_NO_SPI0 6 // interrupt number for SPI0 +#define INT_NO_TKEY 7 // interrupt number for touch-key timer +#define INT_NO_USB 8 // interrupt number for USB +#define INT_NO_ADC 9 // interrupt number for ADC +#define INT_NO_UART1 10 // interrupt number for UART1 +#define INT_NO_PWMX 11 // interrupt number for PWM1/2 +#define INT_NO_GPIO 12 // interrupt number for GPIO +#define INT_NO_WDOG 13 // interrupt number for watch-dog timer + +/* Special Program Space */ +#define DATA_FLASH_ADDR 0xC000 // start address of Data-Flash +#define BOOT_LOAD_ADDR 0x3800 // start address of boot loader program +#define ROM_CFG_ADDR 0x3FF8 // chip configuration information address +#define ROM_CHIP_ID_HX 0x3FFA // chip ID number highest byte (only low byte valid) +#define ROM_CHIP_ID_LO 0x3FFC // chip ID number low word +#define ROM_CHIP_ID_HI 0x3FFE // chip ID number high word + +/* +New Instruction: MOVX @DPTR1,A +Instruction Code: 0xA5 +Instruction Cycle: 1 +Instruction Operation: + step-1. write ACC @DPTR1 into xdata SRAM embedded chip + step-2. increase DPTR1 +ASM example: + INC XBUS_AUX + MOV DPTR,#TARGET_ADDR ;DPTR1 + DEC XBUS_AUX + MOV DPTR,#SOURCE_ADDR ;DPTR0 + MOV R7,#xxH + LOOP: MOVX A,@DPTR ;DPTR0 + INC DPTR ;DPTR0, if need + .DB 0xA5 ;MOVX @DPTR1,A & INC DPTR1 + DJNZ R7,LOOP +*/ + +#endif // __CH554_H__ diff --git a/software/src/config.h b/software/src/config.h new file mode 100755 index 0000000..9edfa7a --- /dev/null +++ b/software/src/config.h @@ -0,0 +1,31 @@ +// =================================================================================== +// User Configurations for CH552 DAPLink +// =================================================================================== + +#pragma once + +// Pin definitions +#define PIN_LED P11 // pin connected to LED, active low +#define PIN_SWD P15 // pin connected to SWDIO/TMS via 100R resistor +#define PIN_SWK P16 // pin connected to SWCLK/TCK via 100R resistor +#define PIN_RST P17 // pin connected to nRESET +#define PIN_TDO P14 // pin connected to TDO via 100R resistor +#define PIN_TDI P32 // pin connected to TDI via 100R resistor +#define PIN_TRST P34 // pin connected to nTRST +#define PIN_RXD P30 // pin connected to RXD via 470R resistor +#define PIN_TXD P31 // pin connected to TXT via 470R resistor + +// USB device descriptor +#define USB_VENDOR_ID 0x1A86 // VID +#define USB_PRODUCT_ID 0x8011 // PID +#define USB_DEVICE_VERSION 0x0100 // v1.0 (BCD-format) + +// USB configuration descriptor +#define USB_MAX_POWER_mA 500 // max power in mA + +// USB descriptor strings +#define MANUFACTURER_STR 'w','a','g','i','m','i','n','a','t','o','r' +#define PRODUCT_STR 'D','A','P','L','i','n','k',' ', 'C','M','S','I','S','-','D','A','P' +#define SERIAL_STR 'C','H','5','5','2' +#define INTERFACE_STR_1 'C','D','C',' ','V','C','P' +#define INTERFACE_STR_2 'H','I','D',' ','D','a','t','a' diff --git a/software/src/dap.c b/software/src/dap.c new file mode 100644 index 0000000..a47dcc8 --- /dev/null +++ b/software/src/dap.c @@ -0,0 +1,1504 @@ +// =================================================================================== +// CMSIS-DAP Commands for CH552 DAPLink +// =================================================================================== +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. December 2017 + * $Revision: V2.0.0 + * + * Project: CMSIS-DAP Source + * Title: DAP.c CMSIS-DAP Commands + * + *---------------------------------------------------------------------------*/ + +#include +#include "dap.h" + +#pragma disable_warning 110 + +// =================================================================================== +// Get DAP Information +// id: info identifier +// info: pointer to info data +// return: number of bytes in info data +// =================================================================================== +static uint8_t DAP_Info(uint8_t id, __xdata uint8_t *info) { + uint8_t length = 0U; + switch(id) { + case DAP_ID_FW_VER: + length = (uint8_t)sizeof(DAP_FW_VER); + strcpy(info, DAP_FW_VER ); + break; + case DAP_ID_CAPABILITIES: + info[0] = DAP_PORT_SWD | DAP_PORT_JTAG; + length = 1U; + break; + case DAP_ID_PACKET_SIZE: + info[0] = DAP_PACKET_SIZE; + info[1] = 0; + length = 2U; + break; + case DAP_ID_PACKET_COUNT: + info[0] = DAP_PACKET_COUNT; + length = 1U; + break; + default: + break; + } + return length; +} + +// =================================================================================== +// Process Host Status AKA DAP_LED command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +// =================================================================================== +static uint8_t DAP_HostStatus(const __xdata uint8_t *req, __xdata uint8_t *res) { + *res = DAP_OK; + switch(*req) { + case DAP_DEBUGGER_CONNECTED: + LED_CON_SET(*(req + 1) & 1U); + break; + case DAP_TARGET_RUNNING: + LED_RUN_SET(*(req + 1) & 1U); + break; + default: + *res = DAP_ERROR; + } + return 1; +} + +// =================================================================================== +// Process Connect command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +// =================================================================================== +__idata uint8_t debug_port; +static uint8_t DAP_Connect(const __xdata uint8_t *req, __xdata uint8_t *res) { + uint8_t port; + if(*req == DAP_PORT_AUTODETECT) port = DAP_DEFAULT_PORT; + else port = *req; + + switch(port) { + case DAP_PORT_SWD: + debug_port = DAP_PORT_SWD; + PORT_SWD_CONNECT(); + break; + case DAP_PORT_JTAG: + debug_port = DAP_PORT_JTAG; + PORT_JTAG_CONNECT(); + break; + default: + port = DAP_PORT_DISABLED; + break; + } + + *res = port; + return 1; +} + +// =================================================================================== +// Process Disconnect command and prepare response +// response: pointer to response data +// return: number of bytes in response +// =================================================================================== +static uint8_t DAP_Disconnect(__xdata uint8_t *res) { + *res = DAP_OK; + debug_port = DAP_PORT_DISABLED; + PORT_OFF(); + return 1; +} + +// =================================================================================== +// Generate SWJ Sequence +// count: sequence bits count +// data: pointer to sequence bits data +// return: none +// =================================================================================== +void SWJ_Sequence(uint8_t count, const __xdata uint8_t *data) { + uint8_t val; + uint8_t n; + + val = 0U; + n = 0U; + while(count--) { + if(n == 0U) { + val = *data++; + n = 8U; + } + + SWD_WRITE_BIT(val); + val >>= 1; + n--; + } +} + +// =================================================================================== +// Generate SWD Sequence +// info: sequence information +// swdo: pointer to SWDIO generated data +// swdi: pointer to SWDIO captured data +// return: none +// =================================================================================== +void SWD_Sequence(uint8_t info, const __xdata uint8_t *swdo, __xdata uint8_t *swdi) { + uint8_t val; + uint8_t bit; + uint8_t n, k; + + n = info & SWD_SEQUENCE_CLK; + if(n == 0U) n = 64U; + + if(info & SWD_SEQUENCE_DIN) { + while(n) { + val = 0U; + for (k = 8U; k && n; k--, n--) { + SWD_READ_BIT(bit); + val >>= 1; + val |= bit << 7; + } + val >>= k; + *swdi++ = (uint8_t)val; + } + } + else { + while(n) { + val = *swdo++; + for(k = 8U; k && n; k--, n--) { + SWD_WRITE_BIT(val); + val >>= 1; + } + } + } +} + +// =================================================================================== +// SWD Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +// =================================================================================== +__idata uint8_t idle_cycles; +uint8_t SWD_Transfer(uint8_t req, __xdata uint8_t *data) { + uint8_t ack; + uint8_t bit = req; + uint8_t val; + uint8_t parity; + uint8_t m, n; + + // Packet req + parity = 0U; + SWD_WRITE_BIT(1U); // start bit + SWD_WRITE_BIT(bit); // APnDP bit + parity += bit; + bit >>= 1; + SWD_WRITE_BIT(bit); // RnW bit + parity += bit; + bit >>= 1; + SWD_WRITE_BIT(bit); // A2 bit + parity += bit; + bit >>= 1; + SWD_WRITE_BIT(bit); // A3 bit + parity += bit; + SWD_WRITE_BIT(parity); // parity bit + SWD_WRITE_BIT(0U); // stop bit + SWD_WRITE_BIT(1U); // park bit + + // Turnaround is always 1 cycle + SWD_OUT_DISABLE(); + SWD_CLOCK_CYCLE(); + + // Acknowledge res + SWD_READ_BIT(bit); + ack = bit << 0; + SWD_READ_BIT(bit); + ack |= bit << 1; + SWD_READ_BIT(bit); + ack |= bit << 2; + + if(ack == DAP_TRANSFER_OK) { + // OK res + // Data transfer + if(req & DAP_TRANSFER_RnW) { // read data + val = 0U; + parity = 0U; + for(m = 0; m < 4; m++) { + for(n = 8U; n; n--) { + SWD_READ_BIT(bit); // read RDATA[0:31] + parity += bit; + val >>= 1; + if(bit) val |= 0x80; + } + if(data) data[m] = val; + } + SWD_READ_BIT(bit); // read parity + if((parity ^ bit) & 1U) + ack = DAP_TRANSFER_ERROR; + + // Turnaround + SWD_CLOCK_CYCLE(); + SWD_OUT_ENABLE(); + } + else { // write data + // Turnaround + SWD_CLOCK_CYCLE(); + SWD_OUT_ENABLE(); + + // Write WDATA[0:31] + parity = 0U; + for(m = 0; m < 4; m++) { + val = data[m]; + ACC = val; + if(P) parity++; + for(n = 8U; n; n--) { + SWD_WRITE_BIT(val); + val >>= 1; + } + } + SWD_WRITE_BIT(parity); // write parity bit + } + // Idle cycles + n = idle_cycles; + if(n) { + SWD_SET(0); + for(; n; n--) SWD_CLOCK_CYCLE(); + } + SWD_SET(1); + return(ack); + } + + if((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) { + // Turnaround + SWD_CLOCK_CYCLE(); + SWD_OUT_ENABLE(); + SWD_SET(1); + return(ack); + } + + // Protocol error - clock out 32bits + parity + turnaround + n = 32U + 1U + 1U; + do { + SWD_CLOCK_CYCLE(); // back off data phase + } while(--n); + + SWD_OUT_ENABLE(); + SWD_SET(1); + return(ack); +} + +// =================================================================================== +// Generate JTAG Sequence +// info: sequence information +// tdi: pointer to TDI generated data +// tdo: pointer to TDO captured data +// return: none +// =================================================================================== +void JTAG_Sequence (uint8_t info, const __xdata uint8_t *tdi, __xdata uint8_t *tdo) { + uint8_t i_val; + uint8_t o_val; + uint8_t bit; + uint8_t n, k; + + n = info & JTAG_SEQUENCE_TCK; + if(n == 0U) n = 64U; + + (info & JTAG_SEQUENCE_TMS) ? (TMS_SET(1)) : (TMS_SET(0)); + + while(n) { + i_val = *tdi++; + o_val = 0U; + for (k = 8U; k && n; k--, n--) { + JTAG_CYCLE_TDIO(i_val, bit); + i_val >>= 1; + o_val >>= 1; + o_val |= bit << 7; + } + o_val >>= k; + if(info & JTAG_SEQUENCE_TDO) *tdo++ = (uint8_t)o_val; + } +} + +// =================================================================================== +// JTAG Set IR +// ir: IR value +// return: none +// =================================================================================== +__idata uint8_t jtag_index; +__idata uint8_t jtag_count; +__xdata uint8_t jtag_ir_length[8]; +__xdata uint8_t jtag_ir_before[8]; +__xdata uint8_t jtag_ir_after[8]; +static void JTAG_IR(uint8_t ir) { + uint8_t n; + + TMS_SET(1); + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ + JTAG_CYCLE_TCK(); /* Select-IR-Scan */ + TMS_SET(0); + JTAG_CYCLE_TCK(); /* Capture-IR */ + JTAG_CYCLE_TCK(); /* Shift-IR */ + + TDI_SET(1); + for(n = jtag_ir_before[jtag_index]; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass before data */ + } + for(n = jtag_ir_length[jtag_index] - 1U; n; n--) { + JTAG_CYCLE_TDI(ir); /* Set IR bits (except last) */ + ir >>= 1; + } + n = jtag_ir_after[jtag_index]; + if(n) { + JTAG_CYCLE_TDI(ir); /* Set last IR bit */ + TDI_SET(1); + for(--n; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass after data */ + } + TMS_SET(1); + JTAG_CYCLE_TCK(); /* Bypass & Exit1-IR */ + } + else { + TMS_SET(1); + JTAG_CYCLE_TDI(ir); /* Set last IR bit & Exit1-IR */ + } + + JTAG_CYCLE_TCK(); /* Update-IR */ + TMS_SET(0); + JTAG_CYCLE_TCK(); /* Idle */ + TDI_SET(1); +} + +// =================================================================================== +// JTAG Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +// =================================================================================== +static uint8_t JTAG_Transfer(uint8_t req, __xdata uint8_t *data) { + uint8_t ack; + uint8_t bit; + uint8_t val; + uint8_t n, m; + + TMS_SET(1); + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ + TMS_SET(0); + JTAG_CYCLE_TCK(); /* Capture-DR */ + JTAG_CYCLE_TCK(); /* Shift-DR */ + + for(n = jtag_index; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass before data */ + } + + JTAG_CYCLE_TDIO(req >> 1, bit); /* Set RnW, Get ACK.0 */ + ack = bit << 1; + JTAG_CYCLE_TDIO(req >> 2, bit); /* Set A2, Get ACK.1 */ + ack |= bit << 0; + JTAG_CYCLE_TDIO(req >> 3, bit); /* Set A3, Get ACK.2 */ + ack |= bit << 2; + + if(ack != DAP_TRANSFER_OK) { + /* Exit on error */ + TMS_SET(1); + JTAG_CYCLE_TCK(); /* Exit1-DR */ + goto exit; + } + + if(req & DAP_TRANSFER_RnW) { + /* Read Transfer */ + val = 0U; + for(m = 0; m < 3; m++) { + for(n = 8U; n; n--) { + JTAG_CYCLE_TDO(bit); /* Get D0..D23 */ + val >>= 1; + if(bit) val |= 0x80; + } + if(data) data[m] = val; + } + + val = 0U; + for(n = 7U; n; n--) { + JTAG_CYCLE_TDO(bit); /* Get D24..D30 */ + if(bit) val |= 0x80; + val >>= 1; + } + n = jtag_count - jtag_index - 1U; + if(n) { + JTAG_CYCLE_TDO(bit); /* Get D31 */ + for(--n; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass after data */ + } + TMS_SET(1); + JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ + } + else { + TMS_SET(1); + JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ + } + if(bit) val |= 0x80; + if(data) data[3] = val; + } + else { + /* Write Transfer */ + for(m = 0; m < 3; m++) { + val = data[m]; + for(n = 8U; n; n--) { + JTAG_CYCLE_TDI(val); /* Set D0..D23 */ + val >>= 1; + } + } + + val = data[3]; + for(n = 7U; n; n--) { + JTAG_CYCLE_TDI(val); /* Set D24..D30 */ + val >>= 1; + } + n = jtag_count - jtag_index - 1U; + if(n) { + JTAG_CYCLE_TDI(val); /* Set D31 */ + for(--n; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass after data */ + } + TMS_SET(1); + JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ + } + else { + TMS_SET(1); + JTAG_CYCLE_TDI(val); /* Set D31 & Exit1-DR */ + } + } + +exit: + JTAG_CYCLE_TCK(); /* Update-DR */ + TMS_SET(0); + JTAG_CYCLE_TCK(); /* Idle */ + TDI_SET(1); + + /* Idle cycles */ + n = idle_cycles; + while(n--) JTAG_CYCLE_TCK(); /* Idle */ + + return ack; +} + +// =================================================================================== +// JTAG Read IDCODE register +// return: value read +// =================================================================================== +void JTAG_ReadIDCode(__xdata uint8_t *data) { + uint8_t bit; + uint8_t val; + uint8_t n, m; + + TMS_SET(1); + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ + TMS_SET(0); + JTAG_CYCLE_TCK(); /* Capture-DR */ + JTAG_CYCLE_TCK(); /* Shift-DR */ + + for(n = jtag_index; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass before data */ + } + + val = 0U; + for(m = 0; m < 3; m++) { + for(n = 8U; n; n--) { + JTAG_CYCLE_TDO(bit); /* Get D0..D23 */ + val >>= 1; + if(bit) val |= 0x80; + } + data[m] = val; + } + val = 0U; + for(n = 7U; n; n--) { + JTAG_CYCLE_TDO(bit); /* Get D24..D30 */ + if(bit) val |= 0x80; + val >>= 1; + } + + TMS_SET(1); + JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ + if(bit) val |= 0x80; + data[3] = val; + + JTAG_CYCLE_TCK(); /* Update-DR */ + TMS_SET(0); + JTAG_CYCLE_TCK(); /* Idle */ +} + +// =================================================================================== +// Process SWJ Pins command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +// =================================================================================== +static uint8_t DAP_SWJ_Pins(const __xdata uint8_t *req, __xdata uint8_t *res) { + uint8_t value; + uint8_t select; + uint16_t wait; + + value = * (req + 0); + select = (uint8_t) * (req + 1); + wait = (uint16_t)(*(req + 2) << 0) | (uint16_t)(*(req + 3) << 8); + if((uint8_t)(*(req + 4)) || (uint8_t)(*(req + 5))) wait |= 0x8000; + + if((select & DAP_SWJ_SWCLK_TCK_BIT) != 0U) { + ((value & DAP_SWJ_SWCLK_TCK_BIT) != 0U) ? (SWK_SET(1)) : (SWK_SET(0)); + } + if((select & DAP_SWJ_SWDIO_TMS_BIT) != 0U) { + ((value & DAP_SWJ_SWDIO_TMS_BIT) != 0U) ? (SWD_SET(1)) : (SWD_SET(0)); + } + if ((select & (1U << DAP_SWJ_TDI)) != 0U) { + TDI_SET(value >> DAP_SWJ_TDI); + } + if ((select & (1U << DAP_SWJ_nTRST)) != 0U) { + TRST_SET(value >> DAP_SWJ_nTRST); + } + if((select & DAP_SWJ_nRESET_BIT) != 0U) { + RST_SET(value >> DAP_SWJ_nRESET); + } + + if(wait != 0U) { + do { + if((select & DAP_SWJ_SWCLK_TCK_BIT) != 0U) { + if((value >> DAP_SWJ_SWCLK_TCK) ^ (SWK_GET())) continue; + } + if((select & DAP_SWJ_SWDIO_TMS_BIT) != 0U) { + if((value >> DAP_SWJ_SWDIO_TMS) ^ (SWD_GET())) continue; + } + if ((select & (1U << DAP_SWJ_TDI)) != 0U) { + if ((value >> DAP_SWJ_TDI) ^ TDI_GET()) continue; + } + if ((select & (1U << DAP_SWJ_nTRST)) != 0U) { + if ((value >> DAP_SWJ_nTRST) ^ TRST_GET()) continue; + } + if((select & DAP_SWJ_nRESET_BIT) != 0U) { + if((value >> DAP_SWJ_nRESET) ^ (RST_GET())) continue; + } + break; + } while(wait--); + } + + value = ((uint8_t)SWK_GET() << DAP_SWJ_SWCLK_TCK) + | ((uint8_t)SWD_GET() << DAP_SWJ_SWDIO_TMS) + | ((uint8_t)TDI_GET() << DAP_SWJ_TDI) + | ((uint8_t)TDO_GET() << DAP_SWJ_TDO) + | ((uint8_t)TRST_GET() << DAP_SWJ_nTRST) + | ((uint8_t)RST_GET() << DAP_SWJ_nRESET); + *res = value; + return 1; +} + +// =================================================================================== +// Process SWJ Sequence command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +// =================================================================================== +static uint8_t DAP_SWJ_Sequence(const __xdata uint8_t *req, __xdata uint8_t *res) { + uint8_t count; + count = *req++; + if(count == 0U) count = 255U; + SWJ_Sequence(count, req); + *res = DAP_OK; + return 1; +} + +// =================================================================================== +// Process SWD Sequence command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +// =================================================================================== +static uint8_t DAP_SWD_Sequence(const __xdata uint8_t *req, __xdata uint8_t *res) { + uint8_t sequence_info; + uint8_t sequence_count; + uint8_t request_count; + uint8_t response_count; + uint8_t count; + + *res++ = DAP_OK; + request_count = 1U; + response_count = 1U; + sequence_count = *req++; + + while(sequence_count--) { + sequence_info = *req++; + count = sequence_info & SWD_SEQUENCE_CLK; + if(count == 0U) count = 64U; + count = (count + 7U) / 8U; + if((sequence_info & SWD_SEQUENCE_DIN) != 0U) SWD_OUT_DISABLE(); + else SWD_OUT_ENABLE(); + SWD_Sequence(sequence_info, req, res); + if(sequence_count == 0U) SWD_OUT_ENABLE(); + if((sequence_info & SWD_SEQUENCE_DIN) != 0U) { + request_count++; + res += count; + response_count += count; + } + else { + req += count; + request_count += count + 1U; + } + } + return response_count; +} + +// =================================================================================== +// Process JTAG Sequence command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +// =================================================================================== +static uint8_t DAP_JTAG_Sequence(const __xdata uint8_t *req, __xdata uint8_t *res) { + uint8_t sequence_info; + uint8_t sequence_count; + uint8_t request_count; + uint8_t response_count; + uint8_t count; + + *res++ = DAP_OK; + request_count = 1U; + response_count = 1U; + sequence_count = *req++; + + while(sequence_count--) { + sequence_info = *req++; + count = sequence_info & JTAG_SEQUENCE_TCK; + if(count == 0U) count = 64U; + count = (count + 7U) / 8U; + JTAG_Sequence(sequence_info, req, res); + req += count; + request_count += count + 1U; + if((sequence_info & JTAG_SEQUENCE_TDO) != 0U) { + res += count; + response_count += count; + } + } + return response_count; +} + +// =================================================================================== +// Process JTAG Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +// =================================================================================== +static uint8_t DAP_JTAG_Configure(const __xdata uint8_t *req, __xdata uint8_t *res) { + uint8_t count; + uint8_t length; + uint8_t bits; + uint8_t n; + + count = *req++; + if(count > 8) count = 8; + jtag_count = count; + + bits = 0U; + for(n = 0U; n < count; n++) { + length = *req++; + jtag_ir_length[n] = length; + jtag_ir_before[n] = bits; + bits += length; + } + for (n = 0U; n < count; n++) { + bits -= jtag_ir_length[n]; + jtag_ir_after[n] = bits; + } + + *res = DAP_OK; + return 1; +} + +// =================================================================================== +// Process JTAG IDCODE command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +// =================================================================================== +__xdata uint8_t data[4]; +static uint8_t DAP_JTAG_IDCode(const __xdata uint8_t *req, __xdata uint8_t *res) { + if(debug_port != DAP_PORT_JTAG) goto id_error; + + // Device index (JTAP TAP) + jtag_index = *req; + if(jtag_index >= jtag_count) goto id_error; + + // Select JTAG chain + JTAG_IR(JTAG_IDCODE); + + // Read IDCODE register + JTAG_ReadIDCode(data); + + // Store Data + *(res+0) = DAP_OK; + *(res+1) = (uint8_t)(data[0]); + *(res+2) = (uint8_t)(data[1]); + *(res+3) = (uint8_t)(data[2]); + *(res+4) = (uint8_t)(data[3]); + + return 5; + +id_error: + *res = DAP_ERROR; + return 1; +} + +// =================================================================================== +// Process Transfer Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +// =================================================================================== +__idata uint16_t retry_count; +__idata uint16_t match_retry; +static uint8_t DAP_TransferConfigure(const __xdata uint8_t *req, __xdata uint8_t *res) { + idle_cycles = *(req + 0); + retry_count = (uint16_t) * (req + 1) + | (uint16_t)(*(req + 2) << 8); + match_retry = (uint16_t) * (req + 3) + | (uint16_t)(*(req + 4) << 8); + *res = DAP_OK; + return 1; +} + +// =================================================================================== +// Process SWD Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +// =================================================================================== +__idata uint8_t match_mask[4]; +__idata uint8_t match_value[4]; +__idata uint8_t DAP_TransferAbort = 0U; +__idata uint8_t request_count; +__idata uint8_t request_value; +__idata uint8_t response_count; +__idata uint8_t response_value; +__idata uint16_t retry; +static uint8_t DAP_SWD_Transfer(const __xdata uint8_t *req, __xdata uint8_t *res) { + const __xdata uint8_t *request_head; + __xdata uint8_t *response_head; + uint8_t post_read; + uint8_t check_write; + + request_head = req; + response_count = 0U; + response_value = 0U; + response_head = res; + res += 2; + DAP_TransferAbort = 0U; + post_read = 0U; + check_write = 0U; + + req++; // ignore DAP index + request_count = *req++; + for(; request_count != 0U; request_count--) { + request_value = *req++; + + // RnW == 1 for read, 0 for write + if(request_value & DAP_TRANSFER_RnW) { + // Read registers + if(post_read) { + // Read was posted before + retry = retry_count; + if((request_value & (DAP_TRANSFER_APnDP | DAP_TRANSFER_MATCH_VALUE)) == DAP_TRANSFER_APnDP) { + // Read previous AP data and post next AP read + do { + response_value = SWD_Transfer(request_value, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + else { + // Read previous AP data + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + post_read = 0U; + } + if(response_value != DAP_TRANSFER_OK) break; + + // Store previous AP data + *res++ = (uint8_t)data[0]; + *res++ = (uint8_t)data[1]; + *res++ = (uint8_t)data[2]; + *res++ = (uint8_t)data[3]; + } + if((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + match_value[0] = (uint8_t)(*(req + 0)); + match_value[1] = (uint8_t)(*(req + 1)); + match_value[2] = (uint8_t)(*(req + 2)); + match_value[3] = (uint8_t)(*(req + 3)); + req += 4; + match_retry = match_retry; + if((request_value & DAP_TRANSFER_APnDP) != 0U) { + // Post AP read + retry = retry_count; + do { + response_value = SWD_Transfer(request_value, NULL); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) break; + } + do { + // Read registers until its value matches or retry counter expires + retry = retry_count; + do { + response_value = SWD_Transfer(request_value, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) break; + } + while(((data[0] & match_mask[0]) != match_value[0] || + (data[1] & match_mask[1]) != match_value[1] || + (data[2] & match_mask[2]) != match_value[2] || + (data[3] & match_mask[3]) != match_value[3]) && + match_retry-- && !DAP_TransferAbort); + if((data[0] & match_mask[0]) != match_value[0] || + (data[1] & match_mask[1]) != match_value[1] || + (data[2] & match_mask[2]) != match_value[2] || + (data[3] & match_mask[3]) != match_value[3]) + response_value |= DAP_TRANSFER_MISMATCH; + if(response_value != DAP_TRANSFER_OK) break; + } + else { + // Normal read + retry = retry_count; + if((request_value & DAP_TRANSFER_APnDP) != 0U) { + // Read AP registers + if(post_read == 0U) { + // Post AP read + do { + response_value = SWD_Transfer(request_value, NULL); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) break; + post_read = 1U; + } + } + else { + // Read DP register + do { + response_value = SWD_Transfer(request_value, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) break; + + // Store data + *res++ = data[0]; + *res++ = data[1]; + *res++ = data[2]; + *res++ = data[3]; + } + } + check_write = 0U; + } + else { // RnW == 0 + // Write register + if(post_read) { + // Read previous data + retry = retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) break; + + // Store previous data + *res++ = data[0]; + *res++ = data[1]; + *res++ = data[2]; + *res++ = data[3]; + post_read = 0U; + } + // Load data + data[0] = (uint8_t)(*(req + 0)); + data[1] = (uint8_t)(*(req + 1)); + data[2] = (uint8_t)(*(req + 2)); + data[3] = (uint8_t)(*(req + 3)); + req += 4; + if((request_value & DAP_TRANSFER_MATCH_MASK) != 0U) { + // Write match mask + match_mask[0] = data[0]; + match_mask[1] = data[1]; + match_mask[2] = data[2]; + match_mask[3] = data[3]; + response_value = DAP_TRANSFER_OK; + } + else { + // Write DP/AP register + retry = retry_count; + do { + response_value = SWD_Transfer(request_value, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) break; + check_write = 1U; + } + } + response_count++; + if(DAP_TransferAbort) break; + } + + for(; request_count != 0U; request_count--) { + // Process canceled requests + request_value = *req++; + if((request_value & DAP_TRANSFER_RnW) != 0U) { // Read register + if((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) req += 4; + } + else req += 4; // Write register + } + + if(response_value == DAP_TRANSFER_OK) { + if(post_read) { + // Read previous data + retry = retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) goto end; + + // Store previous data + *res++ = (uint8_t)data[0]; + *res++ = (uint8_t)data[1]; + *res++ = (uint8_t)data[2]; + *res++ = (uint8_t)data[3]; + } + else if(check_write) { + // Check last write + retry = retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + } + +end: + *(response_head + 0) = (uint8_t)response_count; + *(response_head + 1) = (uint8_t)response_value; + return((uint8_t)(res - response_head)); +} + +// =================================================================================== +// Process JTAG Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +// =================================================================================== +__idata uint8_t request_ir; +__idata uint8_t ir; +static uint8_t DAP_JTAG_Transfer(const __xdata uint8_t *req, __xdata uint8_t *res) { + const __xdata uint8_t *request_head; + __xdata uint8_t *response_head; + uint8_t post_read; + + request_head = req; + response_count = 0U; + response_value = 0U; + response_head = res; + res += 2; + DAP_TransferAbort = 0U; + ir = 0U; + post_read = 0U; + + // Device index (JTAP TAP) + jtag_index = *req++; + if(jtag_index >= jtag_count) goto end; + request_count = *req++; + + for(; request_count != 0U; request_count--) { + request_value = *req++; + request_ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC; + if((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if(post_read) { + // Read was posted before + retry = retry_count; + if((ir == request_ir) && ((request_value & DAP_TRANSFER_MATCH_VALUE) == 0U)) { + // Read previous data and post next read + do { + response_value = JTAG_Transfer(request_value, data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + else { + // Select JTAG chain + if(ir != JTAG_DPACC) { + ir = JTAG_DPACC; + JTAG_IR(ir); + } + // Read previous data + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + post_read = 0U; + } + if(response_value != DAP_TRANSFER_OK) break; + + // Store previous data + *res++ = (uint8_t)data[0]; + *res++ = (uint8_t)data[1]; + *res++ = (uint8_t)data[2]; + *res++ = (uint8_t)data[3]; + } + if((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + match_value[0] = (uint8_t)(*(req + 0)); + match_value[1] = (uint8_t)(*(req + 1)); + match_value[2] = (uint8_t)(*(req + 2)); + match_value[3] = (uint8_t)(*(req + 3)); + req += 4; + match_retry = match_retry; + // Select JTAG chain + if(ir != request_ir) { + ir = request_ir; + JTAG_IR(ir); + } + // Post DP/AP read + retry = retry_count; + do { + response_value = JTAG_Transfer(request_value, NULL); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) break; + do { + // Read register until its value matches or retry counter expires + retry = retry_count; + do { + response_value = JTAG_Transfer(request_value, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) break; + } + while(((data[0] & match_mask[0]) != match_value[0] || + (data[1] & match_mask[1]) != match_value[1] || + (data[2] & match_mask[2]) != match_value[2] || + (data[3] & match_mask[3]) != match_value[3]) && + match_retry-- && !DAP_TransferAbort); + if((data[0] & match_mask[0]) != match_value[0] || + (data[1] & match_mask[1]) != match_value[1] || + (data[2] & match_mask[2]) != match_value[2] || + (data[3] & match_mask[3]) != match_value[3]) + response_value |= DAP_TRANSFER_MISMATCH; + if(response_value != DAP_TRANSFER_OK) break; + } + else { + // Normal read + if (post_read == 0U) { + // Select JTAG chain + if(ir != request_ir) { + ir = request_ir; + JTAG_IR(ir); + } + // Post DP/AP read + retry = retry_count; + do { + response_value = JTAG_Transfer(request_value, NULL); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) break; + post_read = 1U; + } + } + } + else { + // Write register + if (post_read) { + // Select JTAG chain + if(ir != JTAG_DPACC) { + ir = JTAG_DPACC; + JTAG_IR(ir); + } + // Read previous data + retry = retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) break; + + // Store previous data + *res++ = data[0]; + *res++ = data[1]; + *res++ = data[2]; + *res++ = data[3]; + post_read = 0U; + } + // Load data + data[0] = (uint8_t)(*(req + 0)); + data[1] = (uint8_t)(*(req + 1)); + data[2] = (uint8_t)(*(req + 2)); + data[3] = (uint8_t)(*(req + 3)); + req += 4; + if ((request_value & DAP_TRANSFER_MATCH_MASK) != 0U) { + // Write match mask + match_mask[0] = data[0]; + match_mask[1] = data[1]; + match_mask[2] = data[2]; + match_mask[3] = data[3]; + response_value = DAP_TRANSFER_OK; + } + else { + // Select JTAG chain + if(ir != request_ir) { + ir = request_ir; + JTAG_IR(ir); + } + // Write DP/AP register + retry = retry_count; + do { + response_value = JTAG_Transfer(request_value, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) break; + } + } + response_count++; + if(DAP_TransferAbort) break; + } + + for (; request_count != 0U; request_count--) { + // Process canceled requests + request_value = *req++; + if((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) req += 4; + } + else req += 4; // Write register + } + + if(response_value == DAP_TRANSFER_OK) { + // Select JTAG chain + if(ir != JTAG_DPACC) { + ir = JTAG_DPACC; + JTAG_IR(ir); + } + if(post_read) { + // Read previous data + retry = retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) goto end; + + // Store previous data + *res++ = (uint8_t)data[0]; + *res++ = (uint8_t)data[1]; + *res++ = (uint8_t)data[2]; + *res++ = (uint8_t)data[3]; + } + else { + // Check last write + retry = retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + } + +end: + *(response_head+0) = (uint8_t)response_count; + *(response_head+1) = (uint8_t)response_value; + return((uint8_t)(res - response_head)); +} + +// =================================================================================== +// Process SWD Transfer Block command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +// =================================================================================== +static uint8_t DAP_SWD_TransferBlock(const __xdata uint8_t *req, __xdata uint8_t *res) { + __xdata uint8_t *response_head; + response_count = 0U; + response_value = 0U; + response_head = res; + res += 3; + DAP_TransferAbort = 0U; + req++; // ignore DAP index + request_count = (uint16_t)(*(req + 0) << 0) + | (uint16_t)(*(req + 1) << 8); + req += 2; + if(request_count == 0U) goto end; + + request_value = *req++; + if((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register block + if((request_value & DAP_TRANSFER_APnDP) != 0U) { + // Post AP read + retry = retry_count; + do { + response_value = SWD_Transfer(request_value, NULL); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) goto end; + } + while(request_count--) { + // Read DP/AP register + if((request_count == 0U) && ((request_value & DAP_TRANSFER_APnDP) != 0U)) + request_value = DP_RDBUFF | DAP_TRANSFER_RnW; // Last AP read + retry = retry_count; + do { + response_value = SWD_Transfer(request_value, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) goto end; + + // Store data + *res++ = (uint8_t)data[0]; + *res++ = (uint8_t)data[1]; + *res++ = (uint8_t)data[2]; + *res++ = (uint8_t)data[3]; + response_count++; + } + } + else { + // Write register block + while(request_count--) { + // Load data + data[0] = (uint8_t)(*(req + 0)); + data[1] = (uint8_t)(*(req + 1)); + data[2] = (uint8_t)(*(req + 2)); + data[3] = (uint8_t)(*(req + 3)); + req += 4; + + // Write DP/AP register + retry = retry_count; + do { + response_value = SWD_Transfer(request_value, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) goto end; + response_count++; + } + // Check last write + retry = retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + +end: + *(response_head + 0) = response_count; + *(response_head + 1) = 0; + *(response_head + 2) = response_value; + return((uint8_t)(res - response_head)); +} + +// =================================================================================== +// Process JTAG Transfer Block command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +// =================================================================================== +static uint8_t DAP_JTAG_TransferBlock(const __xdata uint8_t *req, __xdata uint8_t *res) { + __xdata uint8_t *response_head; + response_count = 0U; + response_value = 0U; + response_head = res; + res += 3; + DAP_TransferAbort = 0U; + + // Device index (JTAP TAP) + jtag_index = *req++; + if(jtag_index >= jtag_count) goto end; + + request_count = (uint16_t)(*(req + 0) << 0) + | (uint16_t)(*(req + 1) << 8); + req += 2; + if(request_count == 0U) goto end; + request_value = *req++; + + // Select JTAG chain + ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC; + JTAG_IR(ir); + + if((request_value & DAP_TRANSFER_RnW) != 0U) { + // Post read + retry = retry_count; + do { + response_value = JTAG_Transfer(request_value, NULL); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) goto end; + + // Read register block + while(request_count--) { + // Read DP/AP register + if(request_count == 0U) { + // Last read + if(ir != JTAG_DPACC) JTAG_IR(JTAG_DPACC); + request_value = DP_RDBUFF | DAP_TRANSFER_RnW; + } + retry = retry_count; + do { + response_value = JTAG_Transfer(request_value, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) goto end; + + // Store data + *res++ = (uint8_t)data[0]; + *res++ = (uint8_t)data[1]; + *res++ = (uint8_t)data[2]; + *res++ = (uint8_t)data[3]; + response_count++; + } + } + else { + // Write register block + while(request_count--) { + // Load data + data[0] = (uint8_t)(*(req + 0)); + data[1] = (uint8_t)(*(req + 1)); + data[2] = (uint8_t)(*(req + 2)); + data[3] = (uint8_t)(*(req + 3)); + req += 4; + + // Write DP/AP register + retry = retry_count; + do { + response_value = JTAG_Transfer(request_value, data); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if(response_value != DAP_TRANSFER_OK) goto end; + response_count++; + } + + // Check last write + if(ir != JTAG_DPACC) JTAG_IR(JTAG_DPACC); + retry = retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + +end: + *(response_head + 0) = response_count; + *(response_head + 1) = 0; + *(response_head + 2) = response_value; + return((uint8_t)(res - response_head)); +} + +// =================================================================================== +// Process Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +// =================================================================================== +static uint8_t DAP_Transfer(const __xdata uint8_t *req, __xdata uint8_t *res) { + switch(debug_port) { + case DAP_PORT_SWD: + return DAP_SWD_Transfer(req, res); + case DAP_PORT_JTAG: + return DAP_JTAG_Transfer(req, res); + default: + *(res + 0) = 0U; + *(res + 1) = 0U; + break; + } + return 2; +} + +// =================================================================================== +// Process SWD Transfer Block command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +// =================================================================================== +static uint8_t DAP_TransferBlock(const __xdata uint8_t *req, __xdata uint8_t *res) { + switch(debug_port) { + case DAP_PORT_SWD: + return DAP_SWD_TransferBlock(req, res); + case DAP_PORT_JTAG: + return DAP_JTAG_TransferBlock(req, res); + default: + *(res + 0) = 0U; // res count [7:0] + *(res + 1) = 0U; // res count[15:8] + *(res + 2) = 0U; // res value + break; + } + return 3; +} + +// =================================================================================== +// DAP Thread. +// =================================================================================== +uint8_t DAP_Thread(void) { + uint8_t num; + uint8_t __xdata *req = DAP_READ_BUF_PTR; + uint8_t __xdata *res = DAP_WRITE_BUF_PTR; + + *res++ = *req; + switch(*req++) { + case ID_DAP_Info: + num = DAP_Info(*req, res + 1); + *res = (uint8_t)num; + num++; + break; + case ID_DAP_HostStatus: + num = DAP_HostStatus(req, res); + break; + case ID_DAP_Connect: + num = DAP_Connect(req, res); + break; + case ID_DAP_Disconnect: + num = DAP_Disconnect(res); + break; + + case ID_DAP_SWJ_Pins: + num = DAP_SWJ_Pins(req, res); + break; + case ID_DAP_SWJ_Clock: + *res = DAP_OK; + num = 1; + break; + case ID_DAP_SWJ_Sequence: + num = DAP_SWJ_Sequence(req, res); + break; + + case ID_DAP_SWD_Configure: + *res = DAP_OK; + num = 1; + break; + case ID_DAP_SWD_Sequence: + num = DAP_SWD_Sequence(req, res); + break; + + case ID_DAP_JTAG_Sequence: + num = DAP_JTAG_Sequence(req, res); + break; + case ID_DAP_JTAG_Configure: + num = DAP_JTAG_Configure(req, res); + break; + case ID_DAP_JTAG_IDCODE: + num = DAP_JTAG_IDCode(req, res); + break; + + case ID_DAP_TransferConfigure: + num = DAP_TransferConfigure(req, res); + break; + case ID_DAP_Transfer: + num = DAP_SWD_Transfer(req, res); + break; + case ID_DAP_TransferBlock: + num = DAP_TransferBlock(req, res); + break; + + case ID_DAP_WriteABORT: + *res = DAP_OK; + num = 1; + break; + case ID_DAP_ExecuteCommands: + case ID_DAP_QueueCommands: + default: + *(res - 1) = ID_DAP_Invalid; + num = 1; + break; + } + return(num + 1); +} diff --git a/software/src/dap.h b/software/src/dap.h new file mode 100644 index 0000000..776ae09 --- /dev/null +++ b/software/src/dap.h @@ -0,0 +1,204 @@ +// =================================================================================== +// CMSIS-DAP Definitions +// =================================================================================== +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. December 2017 + * $Revision: V2.0.0 + * + * Project: CMSIS-DAP Include + * Title: DAP.h Definitions + * + *---------------------------------------------------------------------------*/ + +#pragma once + +#include +#include "dap_io.h" + +// DAP Firmware Version +#define DAP_FW_VER "1.2.1" + +// DAP Command IDs +#define ID_DAP_Info 0x00U +#define ID_DAP_HostStatus 0x01U +#define ID_DAP_Connect 0x02U +#define ID_DAP_Disconnect 0x03U +#define ID_DAP_TransferConfigure 0x04U +#define ID_DAP_Transfer 0x05U +#define ID_DAP_TransferBlock 0x06U +#define ID_DAP_TransferAbort 0x07U +#define ID_DAP_WriteABORT 0x08U +#define ID_DAP_Delay 0x09U +#define ID_DAP_ResetTarget 0x0AU +#define ID_DAP_SWJ_Pins 0x10U +#define ID_DAP_SWJ_Clock 0x11U +#define ID_DAP_SWJ_Sequence 0x12U +#define ID_DAP_SWD_Configure 0x13U +#define ID_DAP_SWD_Sequence 0x1DU +#define ID_DAP_JTAG_Sequence 0x14U +#define ID_DAP_JTAG_Configure 0x15U +#define ID_DAP_JTAG_IDCODE 0x16U +#define ID_DAP_SWO_Transport 0x17U +#define ID_DAP_SWO_Mode 0x18U +#define ID_DAP_SWO_Baudrate 0x19U +#define ID_DAP_SWO_Control 0x1AU +#define ID_DAP_SWO_Status 0x1BU +#define ID_DAP_SWO_ExtendedStatus 0x1EU +#define ID_DAP_SWO_Data 0x1CU + +#define ID_DAP_QueueCommands 0x7EU +#define ID_DAP_ExecuteCommands 0x7FU + +// DAP Vendor Command IDs +#define ID_DAP_Vendor0 0x80U +#define ID_DAP_Vendor1 0x81U +#define ID_DAP_Vendor2 0x82U +#define ID_DAP_Vendor3 0x83U +#define ID_DAP_Vendor4 0x84U +#define ID_DAP_Vendor5 0x85U +#define ID_DAP_Vendor6 0x86U +#define ID_DAP_Vendor7 0x87U +#define ID_DAP_Vendor8 0x88U +#define ID_DAP_Vendor9 0x89U +#define ID_DAP_Vendor10 0x8AU +#define ID_DAP_Vendor11 0x8BU +#define ID_DAP_Vendor12 0x8CU +#define ID_DAP_Vendor13 0x8DU +#define ID_DAP_Vendor14 0x8EU +#define ID_DAP_Vendor15 0x8FU +#define ID_DAP_Vendor16 0x90U +#define ID_DAP_Vendor17 0x91U +#define ID_DAP_Vendor18 0x92U +#define ID_DAP_Vendor19 0x93U +#define ID_DAP_Vendor20 0x94U +#define ID_DAP_Vendor21 0x95U +#define ID_DAP_Vendor22 0x96U +#define ID_DAP_Vendor23 0x97U +#define ID_DAP_Vendor24 0x98U +#define ID_DAP_Vendor25 0x99U +#define ID_DAP_Vendor26 0x9AU +#define ID_DAP_Vendor27 0x9BU +#define ID_DAP_Vendor28 0x9CU +#define ID_DAP_Vendor29 0x9DU +#define ID_DAP_Vendor30 0x9EU +#define ID_DAP_Vendor31 0x9FU + +#define ID_DAP_Invalid 0xFFU + +// DAP Status Code +#define DAP_OK 0U +#define DAP_ERROR 0xFFU + +// DAP ID +#define DAP_ID_VENDOR 1U +#define DAP_ID_PRODUCT 2U +#define DAP_ID_SER_NUM 3U +#define DAP_ID_FW_VER 4U +#define DAP_ID_DEVICE_VENDOR 5U +#define DAP_ID_DEVICE_NAME 6U +#define DAP_ID_CAPABILITIES 0xF0U +#define DAP_ID_TIMESTAMP_CLOCK 0xF1U +#define DAP_ID_SWO_BUFFER_SIZE 0xFDU +#define DAP_ID_PACKET_COUNT 0xFEU +#define DAP_ID_PACKET_SIZE 0xFFU + +// DAP Host Status +#define DAP_DEBUGGER_CONNECTED 0U +#define DAP_TARGET_RUNNING 1U + +// DAP Port +#define DAP_PORT_AUTODETECT 0U // Autodetect Port +#define DAP_PORT_DISABLED 0U // Port Disabled (I/O pins in High-Z) +#define DAP_PORT_SWD 1U // SWD Port (SWCLK, SWDIO) + nRESET +#define DAP_PORT_JTAG 2U // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET + +// DAP SWJ Pins +#define DAP_SWJ_SWCLK_TCK 0 // SWCLK/TCK +#define DAP_SWJ_SWDIO_TMS 1 // SWDIO/TMS +#define DAP_SWJ_TDI 2 // TDI +#define DAP_SWJ_TDO 3 // TDO +#define DAP_SWJ_nTRST 5 // nTRST +#define DAP_SWJ_nRESET 7 // nRESET + +#define DAP_SWJ_SWCLK_TCK_BIT 0x01 // SWCLK/TCK +#define DAP_SWJ_SWDIO_TMS_BIT 0x02 // SWDIO/TMS +#define DAP_SWJ_TDI_BIT 0x04 // TDI +#define DAP_SWJ_TDO_BIT 0x08 // TDO +#define DAP_SWJ_nTRST_BIT 0x20 // nTRST +#define DAP_SWJ_nRESET_BIT 0x80 // nRESET + +// DAP Transfer Request +#define DAP_TRANSFER_APnDP (1U << 0) +#define DAP_TRANSFER_RnW (1U << 1) +#define DAP_TRANSFER_A2 (1U << 2) +#define DAP_TRANSFER_A3 (1U << 3) +#define DAP_TRANSFER_MATCH_VALUE (1U << 4) +#define DAP_TRANSFER_MATCH_MASK (1U << 5) +#define DAP_TRANSFER_TIMESTAMP (1U << 7) + +// DAP Transfer Response +#define DAP_TRANSFER_OK (1U << 0) +#define DAP_TRANSFER_WAIT (1U << 1) +#define DAP_TRANSFER_FAULT (1U << 2) +#define DAP_TRANSFER_ERROR (1U << 3) +#define DAP_TRANSFER_MISMATCH (1U << 4) + +// DAP SWO Trace Mode +#define DAP_SWO_OFF 0U +#define DAP_SWO_UART 1U +#define DAP_SWO_MANCHESTER 2U + +// DAP SWO Trace Status +#define DAP_SWO_CAPTURE_ACTIVE (1U << 0) +#define DAP_SWO_CAPTURE_PAUSED (1U << 1) +#define DAP_SWO_STREAM_ERROR (1U << 6) +#define DAP_SWO_BUFFER_OVERRUN (1U << 7) + +// Debug Port Register Addresses +#define DP_IDCODE 0x00U // IDCODE Register (SW Read only) +#define DP_ABORT 0x00U // Abort Register (SW Write only) +#define DP_CTRL_STAT 0x04U // Control & Status +#define DP_WCR 0x04U // Wire Control Register (SW Only) +#define DP_SELECT 0x08U // Select Register (JTAG R/W & SW W) +#define DP_RESEND 0x08U // Resend (SW Read Only) +#define DP_RDBUFF 0x0CU // Read Buffer (Read Only) + +// JTAG IR Codes +#define JTAG_ABORT 0x08U +#define JTAG_DPACC 0x0AU +#define JTAG_APACC 0x0BU +#define JTAG_IDCODE 0x0EU +#define JTAG_BYPASS 0x0FU + +// JTAG Sequence Info +#define JTAG_SEQUENCE_TCK 0x3FU // TCK count +#define JTAG_SEQUENCE_TMS 0x40U // TMS value +#define JTAG_SEQUENCE_TDO 0x80U // TDO capture + +// SWD Sequence Info +#define SWD_SEQUENCE_CLK 0x3FU // SWCLK count +#define SWD_SEQUENCE_DIN 0x80U // SWDIO capture + +#define DAP_PACKET_COUNT 1 +#define DAP_PACKET_SIZE 64 // THIS ENDP SIZE +#define DAP_DEFAULT_PORT DAP_PORT_SWD + +extern uint8_t DAP_Thread(void); diff --git a/software/src/dap_io.h b/software/src/dap_io.h new file mode 100644 index 0000000..b5f7cad --- /dev/null +++ b/software/src/dap_io.h @@ -0,0 +1,145 @@ +// =================================================================================== +// CMSIS-DAP CONFIG I/O for CH552 DAPLink +// =================================================================================== + +#pragma once +#include "ch554.h" +#include "gpio.h" +#include "config.h" + + +// =================================================================================== +// SWD PORT CONFIG I/O +// =================================================================================== + +// SWD I/O pin manipulations +#define SWK_SET(val) PIN_write(PIN_SWK, val) +#define SWD_SET(val) PIN_write(PIN_SWD, val) +#define RST_SET(val) PIN_write(PIN_RST, val) +#define SWK_GET() PIN_read(PIN_SWK) +#define SWD_GET() PIN_read(PIN_SWD) +#define RST_GET() PIN_read(PIN_RST) + +#define PIN_DELAY() + +// Connect SWD port (setup port for data transmission) +#define PORT_SWD_CONNECT() { \ + LED_PRT_SET(1); \ +} + +// SWCLK clockout cycle +#define SWD_CLOCK_CYCLE() { \ + SWK_SET(0); \ + PIN_DELAY(); \ + SWK_SET(1); \ +} + +// Write one bit via SWD +#define SWD_WRITE_BIT(bits) { \ + SWD_SET((bits)&1); \ + SWD_CLOCK_CYCLE(); \ +} + +// Read one bit via SWD +#define SWD_READ_BIT(bit) { \ + SWK_SET(0); \ + PIN_DELAY(); \ + bit = SWD_GET(); \ + SWK_SET(1); \ +} + +// Set SWDIO pin to output +#define SWD_OUT_ENABLE() // nothing to be done (open-drain pullup) + +// Set SWDIO pin to input +#define SWD_OUT_DISABLE() SWD_SET(1) + + +// =================================================================================== +// JTAG PORT CONFIG I/O +// =================================================================================== + +// JTAG I/O pin manipulations +#define TCK_SET(val) PIN_write(PIN_SWK, val) +#define TMS_SET(val) PIN_write(PIN_SWD, val) +#define TDO_SET(val) PIN_write(PIN_TDO, val) +#define TDI_SET(val) PIN_write(PIN_TDI, val) +#define TRST_SET(val) PIN_write(PIN_TRST, val) +#define TCK_GET() PIN_read(PIN_SWK) +#define TMS_GET() PIN_read(PIN_SWD) +#define TDO_GET() PIN_read(PIN_TDO) +#define TDI_GET() PIN_read(PIN_TDI) +#define TRST_GET() PIN_read(PIN_TRST) + +// Connect JTAG port (setup port for data transmission) +#define PORT_JTAG_CONNECT() { \ + LED_PRT_SET(1); \ +} + +// JTAG TCK cycle +#define JTAG_CYCLE_TCK() { \ + TCK_SET(0); \ + PIN_DELAY(); \ + TCK_SET(1); \ +} + +// JTAG TDI cycle +#define JTAG_CYCLE_TDI(tdi) { \ + TDI_SET(tdi); \ + JTAG_CYCLE_TCK(); \ +} + +// JTAG TDO cycle +#define JTAG_CYCLE_TDO(tdo) { \ + TCK_SET(0); \ + PIN_DELAY(); \ + tdo = TDO_GET(); \ + TCK_SET(1); \ +} + +// JTAG TDIO cycle +#define JTAG_CYCLE_TDIO(tdi,tdo) { \ + TDI_SET(tdi); \ + TCK_SET(0); \ + PIN_DELAY(); \ + tdo = TDO_GET(); \ + TCK_SET(1); \ +} + + +// =================================================================================== +// GENERAL PORT CONFIG I/O +// =================================================================================== + +// Initial port setup (at firmware start) +#define PORT_SETUP() // nothing to be done (reset values already fit) + +// Disconnect complete port (idle state, input/pullup) +#define PORT_OFF() { \ + SWK_SET(1); \ + SWD_SET(1); \ + TDI_SET(1); \ + TDO_SET(1); \ + RST_SET(1); \ + TRST_SET(1); \ + LED_PRT_SET(0); \ +} + +// LED I/O pin manipulations +#define LED_PRT_SET(val) PIN_write(PIN_LED, !(val)) // LED is active low +#define LED_CON_SET(val) +#define LED_RUN_SET(val) + + +// =================================================================================== +// GENERAL CONFIG +// =================================================================================== + +// HID transfer buffers +#define DAP_READ_BUF_PTR EP1_buffer +#define DAP_WRITE_BUF_PTR EP1_buffer + 64 +extern __xdata uint8_t EP1_buffer[]; + +// DAP init function +#define DAP_init() HID_init(); PORT_SETUP(); +extern void HID_init(void); diff --git a/software/src/delay.c b/software/src/delay.c new file mode 100755 index 0000000..8d68aff --- /dev/null +++ b/software/src/delay.c @@ -0,0 +1,86 @@ +// =================================================================================== +// Delay Functions for CH551, CH552 and CH554 +// =================================================================================== + +#include "delay.h" +#include "ch554.h" + +// =================================================================================== +// Delay in Units of us +// =================================================================================== +void DLY_us(uint16_t n) { // delay in us + #ifdef F_CPU + #if F_CPU <= 6000000 + n >>= 2; + #endif + #if F_CPU <= 3000000 + n >>= 2; + #endif + #if F_CPU <= 750000 + n >>= 4; + #endif + #endif + + while(n) { // total = 12~13 Fsys cycles, 1uS @Fsys=12MHz + SAFE_MOD++; // 2 Fsys cycles, for higher Fsys, add operation here + #ifdef F_CPU + #if F_CPU >= 14000000 + SAFE_MOD++; + #endif + #if F_CPU >= 16000000 + SAFE_MOD++; + #endif + #if F_CPU >= 18000000 + SAFE_MOD++; + #endif + #if F_CPU >= 20000000 + SAFE_MOD++; + #endif + #if F_CPU >= 22000000 + SAFE_MOD++; + #endif + #if F_CPU >= 24000000 + SAFE_MOD++; + #endif + #if F_CPU >= 26000000 + SAFE_MOD++; + #endif + #if F_CPU >= 28000000 + SAFE_MOD++; + #endif + #if F_CPU >= 30000000 + SAFE_MOD++; + #endif + #if F_CPU >= 32000000 + SAFE_MOD++; + #endif + #endif + n--; + } +} + +// =================================================================================== +// Delay in Units of ms +// =================================================================================== +void DLY_ms(uint16_t n) { // delay in ms + while(n) { + DLY_us(1000); + n--; + } +} + +// =================================================================================== +// Delay 20+4*(n-1) Clock Cycles +// =================================================================================== +#pragma callee_saves _delay_more_cycles +void _delay_more_cycles (uint8_t n) __naked { + n; // stop unreferenced arg warning + __asm + .even ; make predictable cycles for jumps + push ar7 ; 2 cycles + mov r7, dpl ; 2 cycles + djnz r7, .+0 ; 2/4 cycles + pop ar7 ; 2 cycles + ret ; 4|5 cycles + __endasm; +} diff --git a/software/src/delay.h b/software/src/delay.h new file mode 100755 index 0000000..d665553 --- /dev/null +++ b/software/src/delay.h @@ -0,0 +1,161 @@ +// =================================================================================== +// Delay Functions for CH551, CH552 and CH554 +// =================================================================================== + +#pragma once +#include + +void DLY_us(uint16_t n); // delay in units of us +void DLY_ms(uint16_t n); // delay in units of ms + +// Delay clock cycles (max. 1039) +// (need to find a smarter way...) +#define DLY_cycles(n) \ + (n == 1 ? (_delay_cycles_1()) : \ + (n == 2 ? (_delay_cycles_2()) : \ + (n == 3 ? (_delay_cycles_3()) : \ + (n == 4 ? (_delay_cycles_4()) : \ + (n == 5 ? (_delay_cycles_5()) : \ + (n == 6 ? (_delay_cycles_6()) : \ + (n == 7 ? (_delay_cycles_7()) : \ + (n == 8 ? (_delay_cycles_8()) : \ + (n == 9 ? (_delay_cycles_9()) : \ + (n == 10 ? (_delay_cycles_10()) : \ + (n == 11 ? (_delay_cycles_11()) : \ + (n == 12 ? (_delay_cycles_12()) : \ + (n == 13 ? (_delay_cycles_13()) : \ + (n == 14 ? (_delay_cycles_14()) : \ + (n == 15 ? (_delay_cycles_15()) : \ + (n == 16 ? (_delay_cycles_16()) : \ + (n == 17 ? (_delay_cycles_17()) : \ + (n == 18 ? (_delay_cycles_18()) : \ + (n == 19 ? (_delay_cycles_19()) : \ + ((n-20)%4 == 0 ? _delay_more_cycles(((n-20)/4)+1) : \ + ((n-20)%4 == 1 ? _delay_more_cycles_1(((n-20)/4)+1) : \ + ((n-20)%4 == 2 ? _delay_more_cycles_2(((n-20)/4)+1) : \ + ((n-20)%4 == 3 ? _delay_more_cycles_3(((n-20)/4)+1) : \ +(0)))))))))))))))))))))))) + +#define _delay_less_cycles(n) _delay_cycles_##n() + +void _delay_more_cycles(uint8_t n); + +inline void _delay_cycles_1(void) { + __asm__("nop"); +} + +inline void _delay_cycles_2(void) { + _delay_cycles_1(); + _delay_cycles_1(); +} + +inline void _delay_cycles_3(void) { + _delay_cycles_2(); + _delay_cycles_1(); +} + +inline void _delay_cycles_4(void) { + _delay_cycles_3(); + _delay_cycles_1(); +} + +inline void _delay_cycles_5(void) { + _delay_cycles_4(); + _delay_cycles_1(); +} + +inline void _delay_cycles_6(void) { + _delay_cycles_5(); + _delay_cycles_1(); +} + +inline void _delay_cycles_7(void) { + _delay_cycles_6(); + _delay_cycles_1(); +} + +inline void _delay_cycles_8(void) { + _delay_cycles_7(); + _delay_cycles_1(); +} + +inline void _delay_cycles_9(void) { + _delay_cycles_8(); + _delay_cycles_1(); +} + +inline void _delay_cycles_10(void) { + _delay_cycles_9(); + _delay_cycles_1(); +} + +inline void _delay_cycles_11(void) { + _delay_cycles_10(); + _delay_cycles_1(); +} + +inline void _delay_cycles_12(void) { + __asm + push a + push b + div ab + pop b + pop a + __endasm; +} + +inline void _delay_cycles_13(void) { + _delay_cycles_12(); + _delay_cycles_1(); +} + +inline void _delay_cycles_14(void) { + _delay_cycles_12(); + _delay_cycles_2(); +} + +inline void _delay_cycles_15(void) { + _delay_cycles_12(); + _delay_cycles_3(); +} + +inline void _delay_cycles_16(void) { + __asm + push a + push b + div ab + div ab + pop b + pop a + __endasm; +} + +inline void _delay_cycles_17(void) { + _delay_cycles_16(); + _delay_cycles_1(); +} + +inline void _delay_cycles_18(void) { + _delay_cycles_16(); + _delay_cycles_2(); +} + +inline void _delay_cycles_19(void) { + _delay_cycles_16(); + _delay_cycles_3(); +} + +inline void _delay_more_cycles_1(uint8_t n) { + _delay_more_cycles(n); + _delay_cycles_1(); +} + +inline void _delay_more_cycles_2(uint8_t n) { + _delay_more_cycles(n); + _delay_cycles_2(); +} + +inline void _delay_more_cycles_3(uint8_t n) { + _delay_more_cycles(n); + _delay_cycles_3(); +} diff --git a/software/src/gpio.h b/software/src/gpio.h new file mode 100644 index 0000000..77d750c --- /dev/null +++ b/software/src/gpio.h @@ -0,0 +1,288 @@ +// =================================================================================== +// Basic GPIO, PWM and ADC Functions for CH551, CH552 and CH554 * v1.4 * +// =================================================================================== +// +// Pins must be defined as P10, P11, P12, etc. - e.g.: +// #define PIN_LED P33 // LED on pin P3.3 +// +// Functions available: +// -------------------- +// PIN_input(PIN) Set PIN as INPUT (high impedance, no pullup) +// PIN_input_PU(PIN) Set PIN as INPUT with internal PULLUP +// PIN_output(PIN) Set PIN as OUTPUT (push-pull) +// PIN_output_OD(PIN) Set PIN as OUTPUT (open-drain) +// +// PIN_low(PIN) Set PIN output value to LOW +// PIN_high(PIN) Set PIN output value to HIGH +// PIN_toggle(PIN) TOGGLE PIN output value +// PIN_read(PIN) Read PIN input value +// PIN_write(PIN, val) Write PIN output value (0 = LOW / 1 = HIGH) +// +// PIN_asm(PIN) Convert PIN for inline assembly: setb PIN_asm(PIN_LED) +// PIN_set(PIN) Convert PIN for direct manipulation: PIN_set(PIN_LED) = 1; +// +// PIN_WAKE_enable(PIN) enable wake-up from sleep by PIN low (P13, P14, P15 only) +// PIN_WAKE_disable(PIN) disable wake-up from sleep by PIN low +// +// PWM_start(PIN) Start PWM output on PIN, can be (P15 or P30) and (P34 or P31) +// PWM_stop(PIN) Stop PWM output on PIN +// PWM_write(PIN, val) Set PWM output active level duty cycle on PIN +// +// PWM_pol_normal(PIN) Set normal PWM polarity on PIN (default low and active high) +// PWM_pol_reverse(PIN) Set reverse PWM polarity on PIN (default high and active low) +// PWM_set_freq(FREQ) Set global PWM frequency (in Hertz) +// +// ADC_enable() Enable ADC +// ADC_disable() Disable ADC +// ADC_fast() Set ADC fast mode ( 96 clock cycles per sample, less accurate) +// ADC_slow() Set ADC slow mode (384 clock cycles per sample, more accurate) +// ADC_input(PIN) Set ADC input pin (P11, P14, P15, P32 only) +// ADC_read() Sample and read ADC value (0..255) +// +// CMP_enable() Enable comparator +// CMP_disable() Disable comparator +// CMP_positive(PIN) Set CMP non-inverting input pin (P11, P14, P15, P32 only) +// CMP_negative(PIN) Set CMP inverting input pin (P14, P32 only) +// CMP_read() Read CMP output (0: pos < neg, 1: pos > neg) +// +// Notes: +// ------ +// Pins used for PWM should be set as OUTPUT beforehand. +// Pins used for ADC or CMP must have been set as INPUT (high impedance) beforehand. +// +// 2022 by Stefan Wagner: https://github.com/wagiminator + +#pragma once +#include +#include "ch554.h" + +// =================================================================================== +// Enumerate pin designators (use these designators to define pins) +// =================================================================================== + +enum{P10, P11, P12, P13, P14, P15, P16, P17, P30, P31, P32, P33, P34, P35, P36, P37}; + +// =================================================================================== +// Helper Defines (these are for internal use only) +// =================================================================================== + +// Define pins for direct bit manipulation +SBIT(PP10, 0x90, 0); +SBIT(PP11, 0x90, 1); +SBIT(PP12, 0x90, 2); +SBIT(PP13, 0x90, 3); +SBIT(PP14, 0x90, 4); +SBIT(PP15, 0x90, 5); +SBIT(PP16, 0x90, 6); +SBIT(PP17, 0x90, 7); +SBIT(PP30, 0xB0, 0); +SBIT(PP31, 0xB0, 1); +SBIT(PP32, 0xB0, 2); +SBIT(PP33, 0xB0, 3); +SBIT(PP34, 0xB0, 4); +SBIT(PP35, 0xB0, 5); +SBIT(PP36, 0xB0, 6); +SBIT(PP37, 0xB0, 7); + +// 2nd-stage glue defines +#define PIN_h_a(PIN) _P##PIN +#define PIN_h_s(PIN) P##PIN + +#define PORT_h_i(PORT, PIN) (P##PORT##_DIR_PU &= ~(1<=P10)&&(PIN<=P17) ? (P1_DIR_PU &= ~(1<<(PIN&7)), P1_MOD_OC &= ~(1<<(PIN&7))) : \ + ((PIN>=P30)&&(PIN<=P37) ? (P3_DIR_PU &= ~(1<<(PIN&7)), P3_MOD_OC &= ~(1<<(PIN&7))) : \ +(0))) + +// =================================================================================== +// Set pin as INPUT with internal PULLUP resistor (also open-drain output, +// when output changes from LOW to HIGH, it will drive HIGH for 2 clock cycles) +// =================================================================================== +#define PIN_input_PU(PIN) \ + ((PIN>=P10)&&(PIN<=P17) ? (P1_MOD_OC |= (1<<(PIN&7)), P1_DIR_PU |= (1<<(PIN&7))) : \ + ((PIN>=P30)&&(PIN<=P37) ? (P3_MOD_OC |= (1<<(PIN&7)), P3_DIR_PU |= (1<<(PIN&7))) : \ +(0))) + +// =================================================================================== +// Set pin as OUTPUT (push-pull) +// =================================================================================== +#define PIN_output(PIN) \ + ((PIN>=P10)&&(PIN<=P17) ? (P1_MOD_OC &= ~(1<<(PIN&7)), P1_DIR_PU |= (1<<(PIN&7))) : \ + ((PIN>=P30)&&(PIN<=P37) ? (P3_MOD_OC &= ~(1<<(PIN&7)), P3_DIR_PU |= (1<<(PIN&7))) : \ +(0))) + +// =================================================================================== +// Set pin as OPEN-DRAIN OUTPUT (also high-impedance input, no pullup) +// =================================================================================== +#define PIN_output_OD(PIN) \ + ((PIN>=P10)&&(PIN<=P17) ? (P1_MOD_OC |= (1<<(PIN&7)), P1_DIR_PU &= ~(1<<(PIN&7))) : \ + ((PIN>=P30)&&(PIN<=P37) ? (P3_MOD_OC |= (1<<(PIN&7)), P3_DIR_PU &= ~(1<<(PIN&7))) : \ +(0))) + +// =================================================================================== +// Pin manipulation macros +// =================================================================================== +#define PIN_low(PIN) PIN_h_s(PIN) = 0 // set pin to LOW +#define PIN_high(PIN) PIN_h_s(PIN) = 1 // set pin to HIGH +#define PIN_toggle(PIN) PIN_h_s(PIN) = !PIN_h_s(PIN) // TOGGLE pin +#define PIN_read(PIN) (PIN_h_s(PIN)) // READ pin +#define PIN_write(PIN, val) PIN_h_s(PIN) = val // WRITE pin value + +// =================================================================================== +// (PORT, PIN) manipulation macros +// =================================================================================== +#define PORT_input(PORT, PIN) PORT_h_i(PORT, PIN) // set pin as INPUT +#define PORT_input_PU(PORT, PIN) PORT_h_iP(PORT, PIN) // set pin as INPUT PULLUP +#define PORT_output(PORT, PIN) PORT_h_o(PORT, PIN) // set pin as OUTPUT +#define PORT_output_OD(PORT, PIN) PORT_h_oO(PORT, PIN) // set pin as OUTPUT OPEN-DRAIN + +#define PORT_low(PORT, PIN) PORT_h_l(PORT, PIN) // set pin to LOW +#define PORT_high(PORT, PIN) PORT_h_h(PORT, PIN) // set pin to HIGH +#define PORT_toggle(PORT, PIN) PORT_h_t(PORT, PIN) // TOGGLE pin +#define PORT_read(PORT, PIN) PORT_h_r(PORT, PIN) // READ pin +#define PORT_write(PORT,PIN,val) PORT_h_w(PORT, PIN, val) // WRITE pin value + +// =================================================================================== +// Convert pin for inline assembly and direct manipulation +// =================================================================================== +#define PIN_asm(PIN) PIN_h_a(PIN) +#define PIN_set(PIN) PIN_h_s(PIN) + +// =================================================================================== +// Enable/disable WAKE-up from sleep by pin LOW (P13, P14, P15 only) +// =================================================================================== +#define WAKE_PIN_enable(PIN) \ + ((PIN == P13) ? (WAKE_CTRL |= bWAK_P1_3_LO) : \ + ((PIN == P14) ? (WAKE_CTRL |= bWAK_P1_4_LO) : \ + ((PIN == P15) ? (WAKE_CTRL |= bWAK_P1_5_LO) : \ +(0))))) + +#define WAKE_PIN_disable(PIN) \ + ((PIN == P13) ? (WAKE_CTRL &= ~bWAK_P1_3_LO) : \ + ((PIN == P14) ? (WAKE_CTRL &= ~bWAK_P1_4_LO) : \ + ((PIN == P15) ? (WAKE_CTRL &= ~bWAK_P1_5_LO) : \ +(0))))) + +// =================================================================================== +// Start PWM on pin, must be a PWM-capable pin: (P15 or P30) and (P34 or P31) +// =================================================================================== +#define PWM_start(PIN) \ + ((PIN == P15) ? (PWM_CTRL &= ~bPWM_CLR_ALL, PIN_FUNC &= ~bPWM1_PIN_X, PWM_CTRL |= bPWM1_OUT_EN) : \ + ((PIN == P34) ? (PWM_CTRL &= ~bPWM_CLR_ALL, PIN_FUNC &= ~bPWM2_PIN_X, PWM_CTRL |= bPWM2_OUT_EN) : \ + ((PIN == P30) ? (PWM_CTRL &= ~bPWM_CLR_ALL, PIN_FUNC |= bPWM1_PIN_X, PWM_CTRL |= bPWM1_OUT_EN) : \ + ((PIN == P31) ? (PWM_CTRL &= ~bPWM_CLR_ALL, PIN_FUNC |= bPWM2_PIN_X, PWM_CTRL |= bPWM2_OUT_EN) : \ +(0))))) + +// =================================================================================== +// Set PWM output active level duty cycle on pin +// =================================================================================== +#define PWM_write(PIN, val) \ + ((PIN == P15) ? (PWM_DATA1 = val) : \ + ((PIN == P34) ? (PWM_DATA2 = val) : \ + ((PIN == P30) ? (PWM_DATA1 = val) : \ + ((PIN == P31) ? (PWM_DATA2 = val) : \ +(0))))) + +// =================================================================================== +// Stop PWM on pin +// =================================================================================== +#define PWM_stop(PIN) \ + ((PIN == P15) ? (PWM_CTRL &= ~bPWM1_OUT_EN) : \ + ((PIN == P34) ? (PWM_CTRL &= ~bPWM2_OUT_EN) : \ + ((PIN == P30) ? (PWM_CTRL &= ~bPWM1_OUT_EN) : \ + ((PIN == P31) ? (PWM_CTRL &= ~bPWM2_OUT_EN) : \ +(0))))) + +// =================================================================================== +// Set normal PWM polarity on pin (default low and active high) +// =================================================================================== +#define PWM_pol_normal(PIN) \ + ((PIN == P15) ? (PWM_CTRL &= ~bPWM1_POLAR) : \ + ((PIN == P34) ? (PWM_CTRL &= ~bPWM2_POLAR) : \ + ((PIN == P30) ? (PWM_CTRL &= ~bPWM1_POLAR) : \ + ((PIN == P31) ? (PWM_CTRL &= ~bPWM2_POLAR) : \ +(0))))) + +// =================================================================================== +// Set reverse PWM polarity on pin (default high and active low) +// =================================================================================== +#define PWM_pol_reverse(PIN) \ + ((PIN == P15) ? (PWM_CTRL |= bPWM1_POLAR) : \ + ((PIN == P34) ? (PWM_CTRL |= bPWM2_POLAR) : \ + ((PIN == P30) ? (PWM_CTRL |= bPWM1_POLAR) : \ + ((PIN == P31) ? (PWM_CTRL |= bPWM2_POLAR) : \ +(0))))) + +// =================================================================================== +// Set global PWM frequency (in Hertz, range: F_CPU/65536 - F_CPU/256) +// =================================================================================== +#define PWM_set_freq(FREQ) \ + (((FREQ) >= F_CPU / 256) ? (PWM_CK_SE = 0) : \ + (((F_CPU / 256 / (FREQ) - 1) > 255) ? (PWM_CK_SE = 255) : \ + (PWM_CK_SE = (uint8_t)(F_CPU / 256 / (FREQ) - 1)) \ +)) + +// =================================================================================== +// Pin to ADC channel conversion (P11, P14, P15, P32 only) +// =================================================================================== +#define ADC_channel(PIN) \ + ((PIN == P11) ? (0) : \ + ((PIN == P14) ? (1) : \ + ((PIN == P15) ? (2) : \ + ((PIN == P32) ? (3) : \ +(0))))) + +// =================================================================================== +// ADC functions (P11, P14, P15, P32 only) +// =================================================================================== +#define ADC_enable() ADC_CFG |= bADC_EN +#define ADC_disable() ADC_CFG &= ~bADC_EN +#define ADC_fast() ADC_CFG |= bADC_CLK +#define ADC_slow() ADC_CFG &= ~bADC_CLK + +#define ADC_input(PIN) \ + ((PIN == P11) ? (ADC_CHAN1 = 0, ADC_CHAN0 = 0) : \ + ((PIN == P14) ? (ADC_CHAN1 = 0, ADC_CHAN0 = 1) : \ + ((PIN == P15) ? (ADC_CHAN1 = 1, ADC_CHAN0 = 0) : \ + ((PIN == P32) ? (ADC_CHAN1 = 1, ADC_CHAN0 = 1) : \ +(0))))) + +inline uint8_t ADC_read(void) { + ADC_START = 1; + while(ADC_START); + return ADC_DATA; +} + +// =================================================================================== +// Pin to comparator inverting input conversion (P14, P32 only) +// =================================================================================== +#define CMP_channel(PIN) \ + ((PIN == P14) ? (0) : \ + ((PIN == P32) ? (1) : \ +(0))) + +// =================================================================================== +// Comparator functions (positive: P11, P14, P15, P32, negative: P14, P32 only) +// =================================================================================== +#define CMP_enable() ADC_CFG |= bCMP_EN +#define CMP_disable() ADC_CFG &= ~bCMP_EN +#define CMP_read() (CMPO) + +#define CMP_positive(PIN) ADC_input(PIN) +#define CMP_negative(PIN) \ + ((PIN == P14) ? (CMP_CHAN = 0) : \ + ((PIN == P32) ? (CMP_CHAN = 1) : \ +(0))) diff --git a/software/src/system.h b/software/src/system.h new file mode 100644 index 0000000..e2260d5 --- /dev/null +++ b/software/src/system.h @@ -0,0 +1,200 @@ +// =================================================================================== +// Basic System Functions for CH551, CH552 and CH554 * v1.4 * +// =================================================================================== +// +// Functions available: +// -------------------- +// CLK_config() set system clock frequency according to F_CPU +// CLK_external() set external crystal as clock source +// CLK_internal() set internal oscillator as clock source +// +// WDT_start() start watchdog timer with full period +// WDT_stop() stop watchdog timer +// WDT_reset() reload watchdog timer with full period +// WDT_set(time) reload watchdog timer with specified time in ms +// WDT_feed(value) reload watchdog timer with specified value +// +// BOOT_now() enter bootloader +// SLEEP_now() put device into sleep +// RST_now() perform software reset +// +// RST_keep(value) keep this value after RESET +// RST_getKeep() read the keeped value +// RST_wasWDT() check if last RESET was caused by watchdog timer +// RST_wasPIN() check if last RESET was caused by RST PIN +// RST_wasPWR() check if last RESET was caused by power-on +// RST_wasSOFT() check if last RESET was caused by software +// +// WAKE_enable(source) enable wake-up from sleep source (sources see below) +// WAKE_disable(source) disable wake-up from sleep source +// WAKE_all_disable() disable all wake-up sources +// +// WAKE_USB_enable() enable wake-up by USB event +// WAKE_RXD0_enable() enable wake-up by RXD0 low level +// WAKE_RXD1_enable() enable wake-up by RXD1 low level +// WAKE_P13_enable() enable wake-up by pin P1.3 low level +// WAKE_P14_enable() enable wake-up by pin P1.4 low level +// WAKE_P15_enable() enable wake-up by pin P1.5 low level +// WAKE_RST_enable() enable wake-up by pin RST high level +// WAKE_INT_enable() enable wake-up by pin P3.2 edge or pin P3.3 low level +// +// WAKE_USB_disable() disable wake-up by USB event +// WAKE_RXD0_disable() disable wake-up by RXD0 low level +// WAKE_RXD1_disable() disable wake-up by RXD1 low level +// WAKE_P13_disable() disable wake-up by pin P1.3 low level +// WAKE_P14_disable() disable wake-up by pin P1.4 low level +// WAKE_P15_disable() disable wake-up by pin P1.5 low level +// WAKE_RST_disable() disable wake-up by pin RST high level +// WAKE_INT_disable() disable wake-up by pin P3.2 edge or pin P3.3 low level +// +// Wake-up from SLEEP sources: +// --------------------------- +// WAKE_USB wake-up by USB event +// WAKE_RXD0 wake-up by RXD0 low level +// WAKE_RXD1 wake-up by RXD1 low level +// WAKE_P13 wake-up by pin P1.3 low level +// WAKE_P14 wake-up by pin P1.4 low level +// WAKE_P15 wake-up by pin P1.5 low level +// WAKE_RST wake-up by pin RST high level +// WAKE_INT wake-up by pin P3.2 edge or pin P3.3 low level +// +// 2023 by Stefan Wagner: https://github.com/wagiminator + +#pragma once +#include +#include "ch554.h" + +// =================================================================================== +// System Clock +// =================================================================================== +inline void CLK_config(void) { + SAFE_MOD = 0x55; + SAFE_MOD = 0xAA; // enter safe mode + + #if F_CPU == 32000000 + __asm__("orl _CLOCK_CFG, #0b00000111"); // 32MHz + #elif F_CPU == 24000000 + __asm__("anl _CLOCK_CFG, #0b11111000"); + __asm__("orl _CLOCK_CFG, #0b00000110"); // 24MHz + #elif F_CPU == 16000000 + __asm__("anl _CLOCK_CFG, #0b11111000"); + __asm__("orl _CLOCK_CFG, #0b00000101"); // 16MHz + #elif F_CPU == 12000000 + __asm__("anl _CLOCK_CFG, #0b11111000"); + __asm__("orl _CLOCK_CFG, #0b00000100"); // 12MHz + #elif F_CPU == 6000000 + __asm__("anl _CLOCK_CFG, #0b11111000"); + __asm__("orl _CLOCK_CFG, #0b00000011"); // 6MHz + #elif F_CPU == 3000000 + __asm__("anl _CLOCK_CFG, #0b11111000"); + __asm__("orl _CLOCK_CFG, #0b00000010"); // 3MHz + #elif F_CPU == 750000 + __asm__("anl _CLOCK_CFG, #0b11111000"); + __asm__("orl _CLOCK_CFG, #0b00000001"); // 750kHz + #elif F_CPU == 187500 + __asm__("anl _CLOCK_CFG, #0b11111000"); // 187.5kHz + #else + #warning F_CPU invalid or not set + #endif + + SAFE_MOD = 0x00; // terminate safe mode +} + +inline void CLK_external(void) { + SAFE_MOD = 0x55; + SAFE_MOD = 0xAA; // enter safe mode + CLOCK_CFG |= bOSC_EN_XT; // enable external crystal + CLOCK_CFG &= ~bOSC_EN_INT; // turn off internal oscillator + SAFE_MOD = 0x00; // terminate safe mode +} + +inline void CLK_inernal(void) { + SAFE_MOD = 0x55; + SAFE_MOD = 0xAA; // enter safe mode + CLOCK_CFG |= bOSC_EN_INT; // turn on internal oscillator + CLOCK_CFG &= ~bOSC_EN_XT; // disable external crystal + SAFE_MOD = 0x00; // terminate safe mode +} + +// =================================================================================== +// Watchdog Timer +// =================================================================================== +#define WDT_reset() WDOG_COUNT = 0 +#define WDT_feed(value) WDOG_COUNT = value +#define WDT_set(time) WDOG_COUNT = (uint8_t)(256 - ((F_CPU / 1000) * time / 65536)) + +inline void WDT_start(void) { + WDOG_COUNT = 0; + SAFE_MOD = 0x55; + SAFE_MOD = 0xAA; + GLOBAL_CFG |= bWDOG_EN; + SAFE_MOD = 0x00; +} + +inline void WDT_stop(void) { + SAFE_MOD = 0x55; + SAFE_MOD = 0xAA; + GLOBAL_CFG &= ~bWDOG_EN; + SAFE_MOD = 0x00; +} + +// =================================================================================== +// Reset +// =================================================================================== +#define RST_keep(value) RESET_KEEP = value +#define RST_getKeep() (RESET_KEEP) +#define RST_wasWDT() ((PCON & MASK_RST_FLAG) == RST_FLAG_WDOG) +#define RST_wasPIN() ((PCON & MASK_RST_FLAG) == RST_FLAG_PIN) +#define RST_wasPWR() ((PCON & MASK_RST_FLAG) == RST_FLAG_POR) +#define RST_wasSOFT() ((PCON & MASK_RST_FLAG) == RST_FLAG_SW) + +inline void RST_now(void) { + SAFE_MOD = 0x55; + SAFE_MOD = 0xAA; + GLOBAL_CFG |= bSW_RESET; +} + +// =================================================================================== +// Bootloader +// =================================================================================== +inline void BOOT_now(void) { + __asm + lcall #BOOT_LOAD_ADDR + __endasm; +} + +// =================================================================================== +// Sleep +// =================================================================================== +#define SLEEP_now() PCON |= PD + +#define WAKE_USB bWAK_BY_USB // wake-up by USB event +#define WAKE_RXD0 bWAK_RXD0_LO // wake-up by RXD0 low level +#define WAKE_RXD1 bWAK_RXD1_LO // wake-up by RXD1 low level +#define WAKE_P13 bWAK_P1_3_LO // wake-up by pin P1.3 low level +#define WAKE_P14 bWAK_P1_4_LO // wake-up by pin P1.4 low level +#define WAKE_P15 bWAK_P1_5_LO // wake-up by pin P1.5 low level +#define WAKE_RST bWAK_RST_HI // wake-up by pin RST high level +#define WAKE_INT bWAK_P3_2E_3L // wake-up by pin P3.2 (INT0) edge or pin P3.3 (INT1) low level + +#define WAKE_enable(source) WAKE_CTRL |= source +#define WAKE_disable(source) WAKE_CTRL &= ~source +#define WAKE_all_disable() WAKE_CTRL = 0 + +#define WAKE_USB_enable() WAKE_CTRL |= bWAK_BY_USB +#define WAKE_RXD0_enable() WAKE_CTRL |= bWAK_RXD0_LO +#define WAKE_RXD1_enable() WAKE_CTRL |= bWAK_RXD1_LO +#define WAKE_P13_enable() WAKE_CTRL |= bWAK_P1_3_LO +#define WAKE_P14_enable() WAKE_CTRL |= bWAK_P1_4_LO +#define WAKE_P15_enable() WAKE_CTRL |= bWAK_P1_5_LO +#define WAKE_RST_enable() WAKE_CTRL |= bWAK_RST_HI +#define WAKE_INT_enable() WAKE_CTRL |= bWAK_P3_2E_3L + +#define WAKE_USB_disable() WAKE_CTRL &= ~bWAK_BY_USB +#define WAKE_RXD0_disable() WAKE_CTRL &= ~bWAK_RXD0_LO +#define WAKE_RXD1_disable() WAKE_CTRL &= ~bWAK_RXD1_LO +#define WAKE_P13_disable() WAKE_CTRL &= ~bWAK_P1_3_LO +#define WAKE_P14_disable() WAKE_CTRL &= ~bWAK_P1_4_LO +#define WAKE_P15_disable() WAKE_CTRL &= ~bWAK_P1_5_LO +#define WAKE_RST_disable() WAKE_CTRL &= ~bWAK_RST_HI +#define WAKE_INT_disable() WAKE_CTRL &= ~bWAK_P3_2E_3L diff --git a/software/src/uart.c b/software/src/uart.c new file mode 100644 index 0000000..eae5f29 --- /dev/null +++ b/software/src/uart.c @@ -0,0 +1,28 @@ +// =================================================================================== +// UART Functions for CH551, CH552 and CH554 +// =================================================================================== + +#include "uart.h" + +__xdata uint8_t UART_buffer[64]; // UART RX ring buffer +volatile uint8_t UART_readPointer = 0; // UART RX buffer read pointer +volatile uint8_t UART_writePointer = 0; // UART RX buffer write pointer +volatile __bit UART_readyFlag = 1; // UART ready to write flag + +// =================================================================================== +// UART Interrupt Service Routine +// =================================================================================== +#pragma save +#pragma nooverlay +void UART_interrupt(void) { + if(RI) { // RX complete? + UART_buffer[UART_writePointer++] = SBUF; // push received byte to buffer... + UART_writePointer &= 63; // increase ring buffer pointer + RI = 0; // clear RX interrupt flag + } + if(TI) { // TX complete? + UART_readyFlag = 1; // set ready to write flag + TI = 0; // clear TX interrupt flag + } +} +#pragma restore diff --git a/software/src/uart.h b/software/src/uart.h new file mode 100644 index 0000000..d838334 --- /dev/null +++ b/software/src/uart.h @@ -0,0 +1,57 @@ +// =================================================================================== +// UART Functions with Receive Buffer and Interrupt for CH551, CH552 and CH554 +// =================================================================================== + +#pragma once +#include +#include "ch554.h" + +// UART Macros +#define UART_ready() (UART_readyFlag) // ready to send data? +#define UART_available() (UART_readPointer != UART_writePointer) // something in buffer? + +// Define initial BAUD rate +#define UART_BAUD 115200 +#define UART_BAUD_SET (uint8_t)(256 - (((F_CPU / 8 / UART_BAUD) + 1) / 2)) + +// Variables +extern __xdata uint8_t UART_buffer[]; +extern volatile uint8_t UART_readPointer; +extern volatile uint8_t UART_writePointer; +extern volatile __bit UART_readyFlag; + +// Setup UART +inline void UART_init(void) { +//SM0 = 0; // UART0 8 data bits + SM1 = 1; // UART0 BAUD rate by timer +//SM2 = 0; // UART0 no multi-device comm +//RCLK = 0; // UART0 receive clock: TIMER1 +//TCLK = 0; // UART0 transmit clock: TIMER1 + PCON |= SMOD; // UART0 fast BAUD rate + TMOD |= bT1_M1; // TIMER1 8-bit auto-reload + T2MOD |= bTMR_CLK | bT1_CLK; // TIMER1 fast clock selection + TH1 = UART_BAUD_SET; // TIMER1 configure for BAUD rate + TR1 = 1; // TIMER1 start + REN = 1; // enable RX + ES = 1; // enable UART0 interrupt +} + +// Transmit a data byte, return echo +inline void UART_write(uint8_t data) { + UART_readyFlag = 0; // clear ready flag + SBUF = data; // start transmitting data byte +} + +// Receive a data byte +inline uint8_t UART_read(void) { + uint8_t result = UART_buffer[UART_readPointer++]; + UART_readPointer &= 63; + return result; +} + +// Set BAUD rate +inline void UART_setBAUD(uint32_t baud) { + TH1 = (uint8_t)(256 - ((((F_CPU / 8) / baud) + 1) / 2)); +} + +void UART_interrupt(void); diff --git a/software/src/usb.h b/software/src/usb.h new file mode 100755 index 0000000..72d2a7b --- /dev/null +++ b/software/src/usb.h @@ -0,0 +1,332 @@ +// =================================================================================== +// USB constant and structure define +// =================================================================================== + +#pragma once +#include + +// USB PID +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 // reserved PID +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_PRE 0x0C +#endif + +// USB standard device request code +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +// USB hub class request code +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +// USB HID class request code +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +// Bit define for USB request type +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 // control IN, device to host +#define USB_REQ_TYP_OUT 0x00 // control OUT, host to device +#define USB_REQ_TYP_READ 0x80 // control read, device to host +#define USB_REQ_TYP_WRITE 0x00 // control write, host to device +#define USB_REQ_TYP_MASK 0x60 // bit mask of request type +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F // bit mask of request recipient +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#endif + +// USB request type for hub class request +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +// Hub class feature selectors +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +// USB descriptor type +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_IAD 0x0B +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +// USB device class +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMM 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_DATA 0x0A +#define USB_DEV_CLASS_MISC 0xEF +#define USB_DEV_CLASS_VENDOR 0xFF +#endif + +// USB endpoint type and attributes +#ifndef USB_ENDP_TYPE_MASK +#define USB_ENDP_DIR_MASK 0x80 +#define USB_ENDP_ADDR_MASK 0x0F +#define USB_ENDP_TYPE_MASK 0x03 +#define USB_ENDP_TYPE_CTRL 0x00 +#define USB_ENDP_TYPE_ISOCH 0x01 +#define USB_ENDP_TYPE_BULK 0x02 +#define USB_ENDP_TYPE_INTER 0x03 +#define USB_ENDP_ADDR_EP1_OUT 0x01 +#define USB_ENDP_ADDR_EP1_IN 0x81 +#define USB_ENDP_ADDR_EP2_OUT 0x02 +#define USB_ENDP_ADDR_EP2_IN 0x82 +#define USB_ENDP_ADDR_EP3_OUT 0x03 +#define USB_ENDP_ADDR_EP3_IN 0x83 +#define USB_ENDP_ADDR_EP4_OUT 0x04 +#define USB_ENDP_ADDR_EP4_IN 0x84 +#endif + +#ifndef USB_DEVICE_ADDR + #define USB_DEVICE_ADDR 0x02 // default USB device address +#endif +#ifndef DEFAULT_ENDP0_SIZE + #define DEFAULT_ENDP0_SIZE 8 // default maximum packet size for endpoint 0 +#endif +#ifndef DEFAULT_ENDP1_SIZE + #define DEFAULT_ENDP1_SIZE 8 // default maximum packet size for endpoint 1 +#endif +#ifndef MAX_PACKET_SIZE + #define MAX_PACKET_SIZE 64 // maximum packet size +#endif +#ifndef USB_BO_CBW_SIZE + #define USB_BO_CBW_SIZE 0x1F // total length of command block CBW + #define USB_BO_CSW_SIZE 0x0D // total length of command status block CSW +#endif +#ifndef USB_BO_CBW_SIG0 + #define USB_BO_CBW_SIG0 0x55 // command block CBW identification flag 'USBC' + #define USB_BO_CBW_SIG1 0x53 + #define USB_BO_CBW_SIG2 0x42 + #define USB_BO_CBW_SIG3 0x43 + #define USB_BO_CSW_SIG0 0x55 // command status block CSW identification flag 'USBS' + #define USB_BO_CSW_SIG1 0x53 + #define USB_BO_CSW_SIG2 0x42 + #define USB_BO_CSW_SIG3 0x53 +#endif + +// USB descriptor type defines +typedef struct _USB_SETUP_REQ { + uint8_t bRequestType; + uint8_t bRequest; + uint8_t wValueL; + uint8_t wValueH; + uint8_t wIndexL; + uint8_t wIndexH; + uint8_t wLengthL; + uint8_t wLengthH; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; +typedef USB_SETUP_REQ __xdata *PXUSB_SETUP_REQ; + +typedef struct _USB_DEVICE_DESCR { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; +typedef USB_DEV_DESCR __xdata *PXUSB_DEV_DESCR; + +typedef struct _USB_CONFIG_DESCR { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; +typedef USB_CFG_DESCR __xdata *PXUSB_CFG_DESCR; + +typedef struct _USB_INTERF_DESCR { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; +typedef USB_ITF_DESCR __xdata *PXUSB_ITF_DESCR; + +typedef struct _USB_ITF_ASS_DESCR { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} USB_IAD_DESCR, *PUSB_IAD_DESCR; +typedef USB_IAD_DESCR __xdata *PXUSB_IAD_DESCR; + +typedef struct _USB_ENDPOINT_DESCR { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; +typedef USB_ENDP_DESCR __xdata *PXUSB_ENDP_DESCR; + +typedef struct _USB_CONFIG_DESCR_LONG { + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[1]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; +typedef USB_CFG_DESCR_LONG __xdata *PXUSB_CFG_DESCR_LONG; + +typedef struct _USB_HUB_DESCR { + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; +typedef USB_HUB_DESCR __xdata *PXUSB_HUB_DESCR; + +typedef struct _USB_HID_DESCR { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bDescriptorTypeX; + uint16_t wDescriptorLength; +} USB_HID_DESCR, *PUSB_HID_DESCR; +typedef USB_HID_DESCR __xdata *PXUSB_HID_DESCR; + +typedef struct _UDISK_BOC_CBW { // command of BulkOnly USB-FlashDisk + uint8_t mCBW_Sig0; + uint8_t mCBW_Sig1; + uint8_t mCBW_Sig2; + uint8_t mCBW_Sig3; + uint8_t mCBW_Tag0; + uint8_t mCBW_Tag1; + uint8_t mCBW_Tag2; + uint8_t mCBW_Tag3; + uint8_t mCBW_DataLen0; + uint8_t mCBW_DataLen1; + uint8_t mCBW_DataLen2; + uint8_t mCBW_DataLen3; // uppest byte of data length, always is 0 + uint8_t mCBW_Flag; // transfer direction and etc. + uint8_t mCBW_LUN; + uint8_t mCBW_CB_Len; // length of command block + uint8_t mCBW_CB_Buf[16]; // command block buffer +} UDISK_BOC_CBW, *PUDISK_BOC_CBW; +typedef UDISK_BOC_CBW __xdata *PXUDISK_BOC_CBW; + +typedef struct _UDISK_BOC_CSW { // status of BulkOnly USB-FlashDisk + uint8_t mCSW_Sig0; + uint8_t mCSW_Sig1; + uint8_t mCSW_Sig2; + uint8_t mCSW_Sig3; + uint8_t mCSW_Tag0; + uint8_t mCSW_Tag1; + uint8_t mCSW_Tag2; + uint8_t mCSW_Tag3; + uint8_t mCSW_Residue0; // return: remainder bytes + uint8_t mCSW_Residue1; + uint8_t mCSW_Residue2; + uint8_t mCSW_Residue3; // uppest byte of remainder length, always is 0 + uint8_t mCSW_Status; // return: result status +} UDISK_BOC_CSW, *PUDISK_BOC_CSW; +typedef UDISK_BOC_CSW __xdata *PXUDISK_BOC_CSW; diff --git a/software/src/usb_cdc.c b/software/src/usb_cdc.c new file mode 100755 index 0000000..648ea90 --- /dev/null +++ b/software/src/usb_cdc.c @@ -0,0 +1,184 @@ +// =================================================================================== +// USB CDC Functions for CH551, CH552 and CH554 +// =================================================================================== + +#include "uart.h" +#include "gpio.h" +#include "config.h" +#include "usb_cdc.h" +#include "usb_handler.h" + +// =================================================================================== +// Variables and Defines +// =================================================================================== + +// Initialize line coding +__xdata CDC_LINE_CODING_TYPE CDC_lineCodingB = { + .baudrate = 115200, // baudrate 115200 + .stopbits = 0, // 1 stopbit + .parity = 0, // no parity + .databits = 8 // 8 databits +}; + +// Variables +volatile __xdata uint8_t CDC_controlLineState = 0; // control line state +volatile __xdata uint8_t CDC_readByteCount = 0; // number of data bytes in IN buffer +volatile __xdata uint8_t CDC_readPointer = 0; // data pointer for fetching +volatile __bit CDC_writeBusyFlag = 0; // flag of whether upload pointer is busy +__xdata uint8_t CDC_writePointer = 0; // data pointer for writing + +// Macros +#define CDC_DTR_flag (CDC_controlLineState & 1) +#define CDC_RTS_flag ((CDC_controlLineState >> 1) & 1) +#define LED_VCP_SET(val) PIN_write(PIN_LED, !(val)) + +// CDC class requests +#define SET_LINE_CODING 0x20 // host configures line coding +#define GET_LINE_CODING 0x21 // host reads configured line coding +#define SET_CONTROL_LINE_STATE 0x22 // generates RS-232/V.24 style control signals + +// =================================================================================== +// Front End Functions +// =================================================================================== + +// Setup USB-CDC +void CDC_init(void) { +//USB_init(); + UEP2_T_LEN = 0; + UEP3_T_LEN = 0; +} + +// Check number of bytes in the IN buffer +uint8_t CDC_available(void) { + return CDC_readByteCount; +} + +// Check if OUT buffer is ready to be written +__bit CDC_ready(void) { + return(!CDC_writeBusyFlag); +} + +// Flush the OUT buffer +void CDC_flush(void) { + if(!CDC_writeBusyFlag && CDC_writePointer > 0) { // not busy and buffer not empty? + UEP2_T_LEN = CDC_writePointer; // number of bytes in OUT buffer + UEP2_CTRL = UEP2_CTRL & ~MASK_UEP_T_RES | UEP_T_RES_ACK; // respond ACK + CDC_writeBusyFlag = 1; // busy for now + CDC_writePointer = 0; // reset write pointer + } +} + +// Write single character to OUT buffer +void CDC_write(char c) { + while(CDC_writeBusyFlag); // wait for ready to write + EP2_buffer[64 + CDC_writePointer++] = c; // write character + if(CDC_writePointer == EP2_SIZE) CDC_flush(); // flush if buffer full +} + +// Read single character from IN buffer +char CDC_read(void) { + char data; + while(!CDC_readByteCount); // wait for data + data = EP2_buffer[CDC_readPointer++]; // get character + if(--CDC_readByteCount == 0) // dec number of bytes in buffer + UEP2_CTRL = UEP2_CTRL & ~MASK_UEP_R_RES | UEP_R_RES_ACK;// request new data if empty + return data; +} + +// Get DTR flag +__bit CDC_getDTR(void) { + return CDC_DTR_flag; +} + +// Get RTS flag +__bit CDC_getRTS(void) { + return CDC_RTS_flag; +} + +// =================================================================================== +// CDC-Specific USB Handler Functions +// =================================================================================== + +// Setup CDC endpoints +void CDC_setup(void) { + UEP2_DMA = (uint16_t)EP2_buffer; // EP2 data transfer address + UEP3_DMA = (uint16_t)EP3_buffer; // EP3 data transfer address + UEP2_CTRL = bUEP_AUTO_TOG // EP2 Auto flip sync flag + | UEP_T_RES_NAK // EP2 IN transaction returns NAK + | UEP_R_RES_ACK; // EP2 OUT transaction returns ACK + UEP3_CTRL = bUEP_AUTO_TOG // EP3 Auto flip sync flag + | UEP_T_RES_NAK; // EP3 IN transaction returns NAK + UEP2_3_MOD = bUEP2_RX_EN | bUEP2_TX_EN // EP2 double buffer (0x0C) + | bUEP3_TX_EN; // EP3 TX enable (0x40) +} + +// Reset CDC parameters +void CDC_reset(void) { + UEP2_CTRL = bUEP_AUTO_TOG | UEP_T_RES_NAK | UEP_R_RES_ACK; + UEP3_CTRL = bUEP_AUTO_TOG | UEP_T_RES_NAK; + CDC_readByteCount = 0; // reset received bytes counter + CDC_writeBusyFlag = 0; // reset write busy flag +} + +// Handle non-standard control requests +uint8_t CDC_control(void) { + uint8_t i; + if((USB_setupBuf->bRequestType & USB_REQ_TYP_MASK) == USB_REQ_TYP_CLASS) { + switch(USB_setupBuf->bRequest) { + case GET_LINE_CODING: // 0x21 currently configured + for(i=0; ibaudrate); // set UART BAUD rate + UEP0_T_LEN = 0; + UEP0_CTRL |= UEP_R_RES_ACK | UEP_T_RES_ACK; // send 0-length packet + } + } + else { + UEP0_T_LEN = 0; + UEP0_CTRL |= UEP_R_RES_ACK | UEP_T_RES_NAK; // respond Nak + } +} + +// Endpoint 2 IN handler (bulk data transfer to host) +void CDC_EP2_IN(void) { + UEP2_T_LEN = 0; // no data to send anymore + UEP2_CTRL = UEP2_CTRL & ~MASK_UEP_T_RES | UEP_T_RES_NAK; // respond NAK by default + CDC_writeBusyFlag = 0; // clear busy flag +} + +// Endpoint 2 OUT handler (bulk data transfer from host) +void CDC_EP2_OUT(void) { + if(U_TOG_OK) { // discard unsynchronized packets + CDC_readByteCount = USB_RX_LEN; // set number of received data bytes + CDC_readPointer = 0; // reset read pointer for fetching + if(CDC_readByteCount) + UEP2_CTRL = UEP2_CTRL & ~MASK_UEP_R_RES | UEP_R_RES_NAK; // respond NAK after a packet. Let main code change response after handling. + } +} + +// Endpoint 3 IN handler +void CDC_EP3_IN(void) { + UEP3_T_LEN = 0; + UEP3_CTRL = UEP3_CTRL & ~ MASK_UEP_T_RES | UEP_T_RES_NAK; // default NAK +} diff --git a/software/src/usb_cdc.h b/software/src/usb_cdc.h new file mode 100755 index 0000000..10ff62b --- /dev/null +++ b/software/src/usb_cdc.h @@ -0,0 +1,32 @@ +// =================================================================================== +// USB CDC Functions for CH551, CH552 and CH554 +// =================================================================================== + +#pragma once +#include + +// =================================================================================== +// CDC Functions +// =================================================================================== +void CDC_init(void); // setup USB-CDC +void CDC_flush(void); // flush OUT buffer +char CDC_read(void); // read single character from IN buffer +void CDC_write(char c); // write single character to OUT buffer +uint8_t CDC_available(void); // check number of bytes in the IN buffer +__bit CDC_ready(void); // check if OUT buffer is ready to be written +__bit CDC_getDTR(void); // get DTR flag +__bit CDC_getRTS(void); // get RTS flag +#define CDC_writeflush(c) {CDC_write(c);CDC_flush();} + +// =================================================================================== +// CDC Line Coding +// =================================================================================== +typedef struct _CDC_LINE_CODING_TYPE { + uint32_t baudrate; // baud rate + uint8_t stopbits; // number of stopbits (0:1bit,1:1.5bits,2:2bits) + uint8_t parity; // parity (0:none,1:odd,2:even,3:mark,4:space) + uint8_t databits; // number of data bits (5,6,7,8 or 16) +} CDC_LINE_CODING_TYPE, *PCDC_LINE_CODING_TYPE; + +extern __xdata CDC_LINE_CODING_TYPE CDC_lineCodingB; +#define CDC_lineCoding ((PCDC_LINE_CODING_TYPE)CDC_lineCodingB) diff --git a/software/src/usb_descr.c b/software/src/usb_descr.c new file mode 100755 index 0000000..8dda93d --- /dev/null +++ b/software/src/usb_descr.c @@ -0,0 +1,212 @@ +// =================================================================================== +// USB Descriptors +// =================================================================================== + +#include "usb_descr.h" + +// =================================================================================== +// Device Descriptor +// =================================================================================== +__code USB_DEV_DESCR DevDescr = { + .bLength = sizeof(DevDescr), // size of the descriptor in bytes: 18 + .bDescriptorType = USB_DESCR_TYP_DEVICE, // device descriptor: 0x01 + .bcdUSB = 0x0200, // USB specification: USB 2.0 + .bDeviceClass = USB_DEV_CLASS_MISC, // miscellaneous class + .bDeviceSubClass = 2, // unused + .bDeviceProtocol = 1, // unused + .bMaxPacketSize0 = EP0_SIZE, // maximum packet size for Endpoint 0 + .idVendor = USB_VENDOR_ID, // VID + .idProduct = USB_PRODUCT_ID, // PID + .bcdDevice = USB_DEVICE_VERSION, // device version + .iManufacturer = 1, // index of Manufacturer String Descr + .iProduct = 2, // index of Product String Descriptor + .iSerialNumber = 3, // index of Serial Number String Descr + .bNumConfigurations = 1 // number of possible configurations +}; + +// =================================================================================== +// Configuration Descriptor +// =================================================================================== +__code USB_CFG_DESCR_HID CfgDescr = { + + // Configuration Descriptor + .config = { + .bLength = sizeof(USB_CFG_DESCR), // size of the descriptor in bytes + .bDescriptorType = USB_DESCR_TYP_CONFIG, // configuration descriptor: 0x02 + .wTotalLength = sizeof(CfgDescr), // total length in bytes + .bNumInterfaces = 3, // number of interfaces: 3 + .bConfigurationValue= 1, // value to select this configuration + .iConfiguration = 0, // no configuration string descriptor + .bmAttributes = 0x80, // attributes = bus powered, no wakeup + .MaxPower = USB_MAX_POWER_mA / 2 // in 2mA units + }, + + + // Interface Association Descriptor + .association = { + .bLength = sizeof(USB_IAD_DESCR), // size of the descriptor in bytes + .bDescriptorType = USB_DESCR_TYP_IAD, // interf association descr: 0x0B + .bFirstInterface = 0, // first interface + .bInterfaceCount = 2, // total number of interfaces + .bFunctionClass = USB_DEV_CLASS_COMM, // function class: CDC (0x02) + .bFunctionSubClass = 2, // 2: Abstract Control Model (ACM) + .bFunctionProtocol = 1, // 1: AT command protocol + .iFunction = 4 // index of String Descriptor + }, + + // Interface Descriptor: Interface 0 (CDC) + .interface0 = { + .bLength = sizeof(USB_ITF_DESCR), // size of the descriptor in bytes: 9 + .bDescriptorType = USB_DESCR_TYP_INTERF, // interface descriptor: 0x04 + .bInterfaceNumber = 0, // number of this interface: 0 + .bAlternateSetting = 0, // value used to select alternative setting + .bNumEndpoints = 1, // number of endpoints used: 1 + .bInterfaceClass = USB_DEV_CLASS_COMM, // interface class: CDC (0x02) + .bInterfaceSubClass = 2, // 2: Abstract Control Model (ACM) + .bInterfaceProtocol = 1, // 1: AT command protocol + .iInterface = 4 // index of String Descriptor + }, + + // Functional Descriptors for Interface 0 + .functional = { + 0x05,0x24,0x00,0x10,0x01, // header functional descriptor + 0x05,0x24,0x01,0x00,0x01, // call management functional descriptor + 0x04,0x24,0x02,0x02, // direct line management functional descriptor + 0x05,0x24,0x06,0x00,0x01 // union functional descriptor: CDC IF0, Data IF1 + }, + + // Endpoint Descriptor: Endpoint 3 (CDC Upload, Interrupt) + .ep3IN = { + .bLength = sizeof(USB_ENDP_DESCR), // size of the descriptor in bytes: 7 + .bDescriptorType = USB_DESCR_TYP_ENDP, // endpoint descriptor: 0x05 + .bEndpointAddress = USB_ENDP_ADDR_EP3_IN, // endpoint: 3, direction: IN (0x83) + .bmAttributes = USB_ENDP_TYPE_INTER, // transfer type: interrupt (0x03) + .wMaxPacketSize = EP3_SIZE, // max packet size + .bInterval = 1 // polling intervall in ms + }, + + // Interface Descriptor: Interface 1 (Data) + .interface1 = { + .bLength = sizeof(USB_ITF_DESCR), // size of the descriptor in bytes: 9 + .bDescriptorType = USB_DESCR_TYP_INTERF, // interface descriptor: 0x04 + .bInterfaceNumber = 1, // number of this interface: 1 + .bAlternateSetting = 0, // value used to select alternative setting + .bNumEndpoints = 2, // number of endpoints used: 2 + .bInterfaceClass = USB_DEV_CLASS_DATA, // interface class: data (0x0a) + .bInterfaceSubClass = 0, // interface sub class + .bInterfaceProtocol = 0, // interface protocol + .iInterface = 4 // index of String Descriptor + }, + + // Endpoint Descriptor: Endpoint 2 (OUT) + .ep2OUT = { + .bLength = sizeof(USB_ENDP_DESCR), // size of the descriptor in bytes: 7 + .bDescriptorType = USB_DESCR_TYP_ENDP, // endpoint descriptor: 0x05 + .bEndpointAddress = USB_ENDP_ADDR_EP2_OUT, // endpoint: 2, direction: OUT (0x02) + .bmAttributes = USB_ENDP_TYPE_BULK, // transfer type: bulk (0x02) + .wMaxPacketSize = EP2_SIZE, // max packet size + .bInterval = 0 // polling intervall (ignored for bulk) + }, + + // Endpoint Descriptor: Endpoint 2 (IN) + .ep2IN = { + .bLength = sizeof(USB_ENDP_DESCR), // size of the descriptor in bytes: 7 + .bDescriptorType = USB_DESCR_TYP_ENDP, // endpoint descriptor: 0x05 + .bEndpointAddress = USB_ENDP_ADDR_EP2_IN, // endpoint: 2, direction: IN (0x82) + .bmAttributes = USB_ENDP_TYPE_BULK, // transfer type: bulk (0x02) + .wMaxPacketSize = EP2_SIZE, // max packet size + .bInterval = 0 // polling intervall (ignored for bulk) + }, + + // Interface Descriptor: Interface 2 (HID) + .interface2 = { + .bLength = sizeof(USB_ITF_DESCR), // size of the descriptor in bytes: 9 + .bDescriptorType = USB_DESCR_TYP_INTERF, // interface descriptor: 0x04 + .bInterfaceNumber = 2, // number of this interface: 2 + .bAlternateSetting = 0, // value used to select alternative setting + .bNumEndpoints = 2, // number of endpoints used: 2 + .bInterfaceClass = USB_DEV_CLASS_HID, // interface class: HID (0x03) + .bInterfaceSubClass = 0, // no subclass + .bInterfaceProtocol = 0, // no protocoll + .iInterface = 5 // interface string descriptor + }, + + // HID Descriptor + .hid0 = { + .bLength = sizeof(USB_HID_DESCR), // size of the descriptor in bytes: 9 + .bDescriptorType = USB_DESCR_TYP_HID, // HID descriptor: 0x21 + .bcdHID = 0x0110, // HID class spec version (BCD: 1.1) + .bCountryCode = 0, // no country code + .bNumDescriptors = 1, // number of report descriptors: 1 + .bDescriptorTypeX = USB_DESCR_TYP_REPORT, // descriptor type: report + .wDescriptorLength = sizeof(ReportDescr) // report descriptor length + }, + + // Endpoint Descriptor: Endpoint 1 (IN, Interrupt) + .ep1IN = { + .bLength = sizeof(USB_ENDP_DESCR), // size of the descriptor in bytes: 7 + .bDescriptorType = USB_DESCR_TYP_ENDP, // endpoint descriptor: 0x05 + .bEndpointAddress = USB_ENDP_ADDR_EP1_IN, // endpoint: 1, direction: IN (0x81) + .bmAttributes = USB_ENDP_TYPE_INTER, // transfer type: interrupt (0x03) + .wMaxPacketSize = EP1_SIZE, // max packet size + .bInterval = 1 // polling intervall in ms + }, + + // Endpoint Descriptor: Endpoint 1 (OUT, Interrupt) + .ep1OUT = { + .bLength = sizeof(USB_ENDP_DESCR), // size of the descriptor in bytes: 7 + .bDescriptorType = USB_DESCR_TYP_ENDP, // endpoint descriptor: 0x05 + .bEndpointAddress = USB_ENDP_ADDR_EP1_OUT, // endpoint: 2, direction: OUT (0x01) + .bmAttributes = USB_ENDP_TYPE_INTER, // transfer type: interrupt (0x03) + .wMaxPacketSize = EP1_SIZE, // max packet size + .bInterval = 1 // polling intervall in ms + } +}; + +// =================================================================================== +// HID Report Descriptor +// =================================================================================== +__code uint8_t ReportDescr[] ={ + 0x06, 0x00, 0xFF, // Usage Page = 0xFF00 (Vendor Defined Page 1) + 0x09, 0x01, // Usage (Vendor Usage 1) + 0xA1, 0x01, // Collection (Application) + 0x15, 0x00, // Logical minimum value 0 + 0x25, 0xFF, // Logical maximum value 255 + 0x75, 0x08, // Report Size: 8-bit field size + 0x95, 0x40, // Report Count: Make 64 fields + 0x09, 0x01, // Usage (Vendor Usage 1) + 0x81, 0x02, // Input (Data,Var,Abs,No Wrap,Linear) + 0x09, 0x01, // Usage (Vendor Usage 1) + 0x91, 0x02, // Output (Data,Var,Abs,No Wrap,Linear) + 0xC0 // End Collection +}; + +__code uint8_t ReportDescrLen = sizeof(ReportDescr); + +// =================================================================================== +// String Descriptors +// =================================================================================== + +// Language Descriptor (Index 0) +__code uint16_t LangDescr[] = { + ((uint16_t)USB_DESCR_TYP_STRING << 8) | sizeof(LangDescr), 0x0409 }; // US English + +// Manufacturer String Descriptor (Index 1) +__code uint16_t ManufDescr[] = { + ((uint16_t)USB_DESCR_TYP_STRING << 8) | sizeof(ManufDescr), MANUFACTURER_STR }; + +// Product String Descriptor (Index 2) +__code uint16_t ProdDescr[] = { + ((uint16_t)USB_DESCR_TYP_STRING << 8) | sizeof(ProdDescr), PRODUCT_STR }; + +// Serial String Descriptor (Index 3) +__code uint16_t SerDescr[] = { + ((uint16_t)USB_DESCR_TYP_STRING << 8) | sizeof(SerDescr), SERIAL_STR }; + +// Interface String Descriptor (Index 4) +__code uint16_t InterfDescr1[] = { + ((uint16_t)USB_DESCR_TYP_STRING << 8) | sizeof(InterfDescr1), INTERFACE_STR_1 }; + +// Interface String Descriptor (Index 5) +__code uint16_t InterfDescr2[] = { + ((uint16_t)USB_DESCR_TYP_STRING << 8) | sizeof(InterfDescr2), INTERFACE_STR_2 }; diff --git a/software/src/usb_descr.h b/software/src/usb_descr.h new file mode 100755 index 0000000..c616ac7 --- /dev/null +++ b/software/src/usb_descr.h @@ -0,0 +1,92 @@ +// =================================================================================== +// USB Descriptors and Definitions +// =================================================================================== +// +// Definition of USB descriptors and endpoint sizes and addresses. +// +// The following must be defined in config.h: +// USB_VENDOR_ID - Vendor ID (16-bit word) +// USB_PRODUCT_ID - Product ID (16-bit word) +// USB_DEVICE_VERSION - Device version (16-bit BCD) +// USB_MAX_POWER_mA - Device max power in mA +// All string descriptors. + +#pragma once +#include +#include "ch554.h" +#include "usb.h" +#include "config.h" + +// =================================================================================== +// USB Endpoint Definitions +// =================================================================================== +#define EP0_SIZE 64 +#define EP1_SIZE 64 +#define EP2_SIZE 64 +#define EP3_SIZE 64 + +#define EP1_ADDR 0 +#define EP2_ADDR (EP1_ADDR + EP1_BUF_SIZE) +#define EP3_ADDR (EP2_ADDR + EP2_BUF_SIZE) +#define EP0_ADDR (EP3_ADDR + EP3_BUF_SIZE) + +#define EP0_BUF_SIZE EP_BUF_SIZE(EP0_SIZE) +#define EP1_BUF_SIZE EP_BUF_SIZE(EP1_SIZE) + 64 +#define EP2_BUF_SIZE EP_BUF_SIZE(EP2_SIZE) + 64 +#define EP3_BUF_SIZE EP_BUF_SIZE(EP3_SIZE) + +#define EP_BUF_SIZE(x) (x+2<64 ? x+2 : 64) + +__xdata __at (EP0_ADDR) uint8_t EP0_buffer[EP0_BUF_SIZE]; +__xdata __at (EP1_ADDR) uint8_t EP1_buffer[EP1_BUF_SIZE]; +__xdata __at (EP2_ADDR) uint8_t EP2_buffer[EP2_BUF_SIZE]; +__xdata __at (EP3_ADDR) uint8_t EP3_buffer[EP3_BUF_SIZE]; + +// =================================================================================== +// Device and Configuration Descriptors +// =================================================================================== +typedef struct _USB_CFG_DESCR_HID { + USB_CFG_DESCR config; + USB_IAD_DESCR association; + USB_ITF_DESCR interface0; + uint8_t functional[19]; + USB_ENDP_DESCR ep3IN; + USB_ITF_DESCR interface1; + USB_ENDP_DESCR ep2OUT; + USB_ENDP_DESCR ep2IN; + USB_ITF_DESCR interface2; + USB_HID_DESCR hid0; + USB_ENDP_DESCR ep1IN; + USB_ENDP_DESCR ep1OUT; +} USB_CFG_DESCR_HID, *PUSB_CFG_DESCR_HID; +typedef USB_CFG_DESCR_HID __xdata *PXUSB_CFG_DESCR_HID; + +extern __code USB_DEV_DESCR DevDescr; +extern __code USB_CFG_DESCR_HID CfgDescr; + +// =================================================================================== +// HID Report Descriptors +// =================================================================================== +extern __code uint8_t ReportDescr[]; +extern __code uint8_t ReportDescrLen; + +#define USB_REPORT_DESCR ReportDescr +#define USB_REPORT_DESCR_LEN ReportDescrLen + +// =================================================================================== +// String Descriptors +// =================================================================================== +extern __code uint16_t LangDescr[]; +extern __code uint16_t ManufDescr[]; +extern __code uint16_t ProdDescr[]; +extern __code uint16_t SerDescr[]; +extern __code uint16_t InterfDescr1[]; +extern __code uint16_t InterfDescr2[]; + +#define USB_STR_DESCR_i0 (uint8_t*)LangDescr +#define USB_STR_DESCR_i1 (uint8_t*)ManufDescr +#define USB_STR_DESCR_i2 (uint8_t*)ProdDescr +#define USB_STR_DESCR_i3 (uint8_t*)SerDescr +#define USB_STR_DESCR_i4 (uint8_t*)InterfDescr1 +#define USB_STR_DESCR_i5 (uint8_t*)InterfDescr2 +#define USB_STR_DESCR_ix (uint8_t*)SerDescr diff --git a/software/src/usb_handler.c b/software/src/usb_handler.c new file mode 100755 index 0000000..ffc15d0 --- /dev/null +++ b/software/src/usb_handler.c @@ -0,0 +1,465 @@ +// =================================================================================== +// USB Handler for CH551, CH552 and CH554 +// =================================================================================== + +#include "usb_handler.h" + +uint16_t SetupLen; +uint8_t SetupReq, UsbConfig; +__code uint8_t *pDescr; + +// =================================================================================== +// Fast Copy Function +// =================================================================================== +// Copy descriptor *pDescr to Ep0 using double pointer +// (Thanks to Ralph Doncaster) +#pragma callee_saves USB_EP0_copyDescr +void USB_EP0_copyDescr(uint8_t len) { + len; // stop unreferenced argument warning + __asm + push ar7 ; r7 -> stack + mov r7, dpl ; r7 <- len + inc _XBUS_AUX ; select dptr1 + mov dptr, #_EP0_buffer ; dptr1 <- EP0_buffer + dec _XBUS_AUX ; select dptr0 + mov dpl, _pDescr ; dptr0 <- *pDescr + mov dph, (_pDescr + 1) + 01$: + clr a ; acc <- #0 + movc a, @a+dptr ; acc <- *pDescr[dptr0] + inc dptr ; inc dptr0 + .DB 0xA5 ; acc -> EP0_buffer[dptr1] & inc dptr1 + djnz r7, 01$ ; repeat len times + pop ar7 ; r7 <- stack + __endasm; +} + +// =================================================================================== +// Endpoint Handler +// =================================================================================== + +void USB_EP0_SETUP(void) { + uint8_t len = USB_RX_LEN; + if(len == (sizeof(USB_SETUP_REQ))) { + SetupLen = ((uint16_t)USB_setupBuf->wLengthH<<8) | (USB_setupBuf->wLengthL); + len = 0; // default is success and upload 0 length + SetupReq = USB_setupBuf->bRequest; + + if( (USB_setupBuf->bRequestType & USB_REQ_TYP_MASK) != USB_REQ_TYP_STANDARD ) { + #ifdef USB_CTRL_NS_handler + len = USB_CTRL_NS_handler(); // non-standard request + #else + len = 0xff; // command not supported + #endif + } + + else { // standard request + switch(SetupReq) { // request ccfType + case USB_GET_DESCRIPTOR: + switch(USB_setupBuf->wValueH) { + + case USB_DESCR_TYP_DEVICE: // Device Descriptor + pDescr = (uint8_t*)&DevDescr; // put descriptor into out buffer + len = sizeof(DevDescr); // descriptor length + break; + + case USB_DESCR_TYP_CONFIG: // Configuration Descriptor + pDescr = (uint8_t*)&CfgDescr; // put descriptor into out buffer + len = sizeof(CfgDescr); // descriptor length + break; + + case USB_DESCR_TYP_STRING: + switch(USB_setupBuf->wValueL) { // String Descriptor Index + case 0: pDescr = USB_STR_DESCR_i0; break; + case 1: pDescr = USB_STR_DESCR_i1; break; + case 2: pDescr = USB_STR_DESCR_i2; break; + case 3: pDescr = USB_STR_DESCR_i3; break; + #ifdef USB_STR_DESCR_i4 + case 4: pDescr = USB_STR_DESCR_i4; break; + #endif + #ifdef USB_STR_DESCR_i5 + case 5: pDescr = USB_STR_DESCR_i5; break; + #endif + #ifdef USB_STR_DESCR_i6 + case 6: pDescr = USB_STR_DESCR_i6; break; + #endif + #ifdef USB_STR_DESCR_i7 + case 7: pDescr = USB_STR_DESCR_i7; break; + #endif + #ifdef USB_STR_DESCR_i8 + case 8: pDescr = USB_STR_DESCR_i8; break; + #endif + #ifdef USB_STR_DESCR_i9 + case 9: pDescr = USB_STR_DESCR_i9; break; + #endif + default: pDescr = USB_STR_DESCR_ix; break; + } + len = pDescr[0]; // descriptor length + break; + + #ifdef USB_REPORT_DESCR + case USB_DESCR_TYP_REPORT: + if(USB_setupBuf->wValueL == 0) { + pDescr = USB_REPORT_DESCR; + len = USB_REPORT_DESCR_LEN; + } + else len = 0xff; + break; + #endif + + default: + len = 0xff; // unsupported descriptors or error + break; + } + + if(len != 0xff) { + if(SetupLen > len) SetupLen = len; // limit length + len = SetupLen >= EP0_SIZE ? EP0_SIZE : SetupLen; + USB_EP0_copyDescr(len); // copy descriptor to Ep0 + SetupLen -= len; + pDescr += len; + } + break; + + case USB_SET_ADDRESS: + SetupLen = USB_setupBuf->wValueL; // save the assigned address + break; + + case USB_GET_CONFIGURATION: + EP0_buffer[0] = UsbConfig; + if (SetupLen >= 1) len = 1; + break; + + case USB_SET_CONFIGURATION: + UsbConfig = USB_setupBuf->wValueL; + break; + + case USB_GET_INTERFACE: + break; + + case USB_SET_INTERFACE: + break; + + case USB_CLEAR_FEATURE: + if( (USB_setupBuf->bRequestType & 0x1F) == USB_REQ_RECIP_DEVICE ) { + if( ( ( (uint16_t)USB_setupBuf->wValueH << 8 ) | USB_setupBuf->wValueL ) == 0x01 ) { + if( ((uint8_t*)&CfgDescr)[7] & 0x20) { + // wake up + } + else len = 0xFF; // failed + } + else len = 0xFF; // failed + } + else if( (USB_setupBuf->bRequestType & USB_REQ_RECIP_MASK) == USB_REQ_RECIP_ENDP ) { + switch(USB_setupBuf->wIndexL) { + #ifdef EP4_IN_callback + case 0x84: + UEP4_CTRL = UEP4_CTRL & ~ ( bUEP_T_TOG | MASK_UEP_T_RES ) | UEP_T_RES_NAK; + break; + #endif + #ifdef EP4_OUT_callback + case 0x04: + UEP4_CTRL = UEP4_CTRL & ~ ( bUEP_R_TOG | MASK_UEP_R_RES ) | UEP_R_RES_ACK; + break; + #endif + #ifdef EP3_IN_callback + case 0x83: + UEP3_CTRL = UEP3_CTRL & ~ ( bUEP_T_TOG | MASK_UEP_T_RES ) | UEP_T_RES_NAK; + break; + #endif + #ifdef EP3_OUT_callback + case 0x03: + UEP3_CTRL = UEP3_CTRL & ~ ( bUEP_R_TOG | MASK_UEP_R_RES ) | UEP_R_RES_ACK; + break; + #endif + #ifdef EP2_IN_callback + case 0x82: + UEP2_CTRL = UEP2_CTRL & ~ ( bUEP_T_TOG | MASK_UEP_T_RES ) | UEP_T_RES_NAK; + break; + #endif + #ifdef EP2_OUT_callback + case 0x02: + UEP2_CTRL = UEP2_CTRL & ~ ( bUEP_R_TOG | MASK_UEP_R_RES ) | UEP_R_RES_ACK; + break; + #endif + #ifdef EP1_IN_callback + case 0x81: + UEP1_CTRL = UEP1_CTRL & ~ ( bUEP_T_TOG | MASK_UEP_T_RES ) | UEP_T_RES_NAK; + break; + #endif + #ifdef EP1_OUT_callback + case 0x01: + UEP1_CTRL = UEP1_CTRL & ~ ( bUEP_R_TOG | MASK_UEP_R_RES ) | UEP_R_RES_ACK; + break; + #endif + default: + len = 0xFF; // unsupported endpoint + break; + } + } + else len = 0xFF; // unsupported for non-endpoint + break; + + case USB_SET_FEATURE: + if( (USB_setupBuf->bRequestType & 0x1F) == USB_REQ_RECIP_DEVICE ) { + if( ( ( (uint16_t)USB_setupBuf->wValueH << 8 ) | USB_setupBuf->wValueL ) == 0x01 ) { + if( !(((uint8_t*)&CfgDescr)[7] & 0x20) ) len = 0xFF; // failed + } + else len = 0xFF; // failed + } + else if( (USB_setupBuf->bRequestType & 0x1F) == USB_REQ_RECIP_ENDP ) { + if( ( ( (uint16_t)USB_setupBuf->wValueH << 8 ) | USB_setupBuf->wValueL ) == 0x00 ) { + switch( ( (uint16_t)USB_setupBuf->wIndexH << 8 ) | USB_setupBuf->wIndexL ) { + #ifdef EP4_IN_callback + case 0x84: + UEP4_CTRL = UEP4_CTRL & (~bUEP_T_TOG) | UEP_T_RES_STALL;// Set EP4 IN STALL + break; + #endif + #ifdef EP4_OUT_callback + case 0x04: + UEP4_CTRL = UEP4_CTRL & (~bUEP_R_TOG) | UEP_R_RES_STALL;// Set EP4 OUT Stall + break; + #endif + #ifdef EP3_IN_callback + case 0x83: + UEP3_CTRL = UEP3_CTRL & (~bUEP_T_TOG) | UEP_T_RES_STALL;// Set EP3 IN STALL + break; + #endif + #ifdef EP3_OUT_callback + case 0x03: + UEP3_CTRL = UEP3_CTRL & (~bUEP_R_TOG) | UEP_R_RES_STALL;// Set EP3 OUT Stall + break; + #endif + #ifdef EP2_IN_callback + case 0x82: + UEP2_CTRL = UEP2_CTRL & (~bUEP_T_TOG) | UEP_T_RES_STALL;// Set EP2 IN STALL + break; + #endif + #ifdef EP2_OUT_callback + case 0x02: + UEP2_CTRL = UEP2_CTRL & (~bUEP_R_TOG) | UEP_R_RES_STALL;// Set EP2 OUT Stall + break; + #endif + #ifdef EP1_IN_callback + case 0x81: + UEP1_CTRL = UEP1_CTRL & (~bUEP_T_TOG) | UEP_T_RES_STALL;// Set EP1 IN STALL + break; + #endif + #ifdef EP1_OUT_callback + case 0x01: + UEP1_CTRL = UEP1_CTRL & (~bUEP_R_TOG) | UEP_R_RES_STALL;// Set EP1 OUT Stall + break; + #endif + default: + len = 0xFF; // failed + break; + } + } + else len = 0xFF; // failed + } + else len = 0xFF; // failed + break; + + case USB_GET_STATUS: + EP0_buffer[0] = 0x00; + EP0_buffer[1] = 0x00; + if(SetupLen >= 2) len = 2; + else len = SetupLen; + break; + + default: + len = 0xff; // failed + break; + } + } + } + else len = 0xff; // wrong packet length + + if(len == 0xff) { + SetupReq = 0xFF; + UEP0_CTRL = bUEP_R_TOG | bUEP_T_TOG | UEP_R_RES_STALL | UEP_T_RES_STALL;//STALL + } + else if(len <= EP0_SIZE) { // Tx data to host or send 0-length packet + UEP0_T_LEN = len; + UEP0_CTRL = bUEP_R_TOG | bUEP_T_TOG | UEP_R_RES_ACK | UEP_T_RES_ACK;// Expect DATA1, Answer ACK + } + else { + UEP0_T_LEN = 0; // Tx data to host or send 0-length packet + UEP0_CTRL = bUEP_R_TOG | bUEP_T_TOG | UEP_R_RES_ACK | UEP_T_RES_ACK;// Expect DATA1, Answer ACK + } +} + +void USB_EP0_IN(void) { + uint8_t len; + switch(SetupReq) { + + case USB_GET_DESCRIPTOR: + len = SetupLen >= EP0_SIZE ? EP0_SIZE : SetupLen; + USB_EP0_copyDescr(len); // copy descriptor to Ep0 + SetupLen -= len; + pDescr += len; + UEP0_T_LEN = len; + UEP0_CTRL ^= bUEP_T_TOG; // switch between DATA0 and DATA1 + break; + + case USB_SET_ADDRESS: + USB_DEV_AD = USB_DEV_AD & bUDA_GP_BIT | SetupLen; + UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + break; + + default: + UEP0_T_LEN = 0; // end of transaction + UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + break; + } +} + +void USB_EP0_OUT(void) { + UEP0_T_LEN = 0; + UEP0_CTRL |= UEP_R_RES_ACK | UEP_T_RES_NAK; // respond Nak +} + +// =================================================================================== +// USB Interrupt Service Routine +// =================================================================================== +#pragma save +#pragma nooverlay +void USB_interrupt(void) { // inline not really working in multiple files in SDCC + if(UIF_TRANSFER) { + // Dispatch to service functions + uint8_t callIndex = USB_INT_ST & MASK_UIS_ENDP; + switch (USB_INT_ST & MASK_UIS_TOKEN) { + case UIS_TOKEN_OUT: + switch (callIndex) { + case 0: EP0_OUT_callback(); break; + #ifdef EP1_OUT_callback + case 1: EP1_OUT_callback(); break; + #endif + #ifdef EP2_OUT_callback + case 2: EP2_OUT_callback(); break; + #endif + #ifdef EP3_OUT_callback + case 3: EP3_OUT_callback(); break; + #endif + #ifdef EP4_OUT_callback + case 4: EP4_OUT_callback(); break; + #endif + default: break; + } + break; + case UIS_TOKEN_SOF: + switch (callIndex) { + #ifdef EP0_SOF_callback + case 0: EP0_SOF_callback(); break; + #endif + #ifdef EP1_SOF_callback + case 1: EP1_SOF_callback(); break; + #endif + #ifdef EP2_SOF_callback + case 2: EP2_SOF_callback(); break; + #endif + #ifdef EP3_SOF_callback + case 3: EP3_SOF_callback(); break; + #endif + #ifdef EP4_SOF_callback + case 4: EP4_SOF_callback(); break; + #endif + default: break; + } + break; + case UIS_TOKEN_IN: + switch (callIndex) { + case 0: EP0_IN_callback(); break; + #ifdef EP1_IN_callback + case 1: EP1_IN_callback(); break; + #endif + #ifdef EP2_IN_callback + case 2: EP2_IN_callback(); break; + #endif + #ifdef EP3_IN_callback + case 3: EP3_IN_callback(); break; + #endif + #ifdef EP4_IN_callback + case 4: EP4_IN_callback(); break; + #endif + default: break; + } + break; + case UIS_TOKEN_SETUP: + switch (callIndex) { + case 0: EP0_SETUP_callback(); break; + #ifdef EP1_SETUP_callback + case 1: EP1_SETUP_callback(); break; + #endif + #ifdef EP2_SETUP_callback + case 2: EP2_SETUP_callback(); break; + #endif + #ifdef EP3_SETUP_callback + case 3: EP3_SETUP_callback(); break; + #endif + #ifdef EP4_SETUP_callback + case 4: EP4_SETUP_callback(); break; + #endif + default: break; + } + break; + } + UIF_TRANSFER = 0; // clear interrupt flag + } + + // Device mode USB bus reset + if(UIF_BUS_RST) { + UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK; + + #ifdef USB_RESET_handler + USB_RESET_handler(); // custom reset handler + #endif + + USB_DEV_AD = 0x00; + UIF_SUSPEND = 0; + UIF_TRANSFER = 0; + UIF_BUS_RST = 0; // clear interrupt flag + } + + // USB bus suspend / wake up + if (UIF_SUSPEND) { + UIF_SUSPEND = 0; + if ( !(USB_MIS_ST & bUMS_SUSPEND) ) USB_INT_FG = 0xFF; // clear interrupt flag + } +} +#pragma restore + +// =================================================================================== +// USB Init Function +// =================================================================================== + +void USB_init(void) { + USB_CTRL = bUC_DEV_PU_EN // USB internal pull-up enable + | bUC_INT_BUSY // Return NAK if USB INT flag not clear + | bUC_DMA_EN; // DMA enable + UDEV_CTRL = bUD_PD_DIS // Disable UDP/UDM pulldown resistor + | bUD_PORT_EN; // Enable port, full-speed + + #if F_CPU < 12000000 // Set low-speed mode if SysFreq < 12 MHz + USB_CTRL |= bUC_LOW_SPEED; + UDEV_CTRL |= bUD_LOW_SPEED; + #endif + + UEP0_DMA = (uint16_t)EP0_buffer; // EP0 data transfer address + UEP0_CTRL = UEP_R_RES_ACK // EP0 Manual flip, OUT transaction returns ACK + | UEP_T_RES_NAK; // EP0 IN transaction returns NAK + + #ifdef USB_INIT_handler + USB_INIT_handler(); // Custom EP init handler + #endif + + USB_INT_EN |= bUIE_SUSPEND // Enable device hang interrupt + | bUIE_TRANSFER // Enable USB transfer completion interrupt + | bUIE_BUS_RST; // Enable device mode USB bus reset interrupt + + USB_INT_FG |= 0x1F; // Clear interrupt flag + IE_USB = 1; // Enable USB interrupt + EA = 1; // Enable global interrupts + + UEP0_T_LEN = 0; // Must be zero at start +} diff --git a/software/src/usb_handler.h b/software/src/usb_handler.h new file mode 100755 index 0000000..a86b47f --- /dev/null +++ b/software/src/usb_handler.h @@ -0,0 +1,52 @@ +// =================================================================================== +// USB Handler for CH551, CH552 and CH554 +// =================================================================================== + +#pragma once +#include +#include "usb_descr.h" + +// =================================================================================== +// Variables +// =================================================================================== +#define USB_setupBuf ((PUSB_SETUP_REQ)EP0_buffer) +extern uint8_t SetupReq; + +// =================================================================================== +// Custom External USB Handler Functions +// =================================================================================== +uint8_t CDC_control(void); +void HID_setup(void); +void HID_reset(void); +void CDC_setup(void); +void CDC_reset(void); +void CDC_EP0_OUT(void); +void HID_EP1_IN(void); +void HID_EP1_OUT(void); +void CDC_EP2_IN(void); +void CDC_EP2_OUT(void); +void CDC_EP3_IN(void); + +// =================================================================================== +// USB Handler Defines +// =================================================================================== +// Custom USB handler functions +#define USB_INIT_handler() {HID_setup(); CDC_setup();} // init custom endpoints +#define USB_RESET_handler() {HID_reset(); CDC_reset();} // custom USB reset handler +#define USB_CTRL_NS_handler CDC_control // handle custom non-standard requests + +// Endpoint callback functions +#define EP0_SETUP_callback USB_EP0_SETUP +#define EP0_IN_callback USB_EP0_IN +#define EP0_OUT_callback CDC_EP0_OUT +#define EP1_IN_callback HID_EP1_IN +#define EP1_OUT_callback HID_EP1_OUT +#define EP2_IN_callback CDC_EP2_IN +#define EP2_OUT_callback CDC_EP2_OUT +#define EP3_IN_callback CDC_EP3_IN + +// =================================================================================== +// Functions +// =================================================================================== +void USB_interrupt(void); +void USB_init(void); diff --git a/software/src/usb_hid.c b/software/src/usb_hid.c new file mode 100644 index 0000000..d075565 --- /dev/null +++ b/software/src/usb_hid.c @@ -0,0 +1,61 @@ +// =================================================================================== +// USB HID Functions for CH551, CH552 and CH554 +// =================================================================================== + +#include "ch554.h" +#include "usb.h" +#include "usb_hid.h" +#include "usb_descr.h" +#include "usb_handler.h" + +// =================================================================================== +// Variables and Defines +// =================================================================================== + +volatile __xdata uint8_t HID_byteCount = 0; // received bytes in endpoint + +// =================================================================================== +// Front End Functions +// =================================================================================== + +// Setup USB HID +void HID_init(void) { + USB_init(); + UEP1_T_LEN = 0; +} + +// =================================================================================== +// HID-Specific USB Handler Functions +// =================================================================================== + +// Setup HID endpoints +void HID_setup(void) { + UEP1_DMA = (uint16_t)EP1_buffer; // EP1 data transfer address + UEP1_CTRL = bUEP_AUTO_TOG // EP1 Auto flip sync flag + | UEP_T_RES_NAK // EP1 IN transaction returns NAK + | UEP_R_RES_ACK; // EP1 OUT transaction returns ACK + UEP4_1_MOD = bUEP1_TX_EN // EP1 TX enable + | bUEP1_RX_EN; // EP1 RX_enable +} + +// Reset HID parameters +void HID_reset(void) { + UEP1_CTRL = bUEP_AUTO_TOG | UEP_T_RES_NAK | UEP_R_RES_ACK; + HID_byteCount = 0; +} + +// Endpoint 1 IN handler (HID report transfer to host) +void HID_EP1_IN(void) { + UEP1_T_LEN = 0; // no data to send anymore + UEP1_CTRL = UEP1_CTRL & ~MASK_UEP_T_RES | UEP_T_RES_NAK; // default NAK +} + +// Endpoint 1 OUT handler (HID report transfer from host) +void HID_EP1_OUT(void) { + if(U_TOG_OK) { // discard unsynchronized packets + HID_byteCount = USB_RX_LEN; + if(HID_byteCount) + // Respond NAK after a packet. Let main code change response after handling. + UEP1_CTRL = UEP1_CTRL & ~MASK_UEP_R_RES | UEP_R_RES_NAK; + } +} diff --git a/software/src/usb_hid.h b/software/src/usb_hid.h new file mode 100644 index 0000000..9cc1b98 --- /dev/null +++ b/software/src/usb_hid.h @@ -0,0 +1,8 @@ +// =================================================================================== +// USB HID Functions for CH551, CH552 and CH554 +// =================================================================================== + +#pragma once +#include + +void HID_init(void); // setup USB-HID diff --git a/software/tools/chprog.py b/software/tools/chprog.py new file mode 100755 index 0000000..9ea36f9 --- /dev/null +++ b/software/tools/chprog.py @@ -0,0 +1,327 @@ +#!/usr/bin/env python3 +# =================================================================================== +# Project: chprog - Programming Tool for CH55x Microcontrollers +# Version: v1.1 +# Year: 2022 +# Author: Stefan Wagner +# Github: https://github.com/wagiminator +# License: MIT License +# =================================================================================== +# +# Description: +# ------------ +# Simple Python tool for flashing CH55x series microcontrollers (CH551, CH552, CH553, +# CH554, CH558 and CH559) with bootloader versions 1.x and 2.xx. +# +# References: +# ----------- +# chprog is based on chflasher and wchprog: +# - https://ATCnetz.de (Aaron Christophel) +# - https://github.com/atc1441/chflasher (Aaron Christophel) +# - https://github.com/juliuswwj/wchprog +# +# Dependencies: +# ------------- +# - pyusb +# +# Operating Instructions: +# ----------------------- +# You need to install pyusb to use chprog. Install it via "pip install pyusb". +# +# On Linux run "sudo apt install python3-pip" and "sudo pip install pyusb". +# Linux users need permission to access the device. Run: +# echo 'SUBSYSTEM=="usb", ATTR{idVendor}=="4348", ATTR{idProduct}=="55e0", MODE="666"' | sudo tee /etc/udev/rules.d/99-ch55x.rules +# Restart udev: sudo service udev restart +# +# On Windows you will need the Zadig tool (https://zadig.akeo.ie/) to install the +# correct driver. Click "Options" and "List All Devices" to select the USB module. +# Then install the libusb-win32 driver. +# +# Connect the CH55x via USB to your PC. The CH55x must be in bootloader mode! +# Run "python3 chprog.py firmware.bin". + + +import usb.core +import usb.util +import sys, struct + + +# =================================================================================== +# Main Function +# =================================================================================== + +def _main(): + if len(sys.argv) != 2: + sys.stderr.write('ERROR: No bin file selected!\n') + sys.exit(1) + + try: + print('Connecting to device ...') + isp = Programmer() + isp.detect() + print('FOUND:', isp.chipname, 'with bootloader v' + isp.bootloader + '.') + print('Erasing chip ...') + isp.erase() + print('Flashing', sys.argv[1], 'to', isp.chipname, '...') + with open(sys.argv[1], 'rb') as f: data = f.read() + isp.flash_data(data) + print('SUCCESS:', len(data), 'bytes written.') + print('Verifying ...') + isp.verify_data(data) + print('SUCCESS:', len(data), 'bytes verified.') + isp.exit() + except Exception as ex: + if str(ex) != '': + sys.stderr.write('ERROR: ' + str(ex) + '!\n') + sys.exit(1) + print('DONE.') + sys.exit(0) + +# =================================================================================== +# Programmer Class +# =================================================================================== + +class Programmer: + def __init__(self): + dev = usb.core.find(idVendor = CH_VID, idProduct = CH_PID) + if dev is None: + sys.stderr.write('ERROR: No CH55x device found!\n') + print('Check if device is in boot mode or check driver.') + raise Exception() + + try: + dev.set_configuration() + except usb.core.USBError as ex: + sys.stderr.write('ERROR: Could not access USB Device!\n') + if str(ex).startswith('[Errno 13]') and platform.system() == 'Linux': + print('Configure udev or execute as root (sudo).') + raise Exception() + + cfg = dev.get_active_configuration() + intf = cfg[(0,0)] + + self.epout = usb.util.find_descriptor(intf, custom_match = lambda e: usb.util.endpoint_direction(e.bEndpointAddress) == usb.util.ENDPOINT_OUT) + self.epin = usb.util.find_descriptor(intf, custom_match = lambda e: usb.util.endpoint_direction(e.bEndpointAddress) == usb.util.ENDPOINT_IN) + assert self.epout is not None + assert self.epin is not None + + self.chipid = 0 + self.chipname = 'CH000' + self.bootloader = '0.0' + self.chipversion = 0 + self.device_erase_size = 8 + self.device_flash_size = 16 + self.code_flash_size = 14336 + + + def detect(self): + identanswer = self.__sendcmd(DETECT_CHIP_CMD_V2) + if len(identanswer) == 0: + raise Exception('Chip identification failed') + if len(identanswer) == 2: + self.chipversion = 1 + self.__identchipv1() + else: + self.chipversion = 2 + self.__identchipv2() + + self.chipname = 'CH5' + str(self.chipid - 30) + if self.chipid == 0x51 or self.chipid == 0x53: + self.code_flash_size = 10240 + elif self.chipid == 0x58: + self.device_flash_size = 64 + self.device_erase_size = 11 + self.code_flash_size = 32768 + elif self.chipid == 0x59: + self.device_flash_size = 64 + self.device_erase_size = 11 + self.code_flash_size = 61440 + + + def erase(self): + if self.chipversion == 1: + self.__erasev1() + else: + self.__erasev2() + + + def flash_bin(self, filename): + with open(filename, 'rb') as f: data = f.read() + self.flash_data(data) + return len(data) + + def verify_bin(self, filename): + with open(filename, 'rb') as f: data = f.read() + self.verify_data(data) + return len(data) + + def flash_data(self, data): + if len(data) > self.code_flash_size: + raise Exception('Not enough memory') + if self.chipversion == 1: + self.__writev1(data, MODE_WRITE_V1) + else: + self.__writev2(data, MODE_WRITE_V2) + + def verify_data(self, data): + if len(data) > self.code_flash_size: + raise Exception('Not enough memory') + if self.chipversion == 1: + self.__writev1(data, MODE_VERIFY_V1) + else: + self.__writev2(data, MODE_VERIFY_V2) + + + def exit(self): + if self.chipversion == 1: + self.__exitv1() + else: + self.__exitv2() + + + def __sendcmd(self, cmd): + self.epout.write(cmd) + b = self.epin.read(64) + if len(b) == 2: + return struct.unpack('> 4) + '.' + str(cfganswer[0] & 0xf) + else: + raise Exception('Wrong bootloader ID') + + def __identchipv2(self): + identanswer = self.__sendcmd(DETECT_CHIP_CMD_V2) + if len(identanswer) == 6: + self.chipid = identanswer[4] + else: + raise Exception('Wrong chip ID') + + cfganswer = self.__sendcmd((0xa7, 0x02, 0x00, 0x1f, 0x00)) + if len(cfganswer) == 30: + self.bootloader = str(cfganswer[19]) + '.' + str(cfganswer[20]) + str(cfganswer[21]) + outbuffer = bytearray(64) + outbuffer[0] = 0xa3 + outbuffer[1] = 0x30 + outbuffer[2] = 0x00 + checksum = cfganswer[22] + checksum += cfganswer[23] + checksum += cfganswer[24] + checksum += cfganswer[25] + for x in range(0x30): + outbuffer[x+3] = checksum & 0xff + self.__sendcmd(outbuffer) + else: + raise Exception('Wrong bootloader ID') + + + def __erasev1(self): + self.__sendcmd((0xa6, 0x04, 0x00, 0x00, 0x00, 0x00)) + for x in range(self.device_flash_size): + buffer = __sendcmd((0xa9, 0x02, 0x00, x * 4)) + if buffer[0] != 0x00: + raise Exception('Erase failed') + + def __erasev2(self): + buffer = self.__sendcmd((0xa4, 0x01, 0x00, self.device_erase_size)) + if buffer[4] != 0x00: + raise Exception('Erase failed') + + + def __exitv1(self): + self.epout.write((0xa5, 0x02, 0x01, 0x00)) + + def __exitv2(self): + self.epout.write((0xa2, 0x01, 0x00, 0x01)) + + + def __writev1(self, data, mode): + rest = len(data) + curr_addr = 0 + pkt_length = 0 + outbuffer = bytearray(64) + outbuffer[0] = mode + while curr_addr < len(data): + if rest >= 0x3c: + pkt_length = 0x3c + else: + pkt_length = rest + outbuffer[1] = pkt_length + outbuffer[2] = (curr_addr & 0xff) + outbuffer[3] = ((curr_addr >> 8) & 0xff) + for x in range(pkt_length): + outbuffer[x + 4] = data[curr_addr + x] + buffer = self.__sendcmd(outbuffer) + curr_addr += pkt_length + rest -= pkt_length + if buffer is not None: + if buffer[0] != 0x00: + if mode == MODE_WRITE_V1: + raise Exception('Write failed') + elif mode == MODE_VERIFY_V1: + raise Exception('Verify failed') + return len(data) + + def __writev2(self, data, mode): + rest = len(data) + curr_addr = 0 + pkt_length = 0 + outbuffer = bytearray(64) + outbuffer[0] = mode + outbuffer[2] = 0x00 + outbuffer[5] = 0x00 + outbuffer[6] = 0x00 + while curr_addr < len(data): + if rest >= 0x38: + pkt_length = 0x38 + else: + pkt_length = rest + outbuffer[1] = (pkt_length+5) + outbuffer[3] = (curr_addr & 0xff) + outbuffer[4] = ((curr_addr >> 8) & 0xff) + outbuffer[7] = rest & 0xff + for x in range(pkt_length): + outbuffer[x + 8] = data[curr_addr + x] + for x in range(pkt_length + 8): + if x % 8 == 7: + outbuffer[x] ^= self.chipid + buffer = self.__sendcmd(outbuffer) + curr_addr += pkt_length + rest -= pkt_length + if buffer is not None: + if buffer[4] != 0x00 and buffer[4] != 0xfe and buffer[4] != 0xf5: + if mode == MODE_WRITE_V2: + raise Exception('Write failed') + elif mode == MODE_VERIFY_V2: + raise Exception('Verify failed') + + +# =================================================================================== +# CH55x Protocol Constants +# =================================================================================== + +CH_VID = 0x4348 +CH_PID = 0x55e0 + +MODE_WRITE_V1 = 0xa8 +MODE_VERIFY_V1 = 0xa7 +MODE_WRITE_V2 = 0xa5 +MODE_VERIFY_V2 = 0xa6 + +DETECT_CHIP_CMD_V1 = (0xa2, 0x13, 0x55, 0x53, 0x42, 0x20, 0x44, 0x42, 0x47, 0x20, 0x43, 0x48, 0x35, 0x35, 0x39, 0x20, 0x26, 0x20, 0x49, 0x53, 0x50, 0x00) +DETECT_CHIP_CMD_V2 = (0xa1, 0x12, 0x00, 0x52, 0x11, 0x4d, 0x43, 0x55, 0x20, 0x49, 0x53, 0x50, 0x20, 0x26, 0x20, 0x57, 0x43, 0x48, 0x2e, 0x43, 0x4e) + +# =================================================================================== + +if __name__ == "__main__": + _main()