Merge branch 'master' into fix_mult

Author: WhiteNinjaZ

doc/src/Images/Overall_view.png

@@ -582,10 +582,12 @@ Grid Layout Example
     Example FPGA grid
 
 
-.. arch:tag:: <interposer_cut dim=x|y loc="int"/>
+.. arch:tag:: <interposer_cut x="int" y="int"/>
 
-    :req_param dim: Dimension or axis of the cut. 'X' or 'x' means a horizontal cut while 'Y' or 'y' means a vertical cut.
-    :req_param loc: Location of the cut. Cuts are done above or to the right of the tiles at coordinate 'loc'. For example a cut with dim=x and loc=0 would cut the vertical wires above tiles in the 0th row. Currently only integer values are supported.
+    :opt_param x: Specifies the x-coordinate of a vertical interposer cut.
+    :opt_param y: Specifies the y-coordinate of a horizontal interposer cut.
+
+    .. note:: Exactly one of the ``x`` or ``y`` attributes must be specified.
 
     .. note:: Interposers are experimental and are currently not supported by VPR and using the related tags will not actually result in any changes to the flow.
     Defines an interposer cut for modelling 2.5D interposer-based architectures. An interposer cut will cut all connections at location 'loc' along the axis 'dim' Leaving the two sides completely unconnected.
@@ -2363,6 +2365,8 @@ Direct Inter-block Connections
 The content within the ``<directlist>`` tag consists of a group of ``<direct>`` tags.
 The ``<direct>`` tag and its contents are described below.
 
+.. note:: ``from_pin`` and ``to_pin`` only support big endian! For example, ``clb.out[8:0]``
+
 .. arch:tag:: <direct name="string" from_pin="string" to_pin="string" x_offset="int" y_offset="int" z_offset="int" switch_name="string" from_side="{left|right|top|bottom}" to_side="{left|right|top|bottom}"/>
 
     :req_param name: is a unique alphanumeric string to name the connection.
@@ -2382,12 +2386,89 @@ The ``<direct>`` tag and its contents are described below.
     The ``from_side`` and ``to_side`` options can usually be left unspecified.
     However they can be used to explicitly control how direct connections to physically equivalent pins (which may appear on multiple sides) are handled.
 
-    **Example:**
-    Consider a carry chain where the ``cout`` of each CLB drives the ``cin`` of the CLB immediately below it, using the delay-less switch one would enter the following:
+**Example: Inter-tile connection**
+Consider a carry chain where the ``cout`` of each CLB drives the ``cin`` of the CLB immediately below it, using the delay-less switch one would enter the following:
 
-    .. code-block:: xml
+.. code-block:: xml
+
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+
+**Example: Inner-tile feedback**
+
+Consider a feedback connection where the ``out`` of each CLB drives the ``in`` of the CLB in the same location, using the connection block switch one would enter the following:
+
+.. code-block:: xml
+
+    <direct name="feedback" from_pin="clb.out" to_pin="clb.in" x_offset="0" y_offset="0" z_offset="0" switch_name="cb_mux"/>
+
+**Example: Cross-sub-tile connection**
+
+In this example, a tile ``cim8_1k`` is defined, under which there are two types of sub-tiles:
+
+- ``mult_8``: the first sub-tile
+- ``memory``: the second, and the third sub-tile
+
+.. code-block:: xml
+
+    <tile name="cim8_1k" height="2" area="396000">
+      <sub_tile name="mult_8" capacity="1">
+        <equivalent_sites>
+          <site pb_type="mult_8" pin_mapping="direct"/>
+        </equivalent_sites>
+        <input name="a" num_pins="8"/>
+        <input name="b" num_pins="8"/>
+        <output name="out" num_pins="16"/>
+        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+          <fc_override port_name="out" fc_type="frac" fc_val="0"/>
+        </fc>
+        <pinlocations pattern="custom">
+          <loc side="left"/>
+          <loc side="top"/>
+          <loc side="right" yoffset="0">mult_8.a[0:2] mult_8.b[0:2] mult_8.out[0:5]</loc>
+          <loc side="right" yoffset="1">mult_8.a[3:5] mult_8.b[3:5] mult_8.out[6:10]</loc>
+          <loc side="bottom">mult_8.a[6:7] mult_8.b[6:7] mult_8.out[11:15]</loc>
+        </pinlocations>
+      </sub_tile>
+      <sub_tile name="memory" capacity="2">
+        <equivalent_sites>
+          <site pb_type="memory"/>
+        </equivalent_sites>
+        <input name="waddr" num_pins="7"/>
+        <input name="raddr" num_pins="7"/>
+        <input name="data_in" num_pins="8"/>
+        <input name="wen" num_pins="1"/>
+        <input name="ren" num_pins="1"/>
+        <output name="data_out" num_pins="8"/>
+        <clock name="clk" num_pins="1"/>
+        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+          <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
+          <fc_override port_name="data_in" fc_type="frac" fc_val="0"/>
+        </fc>
+        <pinlocations pattern="custom">
+          <loc side="left" yoffset="0">memory.clk memory.waddr[0:0] memory.raddr[0:0] memory.data_in[0:0] memory.data_out[0:0]</loc>
+          <loc side="left" yoffset="1">memory.waddr[1:1] memory.raddr[1:1] memory.data_in[1:1] memory.data_out[1:1]</loc>
+          <loc side="top" yoffset="1">memory.waddr[2:2] memory.raddr[2:2] memory.data_in[2:2] memory.data_out[2:2] memory.waddr[3:3] memory.raddr[3:3] memory.data_in[3:3] memory.data_out[3:3]</loc>
+          <loc side="right" yoffset="0">memory.waddr[4:4] memory.raddr[4:4] memory.data_in[4:4] memory.data_out[4:4]</loc>
+          <loc side="right" yoffset="1">memory.waddr[5:5] memory.raddr[5:5] memory.data_in[5:5] memory.data_out[5:5]</loc>
+          <loc side="bottom" yoffset="0">memory.wen memory.waddr[6:6] memory.raddr[6:6] memory.data_in[6:6] memory.data_out[6:6] memory.ren memory.data_in[7:7] memory.data_out[7:7]</loc>
+        </pinlocations>
+      </sub_tile>
+    </tile>
+
+As shown in :numref:`fig_example_subtile_direct_connection`, consider a connection where the ``out`` of a sub tile ``mult_8`` of tile ``cim8_1k`` drives the ``data_in`` of the sub tile ``memory`` of tile ``cim8_1k`` with an offset, using the delayless switch one would enter the following:
+
+.. code-block:: xml
+
+    <direct name="cim_direct0" from_pin="cim8_1k.out[7:0]" to_pin="cim8_1k.data_in[7:0]" x_offset="0" y_offset="0" z_offset="1"/>
+    <direct name="cim_direct1" from_pin="cim8_1k.out[15:8]" to_pin="cim8_1k.data_in[7:0]" x_offset="0" y_offset="0" z_offset="2"/>
+
+.. _fig_example_subtile_direct_connection:
+
+.. figure:: ./example_subtile_direct_connection.png
+   :width: 60%
+   :alt: Example of direct connections across sub-tiles
 
-        <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+   Example of direct connections across sub-tiles
 
 .. _custom_switch_blocks:
 

doc/src/arch/example_subtile_direct_connection.png

@@ -850,7 +850,7 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe
    * ``cost_variance``: Estimates the initial temperature using the variance of cost after a set of trial swaps. The initial temperature is set to a value proportional to the variance.
    * ``equilibrium``: Estimates the initial temperature by trying to predict the equilibrium temperature for the initial placement (i.e. the temperature that would result in no change in cost).
 
-    **Default** ``cost_variance``
+    **Default** ``equilibrium``
 
 .. option:: --init_t <float>
 

doc/src/arch/reference.rst

@@ -308,6 +308,7 @@ Manual Moves
 
 The manual moves feature allows the user to specify the next move in placement. If the move is legal, blocks are swapped and the new move is shown on the architecture. 
 
+.. _fig-misc-tab:
 .. figure:: ../Images/manual_move.png
     :align: center
     :width: 25%
@@ -335,3 +336,15 @@ If the manual move is legal, the cost summary window will display the delta cost
 
 The user can Accept or Reject the manual move based on the values provided. If accepted the block's new location is shown. 
 
+Pause Button
+------------
+
+The pause button allows the user to temporarily stop the program during placement or routing.
+When clicked during the placement stage, the program will pause at the next temperature update.
+When clicked during the routing stage, it will pause at the next router iteration.
+
+The button can be pressed at any time while the program is running. To enable the feature, click the **Pause** button under the **Misc.** tab (see :ref:`fig-misc-tab`).
+Once the program reaches the next temperature update or router iteration after the button is pressed, it will automatically pause.
+
+After the program has paused, clicking **Next Step** allows the user to resume execution from the point where the program was paused.
+This can be continuing from the current temperature in placement or from the current router iteration in routing.

doc/src/vpr/command_line_usage.rst

@@ -9,7 +9,7 @@ How to Cite
 Citations are important in academia, as they ensure contributors receive credit for their efforts.
 Therefore please use the following paper as a general citation whenever you use VTR:
 
-    M. A. Elgammal, A. Mohaghegh, S. G. Shahrouz, F. Mahmoudi, F. Koşar, K. Talaei, J. Fife, D. Khadivi, K. E. Murray, A. Boutros, K.B. Kent, J. Goeders, V. Betz "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration" ACM TRETS, 2025
+    M. A. Elgammal, A. Mohaghegh, S. G. Shahrouz, F. Mahmoudi, F. Koşar, K. Talaei, J. Fife, D. Khadivi, K. E. Murray, A. Boutros, K.B. Kent, J. Goeders, V. Betz "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration" ACM TRETS, Vol. 13, No. 3, Sept. 2025, pp. 1 - 53.
 
 Bibtex:
 
@@ -19,6 +19,10 @@ Bibtex:
       title={VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration},
       author={Elgammal, Mohamed A. and Mohaghegh, Amin and Shahrouz, Soheil G. and Mahmoudi, Fatemehsadat and Kosar, Fahrican and Talaei, Kimia and Fife, Joshua and Khadivi, Daniel and Murray, Kevin and Boutros, Andrew and Kent, Kenneth B. and Goeders, Jeff and Betz, Vaughn},
       journal={ACM Trans. Reconfigurable Technol. Syst.},
+      issue_date = {September 2025},
+      volume = {18},
+      number = {3},
+      numpages = {53},
       year={2025}
     }
 

doc/src/vpr/graphics.rst

@@ -163,11 +163,11 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
         if (annotation.type == E_ANNOT_PIN_TO_PIN_DELAY) {
             //Check that any combinational delays specified match the 'combinational_sinks_ports' in the model
 
-            if (annotation.clock) {
+            if (!annotation.clock.empty()) {
                 //Sequential annotation, check that the clock on the specified port matches the model
 
-                //Annotations always put the pin in the input_pins field
-                VTR_ASSERT(annotation.input_pins);
+                // Annotations always put the pin in the input_pins field
+                VTR_ASSERT(!annotation.input_pins.empty());
                 for (const std::string& input_pin : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
                     InstPort annot_port(input_pin);
                     for (const std::string& clock : vtr::StringToken(annotation.clock).split(" \t\n")) {
@@ -207,15 +207,15 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
                     }
                 }
 
-            } else if (annotation.input_pins && annotation.output_pins) {
-                //Combinational annotation
-                VTR_ASSERT_MSG(!annotation.clock, "Combinational annotations should have no clock");
+            } else if (!annotation.input_pins.empty() && !annotation.output_pins.empty()) {
+                // Combinational annotation
+                VTR_ASSERT_MSG(annotation.clock.empty(), "Combinational annotations should have no clock");
                 for (const std::string& input_pin : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
                     InstPort annot_in(input_pin);
                     for (const std::string& output_pin : vtr::StringToken(annotation.output_pins).split(" \t\n")) {
                         InstPort annot_out(output_pin);
 
-                        //Find the input model port
+                        // Find the input model port
                         const t_model_ports* model_port = nullptr;
                         for (const t_model_ports* port = model.inputs; port != nullptr; port = port->next) {
                             if (port->name == annot_in.port_name()) {
@@ -230,7 +230,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar
                                            annot_in.port_name().c_str(), annot_in.instance_name().c_str());
                         }
 
-                        //Check that the output port is listed in the model's combinational sinks
+                        // Check that the output port is listed in the model's combinational sinks
                         auto b = model_port->combinational_sink_ports.begin();
                         auto e = model_port->combinational_sink_ports.end();
                         auto iter = std::find(b, e, annot_out.port_name());