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alexforencichalexforencich
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fpga/mqnic/fb2CG: Switch fb2CG@KU15P 25G design to use new TDMA BER measurement module
Signed-off-by: Alex Forencich <[email protected]>
1 parent 4b3a9a0 commit e10d54d

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4 files changed

+83
-92
lines changed

4 files changed

+83
-92
lines changed

‎fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
5757
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
5858
SYN_FILES += rtl/common/tx_scheduler_rr.v
5959
SYN_FILES += rtl/common/tdma_scheduler.v
60-
SYN_FILES += rtl/common/tdma_ber.v
61-
SYN_FILES += rtl/common/tdma_ber_ch.v
60+
SYN_FILES += rtl/common/mqnic_tdma_ber.v
6261
SYN_FILES += rtl/common/led_sreg_driver.v
6362
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
6463
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
@@ -143,7 +142,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
143142
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
144143
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
145144
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
146-
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
145+
XDC_FILES += ../../../common/syn/vivado/mqnic_tdma_ber.tcl
147146
XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl
148147

149148
# IP

‎fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,7 @@ SYN_FILES += rtl/common/stats_dma_latency.v
5757
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
5858
SYN_FILES += rtl/common/tx_scheduler_rr.v
5959
SYN_FILES += rtl/common/tdma_scheduler.v
60-
SYN_FILES += rtl/common/tdma_ber.v
61-
SYN_FILES += rtl/common/tdma_ber_ch.v
60+
SYN_FILES += rtl/common/mqnic_tdma_ber.v
6261
SYN_FILES += rtl/common/led_sreg_driver.v
6362
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
6463
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
@@ -143,7 +142,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
143142
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
144143
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
145144
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
146-
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
145+
XDC_FILES += ../../../common/syn/vivado/mqnic_tdma_ber.tcl
147146
XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl
148147

149148
# IP

‎fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -58,8 +58,7 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr_tdma.v
5858
SYN_FILES += rtl/common/tx_scheduler_rr.v
5959
SYN_FILES += rtl/common/tx_scheduler_ctrl_tdma.v
6060
SYN_FILES += rtl/common/tdma_scheduler.v
61-
SYN_FILES += rtl/common/tdma_ber.v
62-
SYN_FILES += rtl/common/tdma_ber_ch.v
61+
SYN_FILES += rtl/common/mqnic_tdma_ber.v
6362
SYN_FILES += rtl/common/led_sreg_driver.v
6463
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
6564
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
@@ -144,7 +143,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
144143
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
145144
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
146145
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
147-
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
146+
XDC_FILES += ../../../common/syn/vivado/mqnic_tdma_ber.tcl
148147
XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl
149148

150149
# IP

‎fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v

Lines changed: 77 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -499,6 +499,7 @@ localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
499499

500500
localparam RB_DRP_QSFP_0_BASE = RB_BASE_ADDR + 16'h70;
501501
localparam RB_DRP_QSFP_1_BASE = RB_DRP_QSFP_0_BASE + 16'h20;
502+
localparam RB_TDMA_BER_BASE = RB_DRP_QSFP_1_BASE + 16'h20;
502503

503504
initial begin
504505
if (PORT_COUNT > 8) begin
@@ -507,27 +508,6 @@ initial begin
507508
end
508509
end
509510

510-
// AXI lite connections
511-
wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr;
512-
wire [2:0] axil_csr_awprot;
513-
wire axil_csr_awvalid;
514-
wire axil_csr_awready;
515-
wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata;
516-
wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb;
517-
wire axil_csr_wvalid;
518-
wire axil_csr_wready;
519-
wire [1:0] axil_csr_bresp;
520-
wire axil_csr_bvalid;
521-
wire axil_csr_bready;
522-
wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr;
523-
wire [2:0] axil_csr_arprot;
524-
wire axil_csr_arvalid;
525-
wire axil_csr_arready;
526-
wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata;
527-
wire [1:0] axil_csr_rresp;
528-
wire axil_csr_rvalid;
529-
wire axil_csr_rready;
530-
531511
// PTP
532512
wire ptp_td_sd;
533513
wire ptp_pps;
@@ -569,6 +549,12 @@ wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_1_drp_reg_rd_data;
569549
wire qsfp_1_drp_reg_rd_wait;
570550
wire qsfp_1_drp_reg_rd_ack;
571551

552+
wire tdma_ber_reg_wr_wait;
553+
wire tdma_ber_reg_wr_ack;
554+
wire [AXIL_CTRL_DATA_WIDTH-1:0] tdma_ber_reg_rd_data;
555+
wire tdma_ber_reg_rd_wait;
556+
wire tdma_ber_reg_rd_ack;
557+
572558
reg ctrl_reg_wr_ack_reg = 1'b0;
573559
reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}};
574560
reg ctrl_reg_rd_ack_reg = 1'b0;
@@ -599,11 +585,11 @@ wire bmc_status_idle;
599585
wire bmc_status_done;
600586
wire bmc_status_timeout;
601587

602-
assign ctrl_reg_wr_wait = qsfp_0_drp_reg_wr_wait | qsfp_1_drp_reg_wr_wait;
603-
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp_0_drp_reg_wr_ack | qsfp_1_drp_reg_wr_ack;
604-
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_0_drp_reg_rd_data | qsfp_1_drp_reg_rd_data;
605-
assign ctrl_reg_rd_wait = qsfp_0_drp_reg_rd_wait | qsfp_1_drp_reg_rd_wait;
606-
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp_0_drp_reg_rd_ack | qsfp_1_drp_reg_rd_ack;
588+
assign ctrl_reg_wr_wait = qsfp_0_drp_reg_wr_wait | qsfp_1_drp_reg_wr_wait | tdma_ber_reg_wr_wait;
589+
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp_0_drp_reg_wr_ack | qsfp_1_drp_reg_wr_ack | tdma_ber_reg_wr_ack;
590+
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_0_drp_reg_rd_data | qsfp_1_drp_reg_rd_data | tdma_ber_reg_rd_data;
591+
assign ctrl_reg_rd_wait = qsfp_0_drp_reg_rd_wait | qsfp_1_drp_reg_rd_wait | tdma_ber_reg_rd_wait;
592+
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp_0_drp_reg_rd_ack | qsfp_1_drp_reg_rd_ack | tdma_ber_reg_rd_ack;
607593

608594
assign qsfp_0_reset_n = !qsfp_0_reset_reg;
609595
assign qsfp_0_lp_mode = qsfp_0_lp_mode_reg;
@@ -878,7 +864,7 @@ rb_drp #(
878864
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
879865
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
880866
.RB_BASE_ADDR(RB_DRP_QSFP_1_BASE),
881-
.RB_NEXT_PTR(0)
867+
.RB_NEXT_PTR(RB_TDMA_BER_BASE)
882868
)
883869
qsfp_1_rb_drp_inst (
884870
.clk(clk_250mhz),
@@ -920,55 +906,63 @@ generate
920906
if (TDMA_BER_ENABLE) begin
921907

922908
// BER tester
923-
tdma_ber #(
909+
mqnic_tdma_ber #(
924910
.COUNT(8),
925-
.INDEX_WIDTH(6),
926-
.SLICE_WIDTH(5),
927-
.AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
928-
.AXIL_ADDR_WIDTH(8+6+$clog2(8)),
929-
.AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
930-
.SCHEDULE_START_S(0),
931-
.SCHEDULE_START_NS(0),
932-
.SCHEDULE_PERIOD_S(0),
933-
.SCHEDULE_PERIOD_NS(1000000),
934-
.TIMESLOT_PERIOD_S(0),
935-
.TIMESLOT_PERIOD_NS(100000),
936-
.ACTIVE_PERIOD_S(0),
937-
.ACTIVE_PERIOD_NS(90000)
911+
.TDMA_INDEX_W(TDMA_INDEX_WIDTH),
912+
.ERR_BITS(66),
913+
.ERR_CNT_W(7),
914+
.RAM_SIZE(1024),
915+
.PHY_PIPELINE(2),
916+
917+
.REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
918+
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
919+
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
920+
.RB_BASE_ADDR(RB_TDMA_BER_BASE),
921+
.RB_NEXT_PTR(0)
938922
)
939923
tdma_ber_inst (
940924
.clk(clk_250mhz),
941925
.rst(rst_250mhz),
926+
927+
/*
928+
* Register interface
929+
*/
930+
.ctrl_reg_wr_addr(ctrl_reg_wr_addr),
931+
.ctrl_reg_wr_data(ctrl_reg_wr_data),
932+
.ctrl_reg_wr_strb(ctrl_reg_wr_strb),
933+
.ctrl_reg_wr_en(ctrl_reg_wr_en),
934+
.ctrl_reg_wr_wait(tdma_ber_reg_wr_wait),
935+
.ctrl_reg_wr_ack(tdma_ber_reg_wr_ack),
936+
.ctrl_reg_rd_addr(ctrl_reg_rd_addr),
937+
.ctrl_reg_rd_en(ctrl_reg_rd_en),
938+
.ctrl_reg_rd_data(tdma_ber_reg_rd_data),
939+
.ctrl_reg_rd_wait(tdma_ber_reg_rd_wait),
940+
.ctrl_reg_rd_ack(tdma_ber_reg_rd_ack),
941+
942+
/*
943+
* PTP clock
944+
*/
945+
.ptp_ts_tod(ptp_sync_ts_tod),
946+
.ptp_ts_tod_step(ptp_sync_ts_tod_step),
947+
948+
/*
949+
* PHY connections
950+
*/
942951
.phy_tx_clk({qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}),
943952
.phy_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}),
944953
.phy_rx_error_count({qsfp_1_rx_error_count_3, qsfp_1_rx_error_count_2, qsfp_1_rx_error_count_1, qsfp_1_rx_error_count_0, qsfp_0_rx_error_count_3, qsfp_0_rx_error_count_2, qsfp_0_rx_error_count_1, qsfp_0_rx_error_count_0}),
945954
.phy_cfg_tx_prbs31_enable({qsfp_1_cfg_tx_prbs31_enable_3, qsfp_1_cfg_tx_prbs31_enable_2, qsfp_1_cfg_tx_prbs31_enable_1, qsfp_1_cfg_tx_prbs31_enable_0, qsfp_0_cfg_tx_prbs31_enable_3, qsfp_0_cfg_tx_prbs31_enable_2, qsfp_0_cfg_tx_prbs31_enable_1, qsfp_0_cfg_tx_prbs31_enable_0}),
946-
.phy_cfg_rx_prbs31_enable({qsfp_1_cfg_rx_prbs31_enable_3, qsfp_1_cfg_rx_prbs31_enable_2, qsfp_1_cfg_rx_prbs31_enable_1, qsfp_1_cfg_rx_prbs31_enable_0, qsfp_0_cfg_rx_prbs31_enable_3, qsfp_0_cfg_rx_prbs31_enable_2, qsfp_0_cfg_rx_prbs31_enable_1, qsfp_0_cfg_rx_prbs31_enable_0}),
947-
.s_axil_awaddr(axil_csr_awaddr),
948-
.s_axil_awprot(axil_csr_awprot),
949-
.s_axil_awvalid(axil_csr_awvalid),
950-
.s_axil_awready(axil_csr_awready),
951-
.s_axil_wdata(axil_csr_wdata),
952-
.s_axil_wstrb(axil_csr_wstrb),
953-
.s_axil_wvalid(axil_csr_wvalid),
954-
.s_axil_wready(axil_csr_wready),
955-
.s_axil_bresp(axil_csr_bresp),
956-
.s_axil_bvalid(axil_csr_bvalid),
957-
.s_axil_bready(axil_csr_bready),
958-
.s_axil_araddr(axil_csr_araddr),
959-
.s_axil_arprot(axil_csr_arprot),
960-
.s_axil_arvalid(axil_csr_arvalid),
961-
.s_axil_arready(axil_csr_arready),
962-
.s_axil_rdata(axil_csr_rdata),
963-
.s_axil_rresp(axil_csr_rresp),
964-
.s_axil_rvalid(axil_csr_rvalid),
965-
.s_axil_rready(axil_csr_rready),
966-
.ptp_ts_96(ptp_sync_ts_tod),
967-
.ptp_ts_step(ptp_sync_ts_tod_step)
955+
.phy_cfg_rx_prbs31_enable({qsfp_1_cfg_rx_prbs31_enable_3, qsfp_1_cfg_rx_prbs31_enable_2, qsfp_1_cfg_rx_prbs31_enable_1, qsfp_1_cfg_rx_prbs31_enable_0, qsfp_0_cfg_rx_prbs31_enable_3, qsfp_0_cfg_rx_prbs31_enable_2, qsfp_0_cfg_rx_prbs31_enable_1, qsfp_0_cfg_rx_prbs31_enable_0})
968956
);
969957

970958
end else begin
971959

960+
assign tdma_ber_reg_wr_wait = 0;
961+
assign tdma_ber_reg_wr_ack = 0;
962+
assign tdma_ber_reg_rd_data = 0;
963+
assign tdma_ber_reg_rd_wait = 0;
964+
assign tdma_ber_reg_rd_ack = 0;
965+
972966
assign qsfp_0_cfg_tx_prbs31_enable_0 = 1'b0;
973967
assign qsfp_0_cfg_rx_prbs31_enable_0 = 1'b0;
974968
assign qsfp_0_cfg_tx_prbs31_enable_1 = 1'b0;
@@ -1403,7 +1397,7 @@ mqnic_core_pcie_us #(
14031397
.AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
14041398
.AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH),
14051399
.AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
1406-
.AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE),
1400+
.AXIL_CSR_PASSTHROUGH_ENABLE(0),
14071401
.RB_NEXT_PTR(RB_BASE_ADDR),
14081402

14091403
// AXI lite interface configuration (application control)
@@ -1537,25 +1531,25 @@ core_inst (
15371531
/*
15381532
* AXI-Lite master interface (passthrough for NIC control and status)
15391533
*/
1540-
.m_axil_csr_awaddr(axil_csr_awaddr),
1541-
.m_axil_csr_awprot(axil_csr_awprot),
1542-
.m_axil_csr_awvalid(axil_csr_awvalid),
1543-
.m_axil_csr_awready(axil_csr_awready),
1544-
.m_axil_csr_wdata(axil_csr_wdata),
1545-
.m_axil_csr_wstrb(axil_csr_wstrb),
1546-
.m_axil_csr_wvalid(axil_csr_wvalid),
1547-
.m_axil_csr_wready(axil_csr_wready),
1548-
.m_axil_csr_bresp(axil_csr_bresp),
1549-
.m_axil_csr_bvalid(axil_csr_bvalid),
1550-
.m_axil_csr_bready(axil_csr_bready),
1551-
.m_axil_csr_araddr(axil_csr_araddr),
1552-
.m_axil_csr_arprot(axil_csr_arprot),
1553-
.m_axil_csr_arvalid(axil_csr_arvalid),
1554-
.m_axil_csr_arready(axil_csr_arready),
1555-
.m_axil_csr_rdata(axil_csr_rdata),
1556-
.m_axil_csr_rresp(axil_csr_rresp),
1557-
.m_axil_csr_rvalid(axil_csr_rvalid),
1558-
.m_axil_csr_rready(axil_csr_rready),
1534+
.m_axil_csr_awaddr(),
1535+
.m_axil_csr_awprot(),
1536+
.m_axil_csr_awvalid(),
1537+
.m_axil_csr_awready(1),
1538+
.m_axil_csr_wdata(),
1539+
.m_axil_csr_wstrb(),
1540+
.m_axil_csr_wvalid(),
1541+
.m_axil_csr_wready(1),
1542+
.m_axil_csr_bresp(0),
1543+
.m_axil_csr_bvalid(0),
1544+
.m_axil_csr_bready(),
1545+
.m_axil_csr_araddr(),
1546+
.m_axil_csr_arprot(),
1547+
.m_axil_csr_arvalid(),
1548+
.m_axil_csr_arready(1),
1549+
.m_axil_csr_rdata(0),
1550+
.m_axil_csr_rresp(0),
1551+
.m_axil_csr_rvalid(0),
1552+
.m_axil_csr_rready(),
15591553

15601554
/*
15611555
* Control register interface

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