From d9c39c2934b75b9a849a4d89d77b1942b6744ccc Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 7 Nov 2023 17:02:00 -0800 Subject: [PATCH] Use new PTP time distribution subsystem Signed-off-by: Alex Forencich --- docs/source/rb/index.rst | 2 +- docs/source/rb/phc.rst | 171 ++++-- docs/source/rb/phc_perout.rst | 4 +- .../dma_bench/rtl/mqnic_app_block_dma_bench.v | 11 +- .../dma_bench/tb/mqnic_core_pcie_us/Makefile | 4 +- .../test_mqnic_core_pcie_us.py | 8 +- fpga/app/template/rtl/mqnic_app_block.v | 11 +- .../template/tb/mqnic_core_pcie_us/Makefile | 4 +- .../test_mqnic_core_pcie_us.py | 8 +- fpga/common/rtl/mqnic_core.v | 168 ++++-- fpga/common/rtl/mqnic_core_axi.v | 38 +- fpga/common/rtl/mqnic_core_pcie.v | 38 +- fpga/common/rtl/mqnic_core_pcie_ptile.v | 38 +- fpga/common/rtl/mqnic_core_pcie_s10.v | 38 +- fpga/common/rtl/mqnic_core_pcie_us.v | 38 +- fpga/common/rtl/mqnic_interface.v | 8 +- fpga/common/rtl/mqnic_ptp.v | 30 +- fpga/common/rtl/mqnic_ptp_clock.v | 561 ++++++++++++------ fpga/common/syn/vivado/mqnic_ptp_clock.tcl | 52 +- fpga/common/tb/mqnic.py | 54 +- fpga/common/tb/mqnic_core_axi/Makefile | 4 +- .../tb/mqnic_core_axi/test_mqnic_core_axi.py | 8 +- fpga/common/tb/mqnic_core_pcie_ptile/Makefile | 4 +- .../test_mqnic_core_pcie_ptile.py | 8 +- fpga/common/tb/mqnic_core_pcie_s10/Makefile | 4 +- .../test_mqnic_core_pcie_s10.py | 8 +- fpga/common/tb/mqnic_core_pcie_us/Makefile | 4 +- .../test_mqnic_core_pcie_us.py | 8 +- .../tb/mqnic_core_pcie_us_tdma/Makefile | 4 +- .../test_mqnic_core_pcie_us.py | 8 +- fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile | 6 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v | 52 +- .../250_SoC/fpga_100g/tb/fpga_core/Makefile | 4 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile | 6 +- fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile | 6 +- fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v | 52 +- .../250_SoC/fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile | 4 +- fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile | 4 +- fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v | 48 +- .../520N_MX/fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- .../ADM_PCIE_9V3/fpga_100g/fpga/Makefile | 6 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 6 +- .../ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile | 6 +- .../ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v | 52 +- .../fpga_100g/tb/fpga_core/Makefile | 4 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +- .../mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile | 6 +- .../ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile | 6 +- .../ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile | 6 +- .../ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 52 +- .../fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- .../mqnic/AU200/fpga_100g/fpga_AU200/Makefile | 6 +- .../fpga_AU200_app_dma_bench/Makefile | 6 +- .../mqnic/AU200/fpga_100g/fpga_AU250/Makefile | 6 +- .../fpga_AU250_app_dma_bench/Makefile | 6 +- .../AU200/fpga_100g/fpga_VCU1525/Makefile | 6 +- .../fpga_VCU1525_app_dma_bench/Makefile | 6 +- fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v | 52 +- .../AU200/fpga_100g/tb/fpga_core/Makefile | 4 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/AU200/fpga_25g/fpga_AU200/Makefile | 6 +- .../AU200/fpga_25g/fpga_AU200_10g/Makefile | 6 +- fpga/mqnic/AU200/fpga_25g/fpga_AU250/Makefile | 6 +- .../AU200/fpga_25g/fpga_AU250_10g/Makefile | 6 +- .../AU200/fpga_25g/fpga_VCU1525/Makefile | 6 +- .../AU200/fpga_25g/fpga_VCU1525_10g/Makefile | 6 +- fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v | 52 +- .../AU200/fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/AU280/fpga_100g/fpga/Makefile | 6 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v | 52 +- .../AU280/fpga_100g/tb/fpga_core/Makefile | 4 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/AU280/fpga_25g/fpga/Makefile | 6 +- fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile | 6 +- fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v | 52 +- .../AU280/fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/AU50/fpga_100g/fpga/Makefile | 6 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v | 52 +- .../AU50/fpga_100g/tb/fpga_core/Makefile | 4 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/AU50/fpga_25g/fpga/Makefile | 6 +- fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile | 6 +- fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v | 52 +- .../mqnic/AU50/fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- .../mqnic/DE10_Agilex/fpga_100g/fpga/Makefile | 4 +- .../DE10_Agilex/fpga_100g/fpga_24AR0/Makefile | 4 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 4 +- .../fpga_app_dma_bench_24AR0/Makefile | 4 +- .../DE10_Agilex/fpga_100g/rtl/fpga_core.v | 52 +- .../fpga_100g/tb/fpga_core/Makefile | 4 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/DE10_Agilex/fpga_25g/fpga/Makefile | 4 +- .../DE10_Agilex/fpga_25g/fpga_10g/Makefile | 4 +- .../fpga_25g/fpga_10g_24AR0/Makefile | 4 +- .../DE10_Agilex/fpga_25g/fpga_24AR0/Makefile | 4 +- .../DE10_Agilex/fpga_25g/rtl/fpga_core.v | 52 +- .../fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- .../DK_DEV_1SDX_P_A/fpga_100g/fpga/Makefile | 4 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 4 +- .../DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v | 52 +- .../fpga_100g/tb/fpga_core/Makefile | 4 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +- .../DK_DEV_1SDX_P_A/fpga_25g/fpga/Makefile | 4 +- .../fpga_25g/fpga_10g/Makefile | 4 +- .../DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v | 52 +- .../fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- .../fpga_25g/fpga_10g_1sm21b/Makefile | 4 +- .../fpga_25g/fpga_10g_1sm21c/Makefile | 4 +- .../fpga_25g/fpga_1sm21b/Makefile | 4 +- .../fpga_25g/fpga_1sm21c/Makefile | 4 +- .../DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v | 52 +- .../fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- .../DK_DEV_AGF014EA/fpga_100g/fpga/Makefile | 4 +- .../fpga_100g/fpga_24AR0/Makefile | 4 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 4 +- .../fpga_app_dma_bench_24AR0/Makefile | 4 +- .../DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v | 52 +- .../fpga_100g/tb/fpga_core/Makefile | 4 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +- .../DK_DEV_AGF014EA/fpga_25g/fpga/Makefile | 4 +- .../fpga_25g/fpga_10g/Makefile | 4 +- .../fpga_25g/fpga_10g_24AR0/Makefile | 4 +- .../fpga_25g/fpga_24AR0/Makefile | 4 +- .../DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v | 52 +- .../fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- .../fpga/fpga_app_dma_bench_ku040/Makefile | 6 +- .../fpga/fpga_app_dma_bench_ku060/Makefile | 6 +- .../fpga/fpga_ku040/Makefile | 6 +- .../fpga/fpga_ku060/Makefile | 6 +- .../fpga/rtl/fpga_core.v | 52 +- .../fpga/tb/fpga_core/Makefile | 4 +- .../fpga/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/KR260/fpga/fpga/Makefile | 6 +- .../KR260/fpga/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/KR260/fpga/rtl/fpga_core.v | 52 +- fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile | 4 +- .../KR260/fpga/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile | 6 +- .../fpga/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v | 48 +- .../NetFPGA_SUME/fpga/tb/fpga_core/Makefile | 4 +- .../fpga/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile | 6 +- .../fpga/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v | 48 +- .../Nexus_K35_S/fpga/tb/fpga_core/Makefile | 4 +- .../fpga/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile | 6 +- .../Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile | 6 +- .../fpga_25g/fpga_app_dma_bench/Makefile | 6 +- .../Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v | 52 +- .../fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile | 6 +- .../Nexus_K3P_S/fpga_25g/fpga_10g/Makefile | 6 +- .../fpga_25g/fpga_app_dma_bench/Makefile | 6 +- .../Nexus_K3P_S/fpga_25g/rtl/fpga_core.v | 48 +- .../fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/VCU108/fpga_25g/fpga/Makefile | 6 +- fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile | 6 +- .../fpga_25g/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v | 52 +- .../VCU108/fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/VCU118/fpga_100g/fpga/Makefile | 6 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v | 52 +- .../VCU118/fpga_100g/tb/fpga_core/Makefile | 4 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/VCU118/fpga_25g/fpga/Makefile | 6 +- fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile | 6 +- fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v | 52 +- .../VCU118/fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile | 6 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v | 52 +- .../XUPP3R/fpga_100g/tb/fpga_core/Makefile | 4 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile | 6 +- fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile | 6 +- fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v | 52 +- .../XUPP3R/fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/XUSP3S/fpga_25g/fpga/Makefile | 6 +- fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/Makefile | 6 +- .../fpga_25g/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v | 52 +- .../XUSP3S/fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/ZCU102/fpga/fpga/Makefile | 6 +- .../ZCU102/fpga/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v | 52 +- fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile | 4 +- .../fpga/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile | 6 +- .../fpga_pcie/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v | 52 +- .../ZCU106/fpga_pcie/tb/fpga_core/Makefile | 4 +- .../fpga_pcie/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile | 6 +- .../fpga_zynqmp/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v | 52 +- .../ZCU106/fpga_zynqmp/tb/fpga_core/Makefile | 4 +- .../tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile | 6 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 6 +- .../fpga_100g/fpga_app_template/Makefile | 6 +- fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile | 6 +- fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v | 52 +- .../fb2CG/fpga_100g/tb/fpga_core/Makefile | 4 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile | 6 +- fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile | 6 +- fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile | 6 +- fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v | 52 +- .../fb2CG/fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile | 6 +- .../fpga_100g/fpga_app_dma_bench/Makefile | 6 +- fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v | 52 +- .../fb4CGg3/fpga_100g/tb/fpga_core/Makefile | 4 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 4 +- fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile | 6 +- fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile | 6 +- fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v | 52 +- .../fb4CGg3/fpga_25g/tb/fpga_core/Makefile | 4 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 4 +- modules/mqnic/mqnic_hw.h | 54 +- modules/mqnic/mqnic_ptp.c | 33 +- utils/mqnic-config.c | 6 +- utils/mqnic-dump.c | 10 +- 248 files changed, 2419 insertions(+), 1800 deletions(-) diff --git a/docs/source/rb/index.rst b/docs/source/rb/index.rst index 3273f3014..015f89a0a 100644 --- a/docs/source/rb/index.rst +++ b/docs/source/rb/index.rst @@ -78,7 +78,7 @@ The NIC register space is constructed from a linked list of register blocks. Ea 0x0000C040 0x00000100 :ref:`rb_sched_rr` 0x0000C050 0x00000100 :ref:`rb_sched_ctrl_tdma` 0x0000C060 0x00000100 :ref:`rb_tdma_sch` - 0x0000C080 0x00000100 :ref:`rb_phc` + 0x0000C080 0x00000200 :ref:`rb_phc` 0x0000C081 0x00000100 :ref:`rb_phc_perout` 0x0000C090 0x00000200 :ref:`rb_rx_queue_map` 0x0000C100 0x00000100 :ref:`rb_gpio` diff --git a/docs/source/rb/phc.rst b/docs/source/rb/phc.rst index 557cfc213..6db6bbe3b 100644 --- a/docs/source/rb/phc.rst +++ b/docs/source/rb/phc.rst @@ -4,7 +4,7 @@ PTP hardware clock register block ================================= -The PTP hardware clock register block has a header with type 0x0000C080, version 0x00000100, and carries several control registers for the PTP clock. +The PTP hardware clock register block has a header with type 0x0000C080, version 0x00000200, and carries several control registers for the PTP clock. .. table:: @@ -13,121 +13,180 @@ The PTP hardware clock register block has a header with type 0x0000C080, version ======== ============== ====== ====== ====== ====== ============= RBB+0x00 Type Vendor ID Type RO 0x0000C080 -------- -------------- -------------- -------------- ------------- - RBB+0x04 Version Major Minor Patch Meta RO 0x00000100 + RBB+0x04 Version Major Minor Patch Meta RO 0x00000200 -------- -------------- ------ ------ ------ ------ ------------- RBB+0x08 Next pointer Pointer to next register block RO - -------- -------------- ------------------------------ ------------- - RBB+0x0C Control Control RO - + RBB+0x0C Control Control RW - -------- -------------- ------------------------------ ------------- - RBB+0x10 Current time Current time (fractional ns) RO - + RBB+0x10 Current FNS Current fractional ns RO - -------- -------------- ------------------------------ ------------- - RBB+0x14 Current time Current time (ns) RO - + RBB+0x14 Current ToD Current ToD (ns) RO - -------- -------------- ------------------------------ ------------- - RBB+0x18 Current time Current time (sec, lower 32) RO - + RBB+0x18 Current ToD Current ToD (sec, lower 32) RO - -------- -------------- ------------------------------ ------------- - RBB+0x1C Current time Current time (sec, upper 32) RO - + RBB+0x1C Current ToD Current ToD (sec, upper 16) RO - -------- -------------- ------------------------------ ------------- - RBB+0x20 Get time Get time (fractional ns) RO - + RBB+0x20 Current rel Current rel. (ns, lower 32) RO - -------- -------------- ------------------------------ ------------- - RBB+0x24 Get time Get time (ns) RO - + RBB+0x24 Current rel Current rel. (ns, upper 16) RO - -------- -------------- ------------------------------ ------------- - RBB+0x28 Get time Get time (sec, lower 32) RO - + RBB+0x28 Current PTM Current PTM (ns, lower 32) RO - -------- -------------- ------------------------------ ------------- - RBB+0x2C Get time Get time (sec, upper 32) RO - + RBB+0x2C Current PTM Current PTM (ns, upper 32) RO - -------- -------------- ------------------------------ ------------- - RBB+0x30 Set time Set time (fractional ns) RW - + RBB+0x30 Snapshot FNS Snapshot fractional ns RO - -------- -------------- ------------------------------ ------------- - RBB+0x34 Set time Set time (ns) RW - + RBB+0x34 Snapshot ToD Snapshot ToD (ns) RO - -------- -------------- ------------------------------ ------------- - RBB+0x38 Set time Set time (sec, lower 32) RW - + RBB+0x38 Snapshot ToD Snapshot ToD (sec, lower 32) RO - -------- -------------- ------------------------------ ------------- - RBB+0x3C Set time Set time (sec, upper 32) RW - + RBB+0x3C Snapshot ToD Snapshot ToD (sec, upper 16) RO - -------- -------------- ------------------------------ ------------- - RBB+0x40 Period Period (fractional ns) RW - + RBB+0x40 Snapshot rel Snapshot rel. (ns, lower 32) RO - -------- -------------- ------------------------------ ------------- - RBB+0x44 Period Period (ns) RW - + RBB+0x44 Snapshot rel Snapshot rel. (ns, upper 16) RO - -------- -------------- ------------------------------ ------------- - RBB+0x48 Nominal period Nominal period (fractional ns) RO - + RBB+0x48 Snapshot PTM Snapshot PTM (ns, lower 32) RO - -------- -------------- ------------------------------ ------------- - RBB+0x4C Nominal period Nominal period (ns) RO - + RBB+0x4C Snapshot PTM Snapshot PTM (ns, upper 32) RO - -------- -------------- ------------------------------ ------------- - RBB+0x50 Adj time Adj time (fractional ns) RW - + RBB+0x50 Offset ToD Offset ToD (ns) RW - -------- -------------- ------------------------------ ------------- - RBB+0x54 Adj time Adj time (ns) RW - + RBB+0x54 Set ToD Set ToD (ns) RW - -------- -------------- ------------------------------ ------------- - RBB+0x58 Adj time count Adj time cycle count RW - + RBB+0x58 Set ToD Set ToD (sec, lower 32) RW - -------- -------------- ------------------------------ ------------- - RBB+0x5C Adj time act Adj time active RO - + RBB+0x5C Set ToD Set ToD (sec, upper 16) RW - + -------- -------------- ------------------------------ ------------- + RBB+0x60 Set rel Set rel. (ns, lower 32) RW - + -------- -------------- ------------------------------ ------------- + RBB+0x64 Set rel Set rel. (ns, upper 16) RW - + -------- -------------- ------------------------------ ------------- + RBB+0x68 Offset rel Offset relative (ns) RW - + -------- -------------- ------------------------------ ------------- + RBB+0x6C Offset FNS Offset FNS (fns) RW - + -------- -------------- ------------------------------ ------------- + RBB+0x70 Nominal period Nominal period (fractional ns) RO - + -------- -------------- ------------------------------ ------------- + RBB+0x74 Nominal period Nominal period (ns) RO - + -------- -------------- ------------------------------ ------------- + RBB+0x78 Period Period (fractional ns) RW - + -------- -------------- ------------------------------ ------------- + RBB+0x7C Period Period (ns) RW - ======== ============== ============================== ============= See :ref:`rb_overview` for definitions of the standard register block header fields. -.. object:: Current time +.. object:: Control - The current time registers read the current time from the PTP clock, with no double-buffering. + The control register contains several control and status bits relating to the operation of the PTP hardware clock. .. table:: ======== ====== ====== ====== ====== ============= Address 31..24 23..16 15..8 7..0 Reset value ======== ====== ====== ====== ====== ============= - RBB+0x10 Current time (fractional ns) RO - - -------- ------------------------------ ------------- - RBB+0x14 Current time (ns) RO - - -------- ------------------------------ ------------- - RBB+0x18 Current time (sec, lower 32) RO - - -------- ------------------------------ ------------- - RBB+0x1C Current time (sec, upper 32) RO - + RBB+0x0C Control RW - ======== ============================== ============= -.. object:: Get time + .. table:: + + === ======== + Bit Function + === ======== + 8 PPS pulse + 16 Locked + 24 Set ToD pending + 25 Offset ToD pending + 26 Set Relative pending + 27 Offset Relative pending + 28 Set Period pending + 29 Offset FNS pending + === ======== - The get time registers read the current time from the PTP clock, with all values latched coincident with reading the fractional ns register. + The PPS pulse bit reflects the current value of the stretched PPS output (rising edge is the active edge). + + The locked bit indicates that the PTP CDC logic between the PTP clock domain and the core clock domain is locked, and therefore the times in the current and snapshot registers are valid. + + The pending bits indicate that a set or offset has been requested, but has not yet been applied. + +.. object:: Current time + + The current time registers read the current time from the PTP clock, with no double-buffering. .. table:: ======== ====== ====== ====== ====== ============= Address 31..24 23..16 15..8 7..0 Reset value ======== ====== ====== ====== ====== ============= - RBB+0x20 Get time (fractional ns) RO - + RBB+0x10 Current fractional ns RO - -------- ------------------------------ ------------- - RBB+0x24 Get time (ns) RO - + RBB+0x14 Current ToD (ns) RO - -------- ------------------------------ ------------- - RBB+0x28 Get time (sec, lower 32) RO - + RBB+0x18 Current ToD (sec, lower 32) RO - -------- ------------------------------ ------------- - RBB+0x2C Get time (sec, upper 32) RO - + RBB+0x1C Current ToD (sec, upper 16) RO - + -------- ------------------------------ ------------- + RBB+0x20 Current rel. (ns, lower 32) RO - + -------- ------------------------------ ------------- + RBB+0x24 Current rel. (ns, upper 16) RO - + -------- ------------------------------ ------------- + RBB+0x28 Current PTM (ns, lower 32) RO - + -------- ------------------------------ ------------- + RBB+0x2C Current PTM (ns, upper 32) RO - ======== ============================== ============= -.. object:: Set time +.. object:: Snapshot time - The set time registers set the current time on the PTP clock, with all values latched coincident with writing the upper 32 bits of the seconds field. + The get time registers read the current time from the PTP clock, with all values latched coincident with reading the fractional ns register. .. table:: ======== ====== ====== ====== ====== ============= Address 31..24 23..16 15..8 7..0 Reset value ======== ====== ====== ====== ====== ============= - RBB+0x30 Set time (fractional ns) RW - + RBB+0x30 Snapshot fractional ns RO - -------- ------------------------------ ------------- - RBB+0x34 Set time (ns) RW - + RBB+0x34 Snapshot ToD (ns) RO - -------- ------------------------------ ------------- - RBB+0x38 Set time (sec, lower 32) RW - + RBB+0x38 Snapshot ToD (sec, lower 32) RO - -------- ------------------------------ ------------- - RBB+0x3C Set time (sec, upper 32) RW - + RBB+0x3C Snapshot ToD (sec, upper 16) RO - + -------- ------------------------------ ------------- + RBB+0x40 Snapshot rel. (ns, lower 32) RO - + -------- ------------------------------ ------------- + RBB+0x44 Snapshot rel. (ns, upper 16) RO - + -------- ------------------------------ ------------- + RBB+0x48 Snapshot PTM (ns, lower 32) RO - + -------- ------------------------------ ------------- + RBB+0x4C Snapshot PTM (ns, upper 32) RO - ======== ============================== ============= -.. object:: Period +.. object:: Set time - The period registers control the period of the PTP clock, with all values latched coincident with writing the ns field. The period value is accumulated into the PTP clock on every clock cycle. + The set time registers set the current time on the PTP clock, while the offset registers can be used to apply precise steps to the PTP clock. The ToD setting is applied when the upper 16 bits of the seconds field is written, and the relative setting is applied when the upper 16 bits of the ns field is written. The FNS and relative offset fields are 32 bit signed integers, while the ToD offset is a 30 bit signed integer with the two MSBs ignored. Offsets are applied immediately and atomically upon writing to the corresponding register. These registers are read-only while updates are pending, pending status is reported in the control register. .. table:: ======== ====== ====== ====== ====== ============= Address 31..24 23..16 15..8 7..0 Reset value ======== ====== ====== ====== ====== ============= - RBB+0x40 Period (fractional ns) RW - + RBB+0x50 Offset ToD (ns) RW - + -------- ------------------------------ ------------- + RBB+0x54 Set ToD (ns) RW - + -------- ------------------------------ ------------- + RBB+0x58 Set ToD (sec, lower 32) RW - + -------- ------------------------------ ------------- + RBB+0x5C Set ToD (sec, upper 16) RW - + -------- ------------------------------ ------------- + RBB+0x60 Set rel. (ns, lower 32) RW - -------- ------------------------------ ------------- - RBB+0x44 Period (ns) RW - + RBB+0x64 Set rel. (ns, upper 16) RW - + -------- ------------------------------ ------------- + RBB+0x68 Offset relative (ns) RW - + -------- ------------------------------ ------------- + RBB+0x6C Offset FNS (fns) RW - ======== ============================== ============= .. object:: Nominal period @@ -139,25 +198,21 @@ See :ref:`rb_overview` for definitions of the standard register block header fie ======== ====== ====== ====== ====== ============= Address 31..24 23..16 15..8 7..0 Reset value ======== ====== ====== ====== ====== ============= - RBB+0x48 Nominal period (fractional ns) RO - + RBB+0x70 Nominal period (fractional ns) RO - -------- ------------------------------ ------------- - RBB+0x4C Nominal period (ns) RO - + RBB+0x74 Nominal period (ns) RO - ======== ============================== ============= -.. object:: Adjust time +.. object:: Period - The adjust time registers can be used to slew the clock over some time period. An adjustment can be specified with some amount of time added every clock cycle for N cycles. + The period registers control the period of the PTP clock, with all values latched coincident with writing the ns field. The period value is accumulated into the PTP clock on every clock cycle, and applies to both the relative and ToD timestamps. .. table:: ======== ====== ====== ====== ====== ============= Address 31..24 23..16 15..8 7..0 Reset value ======== ====== ====== ====== ====== ============= - RBB+0x50 Adj time (fractional ns) RW - - -------- ------------------------------ ------------- - RBB+0x54 Adj time (ns) RW - - -------- ------------------------------ ------------- - RBB+0x58 Adj time cycle count RW - + RBB+0x78 Period (fractional ns) RW - -------- ------------------------------ ------------- - RBB+0x5C Adj time active RO - + RBB+0x7C Period (ns) RW - ======== ============================== ============= diff --git a/docs/source/rb/phc_perout.rst b/docs/source/rb/phc_perout.rst index 7ccb99434..9961041d6 100644 --- a/docs/source/rb/phc_perout.rst +++ b/docs/source/rb/phc_perout.rst @@ -46,6 +46,8 @@ The PTP period output register block has a header with type 0x0000C081, version See :ref:`rb_overview` for definitions of the standard register block header fields. +The period output module keeps track of the times for the next rising edge and next falling edge. Initially, it starts with the specified start time for the rising edge, and start time plus width for the falling edge. If the computed next rising edge time is in the past, the period will be added and it will be checked again, repeating this process until the next rising edge is in the future. Note that the period is added once per clock cycle, so it is recommended to compute a start time that is close to the current time, particularly when using a small period setting, so that the period output module can lock quickly. + .. object:: Control The control register contains several control and status bits relating to the operation of the period output module. @@ -77,8 +79,6 @@ See :ref:`rb_overview` for definitions of the standard register block header fie The error bit indicates that the period output module came out of lock due to the PTP clock being stepped. The error bit is self-clearing on either reacquisition of lock or a setting change. - The period output module keeps track of the times for the next rising edge and next falling edge. Initially, it starts with the specified start time for the rising edge, and start time plus width for the falling edge. If the computed next rising edge time is in the past, the period will be added and it will be checked again, repeating this process until the next rising edge is in the future. Note that the period is added once per clock cycle, so it is recommended to compute a start time that is close to the current time, particularly when using a small period setting, so that the period output module can lock quickly. - .. object:: Start time The start time registers determine the absolute start time for the output waveform (rising edge), with all values latched coincident with writing the upper 32 bits of the seconds field. diff --git a/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v b/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v index 01aaaf0bf..fe06c537b 100644 --- a/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v +++ b/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v @@ -314,13 +314,16 @@ module mqnic_app_block # input wire ptp_clk, input wire ptp_rst, input wire ptp_sample_clk, + input wire ptp_td_sd, input wire ptp_pps, input wire ptp_pps_str, - input wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - input wire ptp_ts_step, + input wire ptp_sync_locked, + input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_rel, + input wire ptp_sync_ts_rel_step, + input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_tod, + input wire ptp_sync_ts_tod_step, input wire ptp_sync_pps, - input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96, - input wire ptp_sync_ts_step, + input wire ptp_sync_pps_str, input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile index 3d546fc27..3a1e2e380 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile @@ -60,8 +60,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v VERILOG_SOURCES += ../../lib/axi/rtl/axi_vfifo_raw.v diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index a2c7dd7ae..25aa6cf07 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -308,14 +308,14 @@ def __init__(self, dut, msix_count=32): tx_clk=iface.port[k].port_tx_clk, tx_rst=iface.port[k].port_tx_rst, tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"), - tx_ptp_time=iface.port[k].port_tx_ptp_ts_96, + tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod, tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts, tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag, tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid, rx_clk=iface.port[k].port_rx_clk, rx_rst=iface.port[k].port_rx_rst, rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"), - rx_ptp_time=iface.port[k].port_rx_ptp_ts_96, + rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod, ifg=12, speed=eth_speed ) @@ -1015,8 +1015,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(eth_rtl_dir, "lfsr.v"), os.path.join(axi_rtl_dir, "axi_vfifo_raw.v"), diff --git a/fpga/app/template/rtl/mqnic_app_block.v b/fpga/app/template/rtl/mqnic_app_block.v index 22719f46a..46f5c22bb 100644 --- a/fpga/app/template/rtl/mqnic_app_block.v +++ b/fpga/app/template/rtl/mqnic_app_block.v @@ -314,13 +314,16 @@ module mqnic_app_block # input wire ptp_clk, input wire ptp_rst, input wire ptp_sample_clk, + input wire ptp_td_sd, input wire ptp_pps, input wire ptp_pps_str, - input wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - input wire ptp_ts_step, + input wire ptp_sync_locked, + input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_rel, + input wire ptp_sync_ts_rel_step, + input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_tod, + input wire ptp_sync_ts_tod_step, input wire ptp_sync_pps, - input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96, - input wire ptp_sync_ts_step, + input wire ptp_sync_pps_str, input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile index 8a813ff3d..574e84484 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile @@ -58,8 +58,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 65dd7908b..e984bbdb2 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -308,14 +308,14 @@ def __init__(self, dut, msix_count=32): tx_clk=iface.port[k].port_tx_clk, tx_rst=iface.port[k].port_tx_rst, tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"), - tx_ptp_time=iface.port[k].port_tx_ptp_ts_96, + tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod, tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts, tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag, tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid, rx_clk=iface.port[k].port_rx_clk, rx_rst=iface.port[k].port_rx_rst, rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"), - rx_ptp_time=iface.port[k].port_rx_ptp_ts_96, + rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod, ifg=12, speed=eth_speed ) @@ -814,8 +814,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index a53cbac2f..51072f016 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -378,13 +378,16 @@ module mqnic_core # input wire ptp_clk, input wire ptp_rst, input wire ptp_sample_clk, + output wire ptp_td_sd, output wire ptp_pps, output wire ptp_pps_str, - output wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - output wire ptp_ts_step, + output wire ptp_sync_locked, + output wire [63:0] ptp_sync_ts_rel, + output wire ptp_sync_ts_rel_step, + output wire [96:0] ptp_sync_ts_tod, + output wire ptp_sync_ts_tod_step, output wire ptp_sync_pps, - output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96, - output wire ptp_sync_ts_step, + output wire ptp_sync_pps_str, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, @@ -397,8 +400,8 @@ module mqnic_core # input wire [PORT_COUNT-1:0] tx_ptp_clk, input wire [PORT_COUNT-1:0] tx_ptp_rst, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_96, - output wire [PORT_COUNT-1:0] tx_ptp_ts_step, + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_tod, + output wire [PORT_COUNT-1:0] tx_ptp_ts_tod_step, output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] m_axis_tx_tdata, output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] m_axis_tx_tkeep, @@ -425,8 +428,8 @@ module mqnic_core # input wire [PORT_COUNT-1:0] rx_ptp_clk, input wire [PORT_COUNT-1:0] rx_ptp_rst, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_96, - output wire [PORT_COUNT-1:0] rx_ptp_ts_step, + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_tod, + output wire [PORT_COUNT-1:0] rx_ptp_ts_tod_step, input wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] s_axis_rx_tdata, input wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] s_axis_rx_tkeep, @@ -822,7 +825,6 @@ end mqnic_ptp #( .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -857,13 +859,16 @@ mqnic_ptp_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse) @@ -3485,8 +3490,8 @@ generate /* * PTP clock */ - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step), + .ptp_ts_tod(ptp_sync_ts_tod), + .ptp_ts_tod_step(ptp_sync_ts_tod_step), /* * Interrupt request output @@ -3525,68 +3530,114 @@ generate assign all_clocks[(n*PORTS_PER_IF+m)*2+0] = port_tx_clk; assign all_clocks[(n*PORTS_PER_IF+m)*2+1] = port_rx_clk; - wire [PTP_TS_WIDTH-1:0] port_rx_ptp_ts_96; - wire port_rx_ptp_ts_step; + wire [PTP_TS_WIDTH-1:0] port_rx_ptp_ts_tod; + wire port_rx_ptp_ts_tod_step; - wire [PTP_TS_WIDTH-1:0] port_tx_ptp_ts_96; - wire port_tx_ptp_ts_step; + wire [PTP_TS_WIDTH-1:0] port_tx_ptp_ts_tod; + wire port_tx_ptp_ts_tod_step; if (PTP_TS_ENABLE) begin: ptp // PTP CDC logic - ptp_clock_cdc #( - .TS_WIDTH(PTP_TS_WIDTH), - .NS_WIDTH(6), - .PIPELINE_OUTPUT(PTP_PORT_CDC_PIPELINE) + ptp_td_leaf #( + .TS_REL_EN(0), + .TS_TOD_EN(1), + .TS_FNS_W(16), + .TS_REL_NS_W(48), + .TS_TOD_S_W(48), + .TS_REL_W(64), + .TS_TOD_W(96), + .TD_SDI_PIPELINE(PTP_PORT_CDC_PIPELINE) ) - tx_ptp_cdc_inst ( - .input_clk(ptp_clk), - .input_rst(ptp_rst), - .output_clk(PTP_SEPARATE_TX_CLOCK ? port_tx_ptp_clk : port_tx_clk), - .output_rst(PTP_SEPARATE_TX_CLOCK ? port_tx_ptp_rst : port_tx_rst), + tx_ptp_td_leaf_inst ( + .clk(PTP_SEPARATE_TX_CLOCK ? port_tx_ptp_clk : port_tx_clk), + .rst(PTP_SEPARATE_TX_CLOCK ? port_tx_ptp_rst : port_tx_rst), .sample_clk(ptp_sample_clk), - .input_ts(ptp_ts_96), - .input_ts_step(ptp_ts_step), - .output_ts(port_tx_ptp_ts_96), - .output_ts_step(port_tx_ptp_ts_step), + + /* + * PTP clock interface + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_td_sdi(ptp_td_sd), + + /* + * Timestamp output + */ + .output_ts_rel(), + .output_ts_rel_step(), + .output_ts_tod(port_tx_ptp_ts_tod), + .output_ts_tod_step(port_tx_ptp_ts_tod_step), + + /* + * PPS output (ToD format only) + */ .output_pps(), + .output_pps_str(), + + /* + * Status + */ .locked() ); - ptp_clock_cdc #( - .TS_WIDTH(PTP_TS_WIDTH), - .NS_WIDTH(6), - .PIPELINE_OUTPUT(PTP_PORT_CDC_PIPELINE) + ptp_td_leaf #( + .TS_REL_EN(0), + .TS_TOD_EN(1), + .TS_FNS_W(16), + .TS_REL_NS_W(48), + .TS_TOD_S_W(48), + .TS_REL_W(64), + .TS_TOD_W(96), + .TD_SDI_PIPELINE(PTP_PORT_CDC_PIPELINE) ) - rx_ptp_cdc_inst ( - .input_clk(ptp_clk), - .input_rst(ptp_rst), - .output_clk(PTP_SEPARATE_RX_CLOCK ? port_rx_ptp_clk : port_rx_clk), - .output_rst(PTP_SEPARATE_RX_CLOCK ? port_rx_ptp_rst : port_rx_rst), + rx_ptp_td_leaf_inst ( + .clk(PTP_SEPARATE_RX_CLOCK ? port_rx_ptp_clk : port_rx_clk), + .rst(PTP_SEPARATE_RX_CLOCK ? port_rx_ptp_rst : port_rx_rst), .sample_clk(ptp_sample_clk), - .input_ts(ptp_ts_96), - .input_ts_step(ptp_ts_step), - .output_ts(port_rx_ptp_ts_96), - .output_ts_step(port_rx_ptp_ts_step), + + /* + * PTP clock interface + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_td_sdi(ptp_td_sd), + + /* + * Timestamp output + */ + .output_ts_rel(), + .output_ts_rel_step(), + .output_ts_tod(port_rx_ptp_ts_tod), + .output_ts_tod_step(port_rx_ptp_ts_tod_step), + + /* + * PPS output (ToD format only) + */ .output_pps(), + .output_pps_str(), + + /* + * Status + */ .locked() ); end else begin - assign port_tx_ptp_ts_96 = 0; - assign port_tx_ptp_ts_step = 1'b0; + assign port_tx_ptp_ts_tod = 0; + assign port_tx_ptp_ts_tod_step = 1'b0; - assign port_rx_ptp_ts_96 = 0; - assign port_rx_ptp_ts_step = 1'b0; + assign port_rx_ptp_ts_tod = 0; + assign port_rx_ptp_ts_tod_step = 1'b0; end - assign tx_ptp_ts_96[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = port_tx_ptp_ts_96; - assign tx_ptp_ts_step[n*PORTS_PER_IF+m] = port_tx_ptp_ts_step; + assign tx_ptp_ts_tod[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = port_tx_ptp_ts_tod; + assign tx_ptp_ts_tod_step[n*PORTS_PER_IF+m] = port_tx_ptp_ts_tod_step; - assign rx_ptp_ts_96[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = port_rx_ptp_ts_96; - assign rx_ptp_ts_step[n*PORTS_PER_IF+m] = port_rx_ptp_ts_step; + assign rx_ptp_ts_tod[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = port_rx_ptp_ts_tod; + assign rx_ptp_ts_tod_step[n*PORTS_PER_IF+m] = port_rx_ptp_ts_tod_step; end @@ -3897,13 +3948,16 @@ if (APP_ENABLE) begin : app .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), diff --git a/fpga/common/rtl/mqnic_core_axi.v b/fpga/common/rtl/mqnic_core_axi.v index 813aaeed3..d8f5f4d5c 100644 --- a/fpga/common/rtl/mqnic_core_axi.v +++ b/fpga/common/rtl/mqnic_core_axi.v @@ -340,13 +340,16 @@ module mqnic_core_axi # input wire ptp_clk, input wire ptp_rst, input wire ptp_sample_clk, + output wire ptp_td_sd, output wire ptp_pps, output wire ptp_pps_str, - output wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - output wire ptp_ts_step, + output wire ptp_sync_locked, + output wire [63:0] ptp_sync_ts_rel, + output wire ptp_sync_ts_rel_step, + output wire [96:0] ptp_sync_ts_tod, + output wire ptp_sync_ts_tod_step, output wire ptp_sync_pps, - output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96, - output wire ptp_sync_ts_step, + output wire ptp_sync_pps_str, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, @@ -359,8 +362,8 @@ module mqnic_core_axi # input wire [PORT_COUNT-1:0] tx_ptp_clk, input wire [PORT_COUNT-1:0] tx_ptp_rst, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_96, - output wire [PORT_COUNT-1:0] tx_ptp_ts_step, + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_tod, + output wire [PORT_COUNT-1:0] tx_ptp_ts_tod_step, output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] m_axis_tx_tdata, output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] m_axis_tx_tkeep, @@ -387,8 +390,8 @@ module mqnic_core_axi # input wire [PORT_COUNT-1:0] rx_ptp_clk, input wire [PORT_COUNT-1:0] rx_ptp_rst, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_96, - output wire [PORT_COUNT-1:0] rx_ptp_ts_step, + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_tod, + output wire [PORT_COUNT-1:0] rx_ptp_ts_tod_step, input wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] s_axis_rx_tdata, input wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] s_axis_rx_tkeep, @@ -1282,13 +1285,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1301,8 +1307,8 @@ core_inst ( .tx_ptp_clk(tx_ptp_clk), .tx_ptp_rst(tx_ptp_rst), - .tx_ptp_ts_96(tx_ptp_ts_96), - .tx_ptp_ts_step(tx_ptp_ts_step), + .tx_ptp_ts_tod(tx_ptp_ts_tod), + .tx_ptp_ts_tod_step(tx_ptp_ts_tod_step), .m_axis_tx_tdata(m_axis_tx_tdata), .m_axis_tx_tkeep(m_axis_tx_tkeep), @@ -1329,8 +1335,8 @@ core_inst ( .rx_ptp_clk(rx_ptp_clk), .rx_ptp_rst(rx_ptp_rst), - .rx_ptp_ts_96(rx_ptp_ts_96), - .rx_ptp_ts_step(rx_ptp_ts_step), + .rx_ptp_ts_tod(rx_ptp_ts_tod), + .rx_ptp_ts_tod_step(rx_ptp_ts_tod_step), .s_axis_rx_tdata(s_axis_rx_tdata), .s_axis_rx_tkeep(s_axis_rx_tkeep), diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v index 638265675..43b163230 100644 --- a/fpga/common/rtl/mqnic_core_pcie.v +++ b/fpga/common/rtl/mqnic_core_pcie.v @@ -357,13 +357,16 @@ module mqnic_core_pcie # input wire ptp_clk, input wire ptp_rst, input wire ptp_sample_clk, + output wire ptp_td_sd, output wire ptp_pps, output wire ptp_pps_str, - output wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - output wire ptp_ts_step, + output wire ptp_sync_locked, + output wire [63:0] ptp_sync_ts_rel, + output wire ptp_sync_ts_rel_step, + output wire [96:0] ptp_sync_ts_tod, + output wire ptp_sync_ts_tod_step, output wire ptp_sync_pps, - output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96, - output wire ptp_sync_ts_step, + output wire ptp_sync_pps_str, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, @@ -376,8 +379,8 @@ module mqnic_core_pcie # input wire [PORT_COUNT-1:0] tx_ptp_clk, input wire [PORT_COUNT-1:0] tx_ptp_rst, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_96, - output wire [PORT_COUNT-1:0] tx_ptp_ts_step, + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_tod, + output wire [PORT_COUNT-1:0] tx_ptp_ts_tod_step, output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] m_axis_tx_tdata, output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] m_axis_tx_tkeep, @@ -404,8 +407,8 @@ module mqnic_core_pcie # input wire [PORT_COUNT-1:0] rx_ptp_clk, input wire [PORT_COUNT-1:0] rx_ptp_rst, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_96, - output wire [PORT_COUNT-1:0] rx_ptp_ts_step, + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_tod, + output wire [PORT_COUNT-1:0] rx_ptp_ts_tod_step, input wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] s_axis_rx_tdata, input wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] s_axis_rx_tkeep, @@ -1938,13 +1941,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1957,8 +1963,8 @@ core_inst ( .tx_ptp_clk(tx_ptp_clk), .tx_ptp_rst(tx_ptp_rst), - .tx_ptp_ts_96(tx_ptp_ts_96), - .tx_ptp_ts_step(tx_ptp_ts_step), + .tx_ptp_ts_tod(tx_ptp_ts_tod), + .tx_ptp_ts_tod_step(tx_ptp_ts_tod_step), .m_axis_tx_tdata(m_axis_tx_tdata), .m_axis_tx_tkeep(m_axis_tx_tkeep), @@ -1985,8 +1991,8 @@ core_inst ( .rx_ptp_clk(rx_ptp_clk), .rx_ptp_rst(rx_ptp_rst), - .rx_ptp_ts_96(rx_ptp_ts_96), - .rx_ptp_ts_step(rx_ptp_ts_step), + .rx_ptp_ts_tod(rx_ptp_ts_tod), + .rx_ptp_ts_tod_step(rx_ptp_ts_tod_step), .s_axis_rx_tdata(s_axis_rx_tdata), .s_axis_rx_tkeep(s_axis_rx_tkeep), diff --git a/fpga/common/rtl/mqnic_core_pcie_ptile.v b/fpga/common/rtl/mqnic_core_pcie_ptile.v index 1df33947b..aff219bce 100644 --- a/fpga/common/rtl/mqnic_core_pcie_ptile.v +++ b/fpga/common/rtl/mqnic_core_pcie_ptile.v @@ -305,13 +305,16 @@ module mqnic_core_pcie_ptile # input wire ptp_clk, input wire ptp_rst, input wire ptp_sample_clk, + output wire ptp_td_sd, output wire ptp_pps, output wire ptp_pps_str, - output wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - output wire ptp_ts_step, + output wire ptp_sync_locked, + output wire [63:0] ptp_sync_ts_rel, + output wire ptp_sync_ts_rel_step, + output wire [96:0] ptp_sync_ts_tod, + output wire ptp_sync_ts_tod_step, output wire ptp_sync_pps, - output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96, - output wire ptp_sync_ts_step, + output wire ptp_sync_pps_str, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, @@ -324,8 +327,8 @@ module mqnic_core_pcie_ptile # input wire [PORT_COUNT-1:0] eth_tx_ptp_clk, input wire [PORT_COUNT-1:0] eth_tx_ptp_rst, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96, - output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step, + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod, + output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step, output wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] m_axis_eth_tx_tdata, output wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] m_axis_eth_tx_tkeep, @@ -352,8 +355,8 @@ module mqnic_core_pcie_ptile # input wire [PORT_COUNT-1:0] eth_rx_ptp_clk, input wire [PORT_COUNT-1:0] eth_rx_ptp_rst, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96, - output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step, + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod, + output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step, input wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] s_axis_eth_rx_tdata, input wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] s_axis_eth_rx_tkeep, @@ -1079,13 +1082,16 @@ core_pcie_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1098,8 +1104,8 @@ core_pcie_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_tx_tdata(m_axis_eth_tx_tdata), .m_axis_tx_tkeep(m_axis_eth_tx_tkeep), @@ -1126,8 +1132,8 @@ core_pcie_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_rx_tdata(s_axis_eth_rx_tdata), .s_axis_rx_tkeep(s_axis_eth_rx_tkeep), diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v index 0d025f8b4..d0946ed6f 100644 --- a/fpga/common/rtl/mqnic_core_pcie_s10.v +++ b/fpga/common/rtl/mqnic_core_pcie_s10.v @@ -301,13 +301,16 @@ module mqnic_core_pcie_s10 # input wire ptp_clk, input wire ptp_rst, input wire ptp_sample_clk, + output wire ptp_td_sd, output wire ptp_pps, output wire ptp_pps_str, - output wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - output wire ptp_ts_step, + output wire ptp_sync_locked, + output wire [63:0] ptp_sync_ts_rel, + output wire ptp_sync_ts_rel_step, + output wire [96:0] ptp_sync_ts_tod, + output wire ptp_sync_ts_tod_step, output wire ptp_sync_pps, - output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96, - output wire ptp_sync_ts_step, + output wire ptp_sync_pps_str, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, @@ -320,8 +323,8 @@ module mqnic_core_pcie_s10 # input wire [PORT_COUNT-1:0] eth_tx_ptp_clk, input wire [PORT_COUNT-1:0] eth_tx_ptp_rst, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96, - output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step, + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod, + output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step, output wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] m_axis_eth_tx_tdata, output wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] m_axis_eth_tx_tkeep, @@ -348,8 +351,8 @@ module mqnic_core_pcie_s10 # input wire [PORT_COUNT-1:0] eth_rx_ptp_clk, input wire [PORT_COUNT-1:0] eth_rx_ptp_rst, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96, - output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step, + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod, + output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step, input wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] s_axis_eth_rx_tdata, input wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] s_axis_eth_rx_tkeep, @@ -1088,13 +1091,16 @@ core_pcie_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1107,8 +1113,8 @@ core_pcie_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_tx_tdata(m_axis_eth_tx_tdata), .m_axis_tx_tkeep(m_axis_eth_tx_tkeep), @@ -1135,8 +1141,8 @@ core_pcie_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_rx_tdata(s_axis_eth_rx_tdata), .s_axis_rx_tkeep(s_axis_eth_rx_tkeep), diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v index 5dabfbb1a..bab8c3b1c 100644 --- a/fpga/common/rtl/mqnic_core_pcie_us.v +++ b/fpga/common/rtl/mqnic_core_pcie_us.v @@ -361,13 +361,16 @@ module mqnic_core_pcie_us # input wire ptp_clk, input wire ptp_rst, input wire ptp_sample_clk, + output wire ptp_td_sd, output wire ptp_pps, output wire ptp_pps_str, - output wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - output wire ptp_ts_step, + output wire ptp_sync_locked, + output wire [63:0] ptp_sync_ts_rel, + output wire ptp_sync_ts_rel_step, + output wire [96:0] ptp_sync_ts_tod, + output wire ptp_sync_ts_tod_step, output wire ptp_sync_pps, - output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96, - output wire ptp_sync_ts_step, + output wire ptp_sync_pps_str, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, @@ -380,8 +383,8 @@ module mqnic_core_pcie_us # input wire [PORT_COUNT-1:0] eth_tx_ptp_clk, input wire [PORT_COUNT-1:0] eth_tx_ptp_rst, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96, - output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step, + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod, + output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step, output wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] m_axis_eth_tx_tdata, output wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] m_axis_eth_tx_tkeep, @@ -408,8 +411,8 @@ module mqnic_core_pcie_us # input wire [PORT_COUNT-1:0] eth_rx_ptp_clk, input wire [PORT_COUNT-1:0] eth_rx_ptp_rst, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96, - output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step, + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod, + output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step, input wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] s_axis_eth_rx_tdata, input wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] s_axis_eth_rx_tkeep, @@ -1208,13 +1211,16 @@ core_pcie_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1227,8 +1233,8 @@ core_pcie_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_tx_tdata(m_axis_eth_tx_tdata), .m_axis_tx_tkeep(m_axis_eth_tx_tkeep), @@ -1255,8 +1261,8 @@ core_pcie_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_rx_tdata(s_axis_eth_rx_tdata), .s_axis_rx_tkeep(s_axis_eth_rx_tkeep), diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v index 38602341a..e64bafd4b 100644 --- a/fpga/common/rtl/mqnic_interface.v +++ b/fpga/common/rtl/mqnic_interface.v @@ -472,8 +472,8 @@ module mqnic_interface # /* * PTP clock */ - input wire [95:0] ptp_ts_96, - input wire ptp_ts_step, + input wire [95:0] ptp_ts_tod, + input wire ptp_ts_tod_step, /* * Interrupt request output @@ -2310,8 +2310,8 @@ for (n = 0; n < SCHEDULERS; n = n + 1) begin : sched /* * PTP clock */ - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_ts_96(ptp_ts_tod), + .ptp_ts_step(ptp_ts_tod_step), /* * Configuration diff --git a/fpga/common/rtl/mqnic_ptp.v b/fpga/common/rtl/mqnic_ptp.v index dd8d7ffb3..f54a31514 100644 --- a/fpga/common/rtl/mqnic_ptp.v +++ b/fpga/common/rtl/mqnic_ptp.v @@ -16,7 +16,6 @@ module mqnic_ptp # ( parameter PTP_CLK_PERIOD_NS_NUM = 4, parameter PTP_CLK_PERIOD_NS_DENOM = 1, - parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 0, parameter PTP_PEROUT_COUNT = 1, @@ -51,13 +50,16 @@ module mqnic_ptp # input wire ptp_clk, input wire ptp_rst, input wire ptp_sample_clk, + output wire ptp_td_sd, output wire ptp_pps, output wire ptp_pps_str, - output wire [95:0] ptp_ts_96, - output wire ptp_ts_step, + output wire ptp_sync_locked, + output wire [63:0] ptp_sync_ts_rel, + output wire ptp_sync_ts_rel_step, + output wire [95:0] ptp_sync_ts_tod, + output wire ptp_sync_ts_tod_step, output wire ptp_sync_pps, - output wire [95:0] ptp_sync_ts_96, - output wire ptp_sync_ts_step, + output wire ptp_sync_pps_str, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse @@ -128,10 +130,7 @@ end mqnic_ptp_clock #( .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), .REG_ADDR_WIDTH(REG_ADDR_WIDTH), .REG_DATA_WIDTH(REG_DATA_WIDTH), .REG_STRB_WIDTH(REG_STRB_WIDTH), @@ -163,13 +162,16 @@ ptp_clock_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step) + .ptp_sync_pps_str(ptp_sync_pps_str) ); generate @@ -209,8 +211,8 @@ if (PTP_PEROUT_ENABLE) begin /* * PTP clock */ - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step), + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step), .ptp_perout_locked(ptp_perout_locked[n]), .ptp_perout_error(ptp_perout_error[n]), .ptp_perout_pulse(ptp_perout_pulse[n]) diff --git a/fpga/common/rtl/mqnic_ptp_clock.v b/fpga/common/rtl/mqnic_ptp_clock.v index ef72a896e..97124e9ce 100644 --- a/fpga/common/rtl/mqnic_ptp_clock.v +++ b/fpga/common/rtl/mqnic_ptp_clock.v @@ -16,10 +16,7 @@ module mqnic_ptp_clock # ( parameter PTP_CLK_PERIOD_NS_NUM = 4, parameter PTP_CLK_PERIOD_NS_DENOM = 1, - parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, parameter REG_ADDR_WIDTH = 7, parameter REG_DATA_WIDTH = 32, parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8), @@ -51,13 +48,16 @@ module mqnic_ptp_clock # input wire ptp_clk, input wire ptp_rst, input wire ptp_sample_clk, + output wire ptp_td_sd, output wire ptp_pps, output wire ptp_pps_str, - output wire [95:0] ptp_ts_96, - output wire ptp_ts_step, + output wire ptp_sync_locked, + output wire [63:0] ptp_sync_ts_rel, + output wire ptp_sync_ts_rel_step, + output wire [95:0] ptp_sync_ts_tod, + output wire ptp_sync_ts_tod_step, output wire ptp_sync_pps, - output wire [95:0] ptp_sync_ts_96, - output wire ptp_sync_ts_step + output wire ptp_sync_pps_str ); parameter PTP_FNS_WIDTH = 32; @@ -67,9 +67,6 @@ parameter PTP_CLK_PERIOD_NS_REM = PTP_CLK_PERIOD_NS_NUM - PTP_CLK_PERIOD_NS*PTP_ parameter PTP_CLK_PERIOD_FNS = (PTP_CLK_PERIOD_NS_REM * {32'd1, {PTP_FNS_WIDTH{1'b0}}}) / PTP_CLK_PERIOD_NS_DENOM; parameter PTP_CLK_PERIOD_FNS_REM = (PTP_CLK_PERIOD_NS_REM * {32'd1, {PTP_FNS_WIDTH{1'b0}}}) - PTP_CLK_PERIOD_FNS*PTP_CLK_PERIOD_NS_DENOM; -parameter PTP_PERIOD_NS_WIDTH = $clog2(PTP_CLK_PERIOD_NS+1) + 2; -parameter PTP_OFFSET_NS_WIDTH = 30; - localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}}; // check configuration @@ -100,17 +97,200 @@ reg reg_wr_ack_reg = 1'b0; reg [REG_DATA_WIDTH-1:0] reg_rd_data_reg = 0; reg reg_rd_ack_reg = 1'b0; -reg [95:0] get_ptp_ts_96_reg = 0; -reg [95:0] set_ptp_ts_96_reg = 0; -reg set_ptp_ts_96_valid_reg = 0; -reg [PTP_PERIOD_NS_WIDTH-1:0] set_ptp_period_ns_reg = PTP_CLK_PERIOD_NS; +reg [95:0] get_ptp_ts_tod_reg = 0; +reg [29:0] set_ptp_ts_tod_ns_reg = 0; +reg [47:0] set_ptp_ts_tod_s_reg = 0; + +reg set_ptp_ts_tod_req_reg = 1'b0; +(* shreg_extract = "no" *) +reg set_ptp_ts_tod_req_sync1_reg = 1'b0, set_ptp_ts_tod_req_sync2_reg = 1'b0; + +reg set_ptp_ts_tod_ack_reg = 1'b0; +(* shreg_extract = "no" *) +reg set_ptp_ts_tod_ack_sync1_reg = 1'b0, set_ptp_ts_tod_ack_sync2_reg = 1'b0; + +reg set_ptp_ts_tod_valid_reg = 0; +wire set_ptp_ts_tod_ready; + +reg [29:0] offset_ptp_ts_tod_ns_reg = 0; + +reg offset_ptp_ts_tod_req_reg = 1'b0; +(* shreg_extract = "no" *) +reg offset_ptp_ts_tod_req_sync1_reg = 1'b0, offset_ptp_ts_tod_req_sync2_reg = 1'b0; + +reg offset_ptp_ts_tod_ack_reg = 1'b0; +(* shreg_extract = "no" *) +reg offset_ptp_ts_tod_ack_sync1_reg = 1'b0, offset_ptp_ts_tod_ack_sync2_reg = 1'b0; + +reg offset_ptp_ts_tod_valid_reg = 0; +wire offset_ptp_ts_tod_ready; + +reg [63:0] get_ptp_ts_rel_reg = 0; +reg [47:0] set_ptp_ts_rel_ns_reg = 0; + +reg set_ptp_ts_rel_req_reg = 1'b0; +(* shreg_extract = "no" *) +reg set_ptp_ts_rel_req_sync1_reg = 1'b0, set_ptp_ts_rel_req_sync2_reg = 1'b0; + +reg set_ptp_ts_rel_ack_reg = 1'b0; +(* shreg_extract = "no" *) +reg set_ptp_ts_rel_ack_sync1_reg = 1'b0, set_ptp_ts_rel_ack_sync2_reg = 1'b0; + +reg set_ptp_ts_rel_valid_reg = 0; +wire set_ptp_ts_rel_ready; + +reg [31:0] offset_ptp_ts_rel_ns_reg = 0; + +reg offset_ptp_ts_rel_req_reg = 1'b0; +(* shreg_extract = "no" *) +reg offset_ptp_ts_rel_req_sync1_reg = 1'b0, offset_ptp_ts_rel_req_sync2_reg = 1'b0; + +reg offset_ptp_ts_rel_ack_reg = 1'b0; +(* shreg_extract = "no" *) +reg offset_ptp_ts_rel_ack_sync1_reg = 1'b0, offset_ptp_ts_rel_ack_sync2_reg = 1'b0; + +reg offset_ptp_ts_rel_valid_reg = 0; +wire offset_ptp_ts_rel_ready; + +reg [7:0] set_ptp_period_ns_reg = PTP_CLK_PERIOD_NS; reg [PTP_FNS_WIDTH-1:0] set_ptp_period_fns_reg = PTP_CLK_PERIOD_FNS; + +reg set_ptp_period_req_reg = 1'b0; +(* shreg_extract = "no" *) +reg set_ptp_period_req_sync1_reg = 1'b0, set_ptp_period_req_sync2_reg = 1'b0; + +reg set_ptp_period_ack_reg = 1'b0; +(* shreg_extract = "no" *) +reg set_ptp_period_ack_sync1_reg = 1'b0, set_ptp_period_ack_sync2_reg = 1'b0; + reg set_ptp_period_valid_reg = 0; -reg [PTP_OFFSET_NS_WIDTH-1:0] set_ptp_offset_ns_reg = 0; -reg [PTP_FNS_WIDTH-1:0] set_ptp_offset_fns_reg = 0; -reg [15:0] set_ptp_offset_count_reg = 0; -reg set_ptp_offset_valid_reg = 0; -wire set_ptp_offset_active; +wire set_ptp_period_ready; + +reg [31:0] offset_ptp_ts_fns_reg = 0; + +reg offset_ptp_ts_req_reg = 1'b0; +(* shreg_extract = "no" *) +reg offset_ptp_ts_req_sync1_reg = 1'b0, offset_ptp_ts_req_sync2_reg = 1'b0; + +reg offset_ptp_ts_ack_reg = 1'b0; +(* shreg_extract = "no" *) +reg offset_ptp_ts_ack_sync1_reg = 1'b0, offset_ptp_ts_ack_sync2_reg = 1'b0; + +reg offset_ptp_ts_valid_reg = 0; +wire offset_ptp_ts_ready; + +always @(posedge ptp_clk) begin + set_ptp_ts_tod_req_sync1_reg <= set_ptp_ts_tod_req_reg; + set_ptp_ts_tod_req_sync2_reg <= set_ptp_ts_tod_req_sync1_reg; + offset_ptp_ts_tod_req_sync1_reg <= offset_ptp_ts_tod_req_reg; + offset_ptp_ts_tod_req_sync2_reg <= offset_ptp_ts_tod_req_sync1_reg; + set_ptp_ts_rel_req_sync1_reg <= set_ptp_ts_rel_req_reg; + set_ptp_ts_rel_req_sync2_reg <= set_ptp_ts_rel_req_sync1_reg; + offset_ptp_ts_rel_req_sync1_reg <= offset_ptp_ts_rel_req_reg; + offset_ptp_ts_rel_req_sync2_reg <= offset_ptp_ts_rel_req_sync1_reg; + set_ptp_period_req_sync1_reg <= set_ptp_period_req_reg; + set_ptp_period_req_sync2_reg <= set_ptp_period_req_sync1_reg; + offset_ptp_ts_req_sync1_reg <= offset_ptp_ts_req_reg; + offset_ptp_ts_req_sync2_reg <= offset_ptp_ts_req_sync1_reg; +end + +always @(posedge clk) begin + set_ptp_ts_tod_ack_sync1_reg <= set_ptp_ts_tod_ack_reg; + set_ptp_ts_tod_ack_sync2_reg <= set_ptp_ts_tod_ack_sync1_reg; + offset_ptp_ts_tod_ack_sync1_reg <= offset_ptp_ts_tod_ack_reg; + offset_ptp_ts_tod_ack_sync2_reg <= offset_ptp_ts_tod_ack_sync1_reg; + set_ptp_ts_rel_ack_sync1_reg <= set_ptp_ts_rel_ack_reg; + set_ptp_ts_rel_ack_sync2_reg <= set_ptp_ts_rel_ack_sync1_reg; + offset_ptp_ts_rel_ack_sync1_reg <= offset_ptp_ts_rel_ack_reg; + offset_ptp_ts_rel_ack_sync2_reg <= offset_ptp_ts_rel_ack_sync1_reg; + set_ptp_period_ack_sync1_reg <= set_ptp_period_ack_reg; + set_ptp_period_ack_sync2_reg <= set_ptp_period_ack_sync1_reg; + offset_ptp_ts_ack_sync1_reg <= offset_ptp_ts_ack_reg; + offset_ptp_ts_ack_sync2_reg <= offset_ptp_ts_ack_sync1_reg; +end + +always @(posedge ptp_clk) begin + if (set_ptp_ts_tod_ack_reg) begin + set_ptp_ts_tod_ack_reg <= set_ptp_ts_tod_req_sync2_reg; + end else begin + if (set_ptp_ts_tod_valid_reg && set_ptp_ts_tod_ready) begin + set_ptp_ts_tod_valid_reg <= 1'b0; + set_ptp_ts_tod_ack_reg <= 1'b1; + end else begin + set_ptp_ts_tod_valid_reg <= set_ptp_ts_tod_req_sync2_reg; + end + end + + if (offset_ptp_ts_tod_ack_reg) begin + offset_ptp_ts_tod_ack_reg <= offset_ptp_ts_tod_req_sync2_reg; + end else begin + if (offset_ptp_ts_tod_valid_reg && offset_ptp_ts_tod_ready) begin + offset_ptp_ts_tod_valid_reg <= 1'b0; + offset_ptp_ts_tod_ack_reg <= 1'b1; + end else begin + offset_ptp_ts_tod_valid_reg <= offset_ptp_ts_tod_req_sync2_reg; + end + end + + if (set_ptp_ts_rel_ack_reg) begin + set_ptp_ts_rel_ack_reg <= set_ptp_ts_rel_req_sync2_reg; + end else begin + if (set_ptp_ts_rel_valid_reg && set_ptp_ts_rel_ready) begin + set_ptp_ts_rel_valid_reg <= 1'b0; + set_ptp_ts_rel_ack_reg <= 1'b1; + end else begin + set_ptp_ts_rel_valid_reg <= set_ptp_ts_rel_req_sync2_reg; + end + end + + if (offset_ptp_ts_rel_ack_reg) begin + offset_ptp_ts_rel_ack_reg <= offset_ptp_ts_rel_req_sync2_reg; + end else begin + if (offset_ptp_ts_rel_valid_reg && offset_ptp_ts_rel_ready) begin + offset_ptp_ts_rel_valid_reg <= 1'b0; + offset_ptp_ts_rel_ack_reg <= 1'b1; + end else begin + offset_ptp_ts_rel_valid_reg <= offset_ptp_ts_rel_req_sync2_reg; + end + end + + if (set_ptp_period_ack_reg) begin + set_ptp_period_ack_reg <= set_ptp_period_req_sync2_reg; + end else begin + if (set_ptp_period_valid_reg && set_ptp_period_ready) begin + set_ptp_period_valid_reg <= 1'b0; + set_ptp_period_ack_reg <= 1'b1; + end else begin + set_ptp_period_valid_reg <= set_ptp_period_req_sync2_reg; + end + end + + if (offset_ptp_ts_ack_reg) begin + offset_ptp_ts_ack_reg <= offset_ptp_ts_req_sync2_reg; + end else begin + if (offset_ptp_ts_valid_reg && offset_ptp_ts_ready) begin + offset_ptp_ts_valid_reg <= 1'b0; + offset_ptp_ts_ack_reg <= 1'b1; + end else begin + offset_ptp_ts_valid_reg <= offset_ptp_ts_req_sync2_reg; + end + end + + if (ptp_rst) begin + set_ptp_ts_tod_ack_reg <= 1'b0; + set_ptp_ts_tod_valid_reg <= 1'b0; + offset_ptp_ts_tod_ack_reg <= 1'b0; + offset_ptp_ts_tod_valid_reg <= 1'b0; + set_ptp_ts_rel_ack_reg <= 1'b0; + set_ptp_ts_rel_valid_reg <= 1'b0; + offset_ptp_ts_rel_ack_reg <= 1'b0; + offset_ptp_ts_rel_valid_reg <= 1'b0; + set_ptp_period_ack_reg <= 1'b0; + set_ptp_period_valid_reg <= 1'b0; + offset_ptp_ts_ack_reg <= 1'b0; + offset_ptp_ts_valid_reg <= 1'b0; + end +end assign reg_wr_wait = 1'b0; assign reg_wr_ack = reg_wr_ack_reg; @@ -123,31 +303,83 @@ always @(posedge clk) begin reg_rd_data_reg <= 0; reg_rd_ack_reg <= 1'b0; + set_ptp_ts_tod_req_reg <= set_ptp_ts_tod_req_reg && !set_ptp_ts_tod_ack_sync2_reg; + offset_ptp_ts_tod_req_reg <= offset_ptp_ts_tod_req_reg && !offset_ptp_ts_tod_ack_sync2_reg; + set_ptp_ts_rel_req_reg <= set_ptp_ts_rel_req_reg && !set_ptp_ts_rel_ack_sync2_reg; + offset_ptp_ts_rel_req_reg <= offset_ptp_ts_rel_req_reg && !offset_ptp_ts_rel_ack_sync2_reg; + offset_ptp_ts_req_reg <= offset_ptp_ts_req_reg && !offset_ptp_ts_ack_sync2_reg; + set_ptp_period_req_reg <= set_ptp_period_req_reg && !set_ptp_period_ack_sync2_reg; + if (reg_wr_en && !reg_wr_ack_reg) begin // write operation reg_wr_ack_reg <= 1'b1; case ({reg_wr_addr >> 2, 2'b00}) // PHC - RBB+7'h30: set_ptp_ts_96_reg[15:0] <= reg_wr_data; // PTP set fns - RBB+7'h34: set_ptp_ts_96_reg[45:16] <= reg_wr_data; // PTP set ns - RBB+7'h38: set_ptp_ts_96_reg[79:48] <= reg_wr_data; // PTP set sec l - RBB+7'h3C: begin - // PTP set sec h - set_ptp_ts_96_reg[95:80] <= reg_wr_data; - set_ptp_ts_96_valid_reg <= !set_ptp_ts_96_valid_reg; + RBB+7'h50: begin + // PTP offset ToD + if (!offset_ptp_ts_tod_req_reg || offset_ptp_ts_tod_ack_sync2_reg) begin + offset_ptp_ts_tod_ns_reg <= reg_wr_data; + offset_ptp_ts_tod_req_reg <= reg_wr_data != 0; + end end - RBB+7'h40: set_ptp_period_fns_reg <= reg_wr_data; // PTP period fns - RBB+7'h44: begin - // PTP period ns - set_ptp_period_ns_reg <= reg_wr_data; - set_ptp_period_valid_reg <= !set_ptp_period_valid_reg; + RBB+7'h54: begin + // PTP set ToD ns + if (!set_ptp_ts_tod_req_reg || set_ptp_ts_tod_ack_sync2_reg) begin + set_ptp_ts_tod_ns_reg <= reg_wr_data; + end end - RBB+7'h50: set_ptp_offset_fns_reg <= reg_wr_data; // PTP offset fns - RBB+7'h54: set_ptp_offset_ns_reg <= reg_wr_data; // PTP offset ns RBB+7'h58: begin - // PTP offset count - set_ptp_offset_count_reg <= reg_wr_data; - set_ptp_offset_valid_reg <= !set_ptp_offset_valid_reg; + // PTP set ToD sec l + if (!set_ptp_ts_tod_req_reg || set_ptp_ts_tod_ack_sync2_reg) begin + set_ptp_ts_tod_s_reg[31:0] <= reg_wr_data; + end + end + RBB+7'h5C: begin + // PTP set ToD sec h + if (!set_ptp_ts_tod_req_reg || set_ptp_ts_tod_ack_sync2_reg) begin + set_ptp_ts_tod_s_reg[47:32] <= reg_wr_data; + set_ptp_ts_tod_req_reg <= 1'b1; + end + end + RBB+7'h60: begin + // PTP set rel ns l + if (!set_ptp_ts_rel_req_reg || set_ptp_ts_rel_ack_sync2_reg) begin + set_ptp_ts_rel_ns_reg[31:0] <= reg_wr_data; + end + end + RBB+7'h64: begin + // PTP set rel ns h + if (!set_ptp_ts_rel_req_reg || set_ptp_ts_rel_ack_sync2_reg) begin + set_ptp_ts_rel_ns_reg[47:32] <= reg_wr_data; + set_ptp_ts_rel_req_reg <= 1'b1; + end + end + RBB+7'h68: begin + // PTP offset rel + if (!offset_ptp_ts_rel_req_reg || offset_ptp_ts_rel_ack_sync2_reg) begin + offset_ptp_ts_rel_ns_reg <= reg_wr_data; + offset_ptp_ts_rel_req_reg <= reg_wr_data != 0; + end + end + RBB+7'h6C: begin + // PTP offset FNS + if (!offset_ptp_ts_req_reg || offset_ptp_ts_ack_sync2_reg) begin + offset_ptp_ts_fns_reg <= reg_wr_data; + offset_ptp_ts_req_reg <= reg_wr_data != 0; + end + end + RBB+7'h78: begin + // PTP period fns + if (!set_ptp_period_req_reg || set_ptp_period_ack_sync2_reg) begin + set_ptp_period_fns_reg <= reg_wr_data; + end + end + RBB+7'h7C: begin + // PTP period ns + if (!set_ptp_period_req_reg || set_ptp_period_ack_sync2_reg) begin + set_ptp_period_ns_reg <= reg_wr_data; + set_ptp_period_req_reg <= 1'b1; + end end default: reg_wr_ack_reg <= 1'b0; endcase @@ -159,39 +391,52 @@ always @(posedge clk) begin case ({reg_rd_addr >> 2, 2'b00}) // PHC RBB+7'h00: reg_rd_data_reg <= 32'h0000C080; // PHC: Type - RBB+7'h04: reg_rd_data_reg <= 32'h00000100; // PHC: Version + RBB+7'h04: reg_rd_data_reg <= 32'h00000200; // PHC: Version RBB+7'h08: reg_rd_data_reg <= RB_NEXT_PTR; // PHC: Next header RBB+7'h0C: begin - // PHC features - reg_rd_data_reg[7:0] <= PTP_PEROUT_ENABLE ? PTP_PEROUT_COUNT : 0; - reg_rd_data_reg[15:8] <= 0; - reg_rd_data_reg[23:16] <= 0; - reg_rd_data_reg[31:24] <= 0; + // PHC control + reg_rd_data_reg[8] <= ptp_sync_pps_str; // PPS + reg_rd_data_reg[16] <= ptp_sync_locked; // Locked + reg_rd_data_reg[24] <= set_ptp_ts_tod_req_reg || set_ptp_ts_tod_ack_sync2_reg; // ToD set pending + reg_rd_data_reg[25] <= offset_ptp_ts_tod_req_reg || offset_ptp_ts_tod_ack_sync2_reg; // ToD offset pending + reg_rd_data_reg[26] <= set_ptp_ts_rel_req_reg || set_ptp_ts_rel_ack_sync2_reg; // Relative set pending + reg_rd_data_reg[27] <= offset_ptp_ts_rel_req_reg || offset_ptp_ts_rel_ack_sync2_reg; // Relative offset pending + reg_rd_data_reg[28] <= set_ptp_period_req_reg || set_ptp_period_ack_sync2_reg; // Period set pending + reg_rd_data_reg[29] <= offset_ptp_ts_req_reg || offset_ptp_ts_ack_sync2_reg; // FNS offset pending end - RBB+7'h10: reg_rd_data_reg <= ptp_sync_ts_96[15:0]; // PTP cur fns - RBB+7'h14: reg_rd_data_reg <= ptp_sync_ts_96[45:16]; // PTP cur ns - RBB+7'h18: reg_rd_data_reg <= ptp_sync_ts_96[79:48]; // PTP cur sec l - RBB+7'h1C: reg_rd_data_reg <= ptp_sync_ts_96[95:80]; // PTP cur sec h - RBB+7'h20: begin - // PTP get fns - get_ptp_ts_96_reg <= ptp_sync_ts_96; - reg_rd_data_reg <= ptp_sync_ts_96[15:0]; + RBB+7'h10: reg_rd_data_reg <= {ptp_sync_ts_tod[15:0], 16'd0}; // PTP cur fns + RBB+7'h14: reg_rd_data_reg <= ptp_sync_ts_tod[47:16]; // PTP cur ToD ns + RBB+7'h18: reg_rd_data_reg <= ptp_sync_ts_tod[79:48]; // PTP cur ToD sec l + RBB+7'h1C: reg_rd_data_reg <= ptp_sync_ts_tod[95:80]; // PTP cur ToD sec h + RBB+7'h20: reg_rd_data_reg <= ptp_sync_ts_rel[47:16]; // PTP cur rel ns l + RBB+7'h24: reg_rd_data_reg <= ptp_sync_ts_rel[63:48]; // PTP cur rel ns h + RBB+7'h28: reg_rd_data_reg <= 0; // PTP cur PTM l + RBB+7'h2C: reg_rd_data_reg <= 0; // PTP cur PTM h + RBB+7'h30: begin + // PTP snapshot fns + get_ptp_ts_tod_reg <= ptp_sync_ts_tod; + get_ptp_ts_rel_reg <= ptp_sync_ts_rel; + reg_rd_data_reg <= {ptp_sync_ts_tod[15:0], 16'd0}; end - RBB+7'h24: reg_rd_data_reg <= get_ptp_ts_96_reg[45:16]; // PTP get ns - RBB+7'h28: reg_rd_data_reg <= get_ptp_ts_96_reg[79:48]; // PTP get sec l - RBB+7'h2C: reg_rd_data_reg <= get_ptp_ts_96_reg[95:80]; // PTP get sec h - RBB+7'h30: reg_rd_data_reg <= set_ptp_ts_96_reg[15:0]; // PTP set fns - RBB+7'h34: reg_rd_data_reg <= set_ptp_ts_96_reg[45:16]; // PTP set ns - RBB+7'h38: reg_rd_data_reg <= set_ptp_ts_96_reg[79:48]; // PTP set sec l - RBB+7'h3C: reg_rd_data_reg <= set_ptp_ts_96_reg[95:80]; // PTP set sec h - RBB+7'h40: reg_rd_data_reg <= set_ptp_period_fns_reg; // PTP period fns - RBB+7'h44: reg_rd_data_reg <= set_ptp_period_ns_reg; // PTP period ns - RBB+7'h48: reg_rd_data_reg <= PTP_CLK_PERIOD_FNS; // PTP nom period fns - RBB+7'h4C: reg_rd_data_reg <= PTP_CLK_PERIOD_NS; // PTP nom period ns - RBB+7'h50: reg_rd_data_reg <= set_ptp_offset_fns_reg; // PTP offset fns - RBB+7'h54: reg_rd_data_reg <= set_ptp_offset_ns_reg; // PTP offset ns - RBB+7'h58: reg_rd_data_reg <= set_ptp_offset_count_reg; // PTP offset count - RBB+7'h5C: reg_rd_data_reg <= set_ptp_offset_active; // PTP offset status + RBB+7'h34: reg_rd_data_reg <= get_ptp_ts_tod_reg[45:16]; // PTP snapshot ToD ns + RBB+7'h38: reg_rd_data_reg <= get_ptp_ts_tod_reg[79:48]; // PTP snapshot ToD sec l + RBB+7'h3C: reg_rd_data_reg <= get_ptp_ts_tod_reg[95:80]; // PTP snapshot ToD sec h + RBB+7'h40: reg_rd_data_reg <= get_ptp_ts_rel_reg[47:16]; // PTP snapshot rel ns l + RBB+7'h44: reg_rd_data_reg <= get_ptp_ts_rel_reg[63:48]; // PTP snapshot rel ns h + RBB+7'h48: reg_rd_data_reg <= 0; // PTP snapshot PTM l + RBB+7'h4C: reg_rd_data_reg <= 0; // PTP snapshot PTM h + RBB+7'h50: reg_rd_data_reg <= offset_ptp_ts_tod_ns_reg; // PTP offset ToD + RBB+7'h54: reg_rd_data_reg <= set_ptp_ts_tod_ns_reg; // PTP set ToD ns + RBB+7'h58: reg_rd_data_reg <= set_ptp_ts_tod_s_reg[31:0]; // PTP set ToD sec l + RBB+7'h5C: reg_rd_data_reg <= set_ptp_ts_tod_s_reg[47:16]; // PTP set ToD sec h + RBB+7'h60: reg_rd_data_reg <= set_ptp_ts_rel_ns_reg[31:0]; // PTP set rel ns l + RBB+7'h64: reg_rd_data_reg <= set_ptp_ts_rel_ns_reg[47:16]; // PTP set rel ns h + RBB+7'h68: reg_rd_data_reg <= offset_ptp_ts_rel_ns_reg; // PTP offset rel + RBB+7'h6C: reg_rd_data_reg <= offset_ptp_ts_fns_reg; // PTP offset FNS + RBB+7'h70: reg_rd_data_reg <= PTP_CLK_PERIOD_FNS; // PTP nom period fns + RBB+7'h74: reg_rd_data_reg <= PTP_CLK_PERIOD_NS; // PTP nom period ns + RBB+7'h78: reg_rd_data_reg <= set_ptp_period_fns_reg; // PTP period fns + RBB+7'h7C: reg_rd_data_reg <= set_ptp_period_ns_reg; // PTP period ns default: reg_rd_ack_reg <= 1'b0; endcase end @@ -202,144 +447,118 @@ always @(posedge clk) begin set_ptp_period_ns_reg <= PTP_CLK_PERIOD_NS; set_ptp_period_fns_reg <= PTP_CLK_PERIOD_FNS; - end -end - -(* shreg_extract = "no" *) -reg set_ptp_ts_96_valid_sync_1_reg = 1'b0; -(* shreg_extract = "no" *) -reg set_ptp_ts_96_valid_sync_2_reg = 1'b0; -(* shreg_extract = "no" *) -reg set_ptp_ts_96_valid_sync_3_reg = 1'b0; - -(* shreg_extract = "no" *) -reg set_ptp_period_valid_sync_1_reg = 1'b0; -(* shreg_extract = "no" *) -reg set_ptp_period_valid_sync_2_reg = 1'b0; -(* shreg_extract = "no" *) -reg set_ptp_period_valid_sync_3_reg = 1'b0; - -(* shreg_extract = "no" *) -reg set_ptp_offset_valid_sync_1_reg = 1'b0; -(* shreg_extract = "no" *) -reg set_ptp_offset_valid_sync_2_reg = 1'b0; -(* shreg_extract = "no" *) -reg set_ptp_offset_valid_sync_3_reg = 1'b0; -always @(posedge ptp_clk) begin - set_ptp_ts_96_valid_sync_1_reg <= set_ptp_ts_96_valid_reg; - set_ptp_ts_96_valid_sync_2_reg <= set_ptp_ts_96_valid_sync_1_reg; - set_ptp_ts_96_valid_sync_3_reg <= set_ptp_ts_96_valid_sync_2_reg; - - set_ptp_period_valid_sync_1_reg <= set_ptp_period_valid_reg; - set_ptp_period_valid_sync_2_reg <= set_ptp_period_valid_sync_1_reg; - set_ptp_period_valid_sync_3_reg <= set_ptp_period_valid_sync_2_reg; - - set_ptp_offset_valid_sync_1_reg <= set_ptp_offset_valid_reg; - set_ptp_offset_valid_sync_2_reg <= set_ptp_offset_valid_sync_1_reg; - set_ptp_offset_valid_sync_3_reg <= set_ptp_offset_valid_sync_2_reg; + set_ptp_ts_tod_req_reg <= 1'b0; + offset_ptp_ts_tod_req_reg <= 1'b0; + set_ptp_ts_rel_req_reg <= 1'b0; + offset_ptp_ts_rel_req_reg <= 1'b0; + offset_ptp_ts_req_reg <= 1'b0; + set_ptp_period_req_reg <= 1'b0; + end end // PTP clock -ptp_clock #( - .PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH), - .OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH), - .FNS_WIDTH(PTP_FNS_WIDTH), - .PERIOD_NS(PTP_CLK_PERIOD_NS), - .PERIOD_FNS(PTP_CLK_PERIOD_FNS), - .DRIFT_ENABLE(0), - .DRIFT_NS(0), - .DRIFT_FNS(PTP_CLK_PERIOD_FNS_REM), - .DRIFT_RATE(PTP_CLK_PERIOD_NS_DENOM), - .PIPELINE_OUTPUT(PTP_CLOCK_PIPELINE) +ptp_td_phc #( + .PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM) ) -ptp_clock_inst ( +ptp_td_phc_inst ( .clk(ptp_clk), .rst(ptp_rst), /* - * Timestamp inputs for synchronization + * ToD timestamp control */ - .input_ts_96(set_ptp_ts_96_reg), - .input_ts_96_valid(set_ptp_ts_96_valid_sync_2_reg ^ set_ptp_ts_96_valid_sync_3_reg), - .input_ts_64(0), - .input_ts_64_valid(1'b0), + .input_ts_tod_s(set_ptp_ts_tod_s_reg), + .input_ts_tod_ns(set_ptp_ts_tod_ns_reg), + .input_ts_tod_valid(set_ptp_ts_tod_valid_reg), + .input_ts_tod_ready(set_ptp_ts_tod_ready), + .input_ts_tod_offset_ns(offset_ptp_ts_tod_ns_reg), + .input_ts_tod_offset_valid(offset_ptp_ts_tod_valid_reg), + .input_ts_tod_offset_ready(offset_ptp_ts_tod_ready), /* - * Period adjustment + * Relative timestamp control */ - .input_period_ns(set_ptp_period_ns_reg), - .input_period_fns(set_ptp_period_fns_reg), - .input_period_valid(set_ptp_period_valid_sync_2_reg ^ set_ptp_period_valid_sync_3_reg), + .input_ts_rel_ns(set_ptp_ts_rel_ns_reg), + .input_ts_rel_valid(set_ptp_ts_rel_valid_reg), + .input_ts_rel_ready(set_ptp_ts_rel_ready), + .input_ts_rel_offset_ns(offset_ptp_ts_rel_ns_reg), + .input_ts_rel_offset_valid(offset_ptp_ts_rel_valid_reg), + .input_ts_rel_offset_ready(offset_ptp_ts_rel_ready), /* - * Offset adjustment + * Fractional ns control */ - .input_adj_ns(set_ptp_offset_ns_reg), - .input_adj_fns(set_ptp_offset_fns_reg), - .input_adj_count(set_ptp_offset_count_reg), - .input_adj_valid(set_ptp_offset_valid_sync_2_reg ^ set_ptp_offset_valid_sync_3_reg), - // .input_adj_active(set_ptp_offset_active), + .input_ts_offset_fns(offset_ptp_ts_fns_reg), + .input_ts_offset_valid(offset_ptp_ts_valid_reg), + .input_ts_offset_ready(offset_ptp_ts_ready), /* - * Drift adjustment + * Period control */ - .input_drift_ns(0), - .input_drift_fns(0), - .input_drift_rate(0), - .input_drift_valid(0), + .input_period_ns(set_ptp_period_ns_reg), + .input_period_fns(set_ptp_period_fns_reg), + .input_period_valid(set_ptp_period_valid_reg), + .input_period_ready(set_ptp_period_ready), + .input_drift_num(0), + .input_drift_denom(0), + .input_drift_valid(1'b0), + .input_drift_ready(), /* - * Timestamp outputs + * Time distribution serial data output */ - .output_ts_96(ptp_ts_96), - .output_ts_64(), - .output_ts_step(ptp_ts_step), + .ptp_td_sdo(ptp_td_sd), /* * PPS output */ - .output_pps(ptp_pps) + .output_pps(ptp_pps), + .output_pps_str(ptp_pps_str) ); -// stretched PPS output -localparam PPS_CNT_PERIOD = (64'd500_000_000*PTP_CLK_PERIOD_NS_DENOM)/PTP_CLK_PERIOD_NS_NUM; - -reg [$clog2(PPS_CNT_PERIOD)-1:0] pps_counter_reg = 0; -reg pps_str_reg = 0; - -always @(posedge ptp_clk) begin - pps_str_reg <= 1'b0; - - if (ptp_pps) begin - pps_counter_reg <= PPS_CNT_PERIOD; - pps_str_reg <= 1'b1; - end else if (pps_counter_reg > 0) begin - pps_counter_reg <= pps_counter_reg - 1; - pps_str_reg <= 1'b1; - end -end - -assign ptp_pps_str = pps_str_reg; - // sync to core clock domain -ptp_clock_cdc #( - .TS_WIDTH(96), - .NS_WIDTH(PTP_PERIOD_NS_WIDTH), - .PIPELINE_OUTPUT(PTP_CLOCK_CDC_PIPELINE) +ptp_td_leaf #( + .TS_REL_EN(1), + .TS_TOD_EN(1), + .TS_FNS_W(16), + .TS_REL_NS_W(48), + .TS_TOD_S_W(48), + .TS_REL_W(64), + .TS_TOD_W(96), + .TD_SDI_PIPELINE(PTP_CLOCK_CDC_PIPELINE) ) -ptp_cdc_inst ( - .input_clk(ptp_clk), - .input_rst(ptp_rst), - .output_clk(clk), - .output_rst(rst), +ptp_td_leaf_inst ( + .clk(clk), + .rst(rst), .sample_clk(ptp_sample_clk), - .input_ts(ptp_ts_96), - .input_ts_step(ptp_ts_step), - .output_ts(ptp_sync_ts_96), - .output_ts_step(ptp_sync_ts_step), + + /* + * PTP clock interface + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_td_sdi(ptp_td_sd), + + /* + * Timestamp output + */ + .output_ts_rel(ptp_sync_ts_rel), + .output_ts_rel_step(ptp_sync_ts_rel_step), + .output_ts_tod(ptp_sync_ts_tod), + .output_ts_tod_step(ptp_sync_ts_tod_step), + + /* + * PPS output (ToD format only) + */ .output_pps(ptp_sync_pps), - .locked() + .output_pps_str(ptp_sync_pps_str), + + /* + * Status + */ + .locked(ptp_sync_locked) ); endmodule diff --git a/fpga/common/syn/vivado/mqnic_ptp_clock.tcl b/fpga/common/syn/vivado/mqnic_ptp_clock.tcl index dfed327de..2db5d4112 100644 --- a/fpga/common/syn/vivado/mqnic_ptp_clock.tcl +++ b/fpga/common/syn/vivado/mqnic_ptp_clock.tcl @@ -6,31 +6,45 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_ptp_clock || REF_NAME == mqnic_ptp_clock)}] { puts "Inserting timing constraints for mqnic_ptp_clock instance $inst" - set src_clk [get_clocks -of_objects [get_cells "$inst/set_ptp_ts_96_valid_reg_reg"]] + set src_clk [get_clocks -of_objects [get_cells "$inst/set_ptp_period_req_reg_reg"]] set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}] - set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_ts_96_valid_sync_\[123\]_reg_reg" -filter "PARENT == $inst"] + set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_ts_tod_(req|ack)_sync\[12\]_reg_reg" -filter "PARENT == $inst"] - set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_inc_reg_reg[*]"] -datapath_only $src_clk_period - set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_inc_reg_reg[*]"] -datapath_only $src_clk_period - set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_ovf_reg_reg[*]"] -datapath_only $src_clk_period - set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_ovf_reg_reg[*]"] -datapath_only $src_clk_period - set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_s_reg_reg[*]"] -datapath_only $src_clk_period - set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_reg_reg[*]"] -datapath_only $src_clk_period - set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_reg_reg[*]"] -datapath_only $src_clk_period - set_max_delay -from [get_cells "$inst/set_ptp_ts_96_valid_reg_reg"] -to [get_cells "$inst/set_ptp_ts_96_valid_sync_1_reg_reg"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/set_ptp_ts_tod_s_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/ts_tod_s_reg_reg[*]"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/set_ptp_ts_tod_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/ts_tod_ns_reg_reg[*]"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/set_ptp_ts_tod_req_reg_reg"] -to [get_cells "$inst/set_ptp_ts_tod_req_sync1_reg_reg"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/set_ptp_ts_tod_ack_reg_reg"] -to [get_cells "$inst/set_ptp_ts_tod_ack_sync1_reg_reg"] -datapath_only $src_clk_period - set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_period_valid_sync_\[123\]_reg_reg" -filter "PARENT == $inst"] + set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/offset_ptp_ts_tod_(req|ack)_sync\[12\]_reg_reg" -filter "PARENT == $inst"] - set_max_delay -from [get_cells "$inst/set_ptp_period_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/period_ns_reg_reg[*]"] -datapath_only $src_clk_period - set_max_delay -from [get_cells "$inst/set_ptp_period_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/period_fns_reg_reg[*]"] -datapath_only $src_clk_period - set_max_delay -from [get_cells "$inst/set_ptp_period_valid_reg_reg"] -to [get_cells "$inst/set_ptp_period_valid_sync_1_reg_reg"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/offset_ptp_ts_tod_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/adder_b_reg_reg[*]"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/offset_ptp_ts_tod_req_reg_reg"] -to [get_cells "$inst/offset_ptp_ts_tod_req_sync1_reg_reg"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/offset_ptp_ts_tod_ack_reg_reg"] -to [get_cells "$inst/offset_ptp_ts_tod_ack_sync1_reg_reg"] -datapath_only $src_clk_period - set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_offset_valid_sync_\[123\]_reg_reg" -filter "PARENT == $inst"] + set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_ts_rel_(req|ack)_sync\[12\]_reg_reg" -filter "PARENT == $inst"] - set_max_delay -from [get_cells "$inst/set_ptp_offset_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_ns_reg_reg[*]"] -datapath_only $src_clk_period - set_max_delay -from [get_cells "$inst/set_ptp_offset_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_fns_reg_reg[*]"] -datapath_only $src_clk_period - set_max_delay -from [get_cells "$inst/set_ptp_offset_count_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_count_reg_reg[*]"] -datapath_only $src_clk_period - set_max_delay -from [get_cells "$inst/set_ptp_offset_valid_reg_reg"] -to [get_cells "$inst/set_ptp_offset_valid_sync_1_reg_reg"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/set_ptp_ts_rel_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/ts_rel_ns_reg_reg[*]"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/set_ptp_ts_rel_req_reg_reg"] -to [get_cells "$inst/set_ptp_ts_rel_req_sync1_reg_reg"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/set_ptp_ts_rel_ack_reg_reg"] -to [get_cells "$inst/set_ptp_ts_rel_ack_sync1_reg_reg"] -datapath_only $src_clk_period + + set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/offset_ptp_ts_rel_(req|ack)_sync\[12\]_reg_reg" -filter "PARENT == $inst"] + + set_max_delay -from [get_cells "$inst/offset_ptp_ts_rel_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/adder_b_reg_reg[*]"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/offset_ptp_ts_rel_req_reg_reg"] -to [get_cells "$inst/offset_ptp_ts_rel_req_sync1_reg_reg"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/offset_ptp_ts_rel_ack_reg_reg"] -to [get_cells "$inst/offset_ptp_ts_rel_ack_sync1_reg_reg"] -datapath_only $src_clk_period + + set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_period_(req|ack)_sync\[12\]_reg_reg" -filter "PARENT == $inst"] + + set_max_delay -from [get_cells "$inst/set_ptp_period_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/period_ns_reg_reg[*]"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/set_ptp_period_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/period_fns_reg_reg[*]"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/set_ptp_period_req_reg_reg"] -to [get_cells "$inst/set_ptp_period_req_sync1_reg_reg"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/set_ptp_period_ack_reg_reg"] -to [get_cells "$inst/set_ptp_period_ack_sync1_reg_reg"] -datapath_only $src_clk_period + + set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/offset_ptp_ts_(req|ack)_sync\[12\]_reg_reg" -filter "PARENT == $inst"] + + set_max_delay -from [get_cells "$inst/offset_ptp_ts_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_td_phc_inst/adder_b_reg_reg[*]"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/offset_ptp_ts_req_reg_reg"] -to [get_cells "$inst/offset_ptp_ts_req_sync1_reg_reg"] -datapath_only $src_clk_period + set_max_delay -from [get_cells "$inst/offset_ptp_ts_ack_reg_reg"] -to [get_cells "$inst/offset_ptp_ts_ack_sync1_reg_reg"] -datapath_only $src_clk_period } diff --git a/fpga/common/tb/mqnic.py b/fpga/common/tb/mqnic.py index 4e8bec389..ce6755bdd 100644 --- a/fpga/common/tb/mqnic.py +++ b/fpga/common/tb/mqnic.py @@ -85,29 +85,37 @@ MQNIC_RB_CLK_INFO_CLK_FREQ = 0x1C MQNIC_RB_CLK_INFO_FREQ_BASE = 0x20 -MQNIC_RB_PHC_TYPE = 0x0000C080 -MQNIC_RB_PHC_VER = 0x00000100 -MQNIC_RB_PHC_REG_CTRL = 0x0C -MQNIC_RB_PHC_REG_CUR_FNS = 0x10 -MQNIC_RB_PHC_REG_CUR_NS = 0x14 -MQNIC_RB_PHC_REG_CUR_SEC_L = 0x18 -MQNIC_RB_PHC_REG_CUR_SEC_H = 0x1C -MQNIC_RB_PHC_REG_GET_FNS = 0x20 -MQNIC_RB_PHC_REG_GET_NS = 0x24 -MQNIC_RB_PHC_REG_GET_SEC_L = 0x28 -MQNIC_RB_PHC_REG_GET_SEC_H = 0x2C -MQNIC_RB_PHC_REG_SET_FNS = 0x30 -MQNIC_RB_PHC_REG_SET_NS = 0x34 -MQNIC_RB_PHC_REG_SET_SEC_L = 0x38 -MQNIC_RB_PHC_REG_SET_SEC_H = 0x3C -MQNIC_RB_PHC_REG_PERIOD_FNS = 0x40 -MQNIC_RB_PHC_REG_PERIOD_NS = 0x44 -MQNIC_RB_PHC_REG_NOM_PERIOD_FNS = 0x48 -MQNIC_RB_PHC_REG_NOM_PERIOD_NS = 0x4C -MQNIC_RB_PHC_REG_ADJ_FNS = 0x50 -MQNIC_RB_PHC_REG_ADJ_NS = 0x54 -MQNIC_RB_PHC_REG_ADJ_COUNT = 0x58 -MQNIC_RB_PHC_REG_ADJ_ACTIVE = 0x5C +MQNIC_RB_PHC_TYPE = 0x0000C080 +MQNIC_RB_PHC_VER = 0x00000200 +MQNIC_RB_PHC_REG_CTRL = 0x0C +MQNIC_RB_PHC_REG_CUR_FNS = 0x10 +MQNIC_RB_PHC_REG_CUR_TOD_NS = 0x14 +MQNIC_RB_PHC_REG_CUR_TOD_SEC_L = 0x18 +MQNIC_RB_PHC_REG_CUR_TOD_SEC_H = 0x1C +MQNIC_RB_PHC_REG_CUR_REL_NS_L = 0x20 +MQNIC_RB_PHC_REG_CUR_REL_NS_H = 0x24 +MQNIC_RB_PHC_REG_CUR_PTM_NS_L = 0x28 +MQNIC_RB_PHC_REG_CUR_PTM_NS_H = 0x2C +MQNIC_RB_PHC_REG_SNAP_FNS = 0x30 +MQNIC_RB_PHC_REG_SNAP_TOD_NS = 0x34 +MQNIC_RB_PHC_REG_SNAP_TOD_SEC_L = 0x38 +MQNIC_RB_PHC_REG_SNAP_TOD_SEC_H = 0x3C +MQNIC_RB_PHC_REG_SNAP_REL_NS_L = 0x40 +MQNIC_RB_PHC_REG_SNAP_REL_NS_H = 0x44 +MQNIC_RB_PHC_REG_SNAP_PTM_NS_L = 0x48 +MQNIC_RB_PHC_REG_SNAP_PTM_NS_H = 0x4C +MQNIC_RB_PHC_REG_OFFSET_TOD_NS = 0x50 +MQNIC_RB_PHC_REG_SET_TOD_NS = 0x54 +MQNIC_RB_PHC_REG_SET_TOD_SEC_L = 0x58 +MQNIC_RB_PHC_REG_SET_TOD_SEC_H = 0x5C +MQNIC_RB_PHC_REG_SET_REL_NS_L = 0x60 +MQNIC_RB_PHC_REG_SET_REL_NS_H = 0x64 +MQNIC_RB_PHC_REG_OFFSET_REL_NS = 0x68 +MQNIC_RB_PHC_REG_OFFSET_FNS = 0x6C +MQNIC_RB_PHC_REG_NOM_PERIOD_FNS = 0x70 +MQNIC_RB_PHC_REG_NOM_PERIOD_NS = 0x74 +MQNIC_RB_PHC_REG_PERIOD_FNS = 0x78 +MQNIC_RB_PHC_REG_PERIOD_NS = 0x7C MQNIC_RB_PHC_PEROUT_TYPE = 0x0000C081 MQNIC_RB_PHC_PEROUT_VER = 0x00000100 diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile index 49ec5bd01..1e61c1e99 100644 --- a/fpga/common/tb/mqnic_core_axi/Makefile +++ b/fpga/common/tb/mqnic_core_axi/Makefile @@ -56,8 +56,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py index 52efe38be..6de7a638b 100644 --- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py +++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py @@ -90,14 +90,14 @@ def __init__(self, dut): tx_clk=iface.port[k].port_tx_clk, tx_rst=iface.port[k].port_tx_rst, tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"), - tx_ptp_time=iface.port[k].port_tx_ptp_ts_96, + tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod, tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts, tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag, tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid, rx_clk=iface.port[k].port_rx_clk, rx_rst=iface.port[k].port_rx_rst, rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"), - rx_ptp_time=iface.port[k].port_rx_ptp_ts_96, + rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod, ifg=12, speed=eth_speed ) @@ -603,8 +603,8 @@ def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width, os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile index 6161dfcbb..3abd8cb78 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile @@ -57,8 +57,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py index 9e884a131..dae0619e2 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py +++ b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py @@ -286,14 +286,14 @@ def __init__(self, dut, msix_count=32): tx_clk=iface.port[k].port_tx_clk, tx_rst=iface.port[k].port_tx_rst, tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"), - tx_ptp_time=iface.port[k].port_tx_ptp_ts_96, + tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod, tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts, tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag, tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid, rx_clk=iface.port[k].port_rx_clk, rx_rst=iface.port[k].port_rx_rst, rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"), - rx_ptp_time=iface.port[k].port_rx_ptp_ts_96, + rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod, ifg=12, speed=eth_speed ) @@ -805,8 +805,8 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width, os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile index 3c9c59410..b776daa53 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile @@ -57,8 +57,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py index 875895507..93955ad8e 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py +++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py @@ -234,14 +234,14 @@ def __init__(self, dut, msix_count=32): tx_clk=iface.port[k].port_tx_clk, tx_rst=iface.port[k].port_tx_rst, tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"), - tx_ptp_time=iface.port[k].port_tx_ptp_ts_96, + tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod, tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts, tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag, tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid, rx_clk=iface.port[k].port_rx_clk, rx_rst=iface.port[k].port_rx_rst, rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"), - rx_ptp_time=iface.port[k].port_rx_ptp_ts_96, + rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod, ifg=12, speed=eth_speed ) @@ -753,8 +753,8 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile index f0ad846cb..bb983a520 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile @@ -57,8 +57,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 2cc13e192..860688de4 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -308,14 +308,14 @@ def __init__(self, dut, msix_count=32): tx_clk=iface.port[k].port_tx_clk, tx_rst=iface.port[k].port_tx_rst, tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"), - tx_ptp_time=iface.port[k].port_tx_ptp_ts_96, + tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod, tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts, tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag, tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid, rx_clk=iface.port[k].port_rx_clk, rx_rst=iface.port[k].port_rx_rst, rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"), - rx_ptp_time=iface.port[k].port_rx_ptp_ts_96, + rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod, ifg=12, speed=eth_speed ) @@ -827,8 +827,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile index 0b0beefe4..8d707d5b9 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile @@ -59,8 +59,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py index b3b60a0e6..180743179 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py @@ -308,14 +308,14 @@ def __init__(self, dut, msix_count=32): tx_clk=iface.port[k].port_tx_clk, tx_rst=iface.port[k].port_tx_rst, tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"), - tx_ptp_time=iface.port[k].port_tx_ptp_ts_96, + tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod, tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts, tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag, tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid, rx_clk=iface.port[k].port_rx_clk, rx_rst=iface.port[k].port_rx_rst, rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"), - rx_ptp_time=iface.port[k].port_rx_ptp_ts_96, + rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod, ifg=12, speed=eth_speed ) @@ -882,8 +882,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile index 7e4d665c7..412c5be99 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile @@ -57,8 +57,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -115,7 +115,7 @@ XDC_FILES = fpga.xdc XDC_FILES += placement.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile index 532550b68..9236ce876 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile @@ -60,8 +60,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v @@ -125,7 +125,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v index ed252a5c3..2a80d0496 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v @@ -460,13 +460,16 @@ initial begin end // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -767,8 +770,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -794,8 +797,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -899,8 +902,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -926,8 +929,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1262,13 +1265,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1281,8 +1287,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1309,8 +1315,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile index b57188305..22c8a021e 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile @@ -56,8 +56,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py index 093c0c686..a043aa7e8 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -619,8 +619,8 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "stats_dma_latency.v"), os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile index 54894f575..a554ed95a 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -134,7 +134,7 @@ XDC_FILES = fpga.xdc XDC_FILES += placement.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile index 54894f575..a554ed95a 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -134,7 +134,7 @@ XDC_FILES = fpga.xdc XDC_FILES += placement.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v index 234bf33ed..9e7d09360 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v @@ -507,13 +507,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -855,8 +858,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -888,8 +891,8 @@ assign led[3] = ptp_pps_str; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -913,8 +916,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1049,8 +1052,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1466,13 +1469,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1485,8 +1491,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1513,8 +1519,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile index 9305162ed..cb1c6d148 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile @@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py index 56f79576e..e9608bf26 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -635,8 +635,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile b/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile index 4a079b871..9f3d57b99 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile @@ -74,8 +74,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile index ef69d548f..7953d0bbe 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile @@ -74,8 +74,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v index 053be6d54..11ad017bc 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v @@ -461,13 +461,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -662,8 +665,8 @@ assign led_qsfp[3] = 1'b1; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -687,8 +690,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -823,8 +826,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1165,13 +1168,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1184,8 +1190,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1212,8 +1218,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile index 1e0b2137d..84aaf6a89 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile @@ -65,8 +65,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py index c67f9eff5..b657b1f9a 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -543,8 +543,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile index 01a3f83f1..cdd5edff6 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += rtl/common/i2c_single_reg.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -118,7 +118,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile index 9cec173d5..680e8ccb6 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile @@ -62,8 +62,8 @@ SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v @@ -128,7 +128,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile index 2849c0a34..36af63381 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile @@ -61,8 +61,8 @@ SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += rtl/common/i2c_single_reg.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -120,7 +120,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index 96b15dce4..79f7abbbe 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -467,13 +467,16 @@ initial begin end // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -857,8 +860,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -884,8 +887,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -989,8 +992,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -1016,8 +1019,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1352,13 +1355,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1371,8 +1377,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1399,8 +1405,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile index da4c9bb32..60b02e6f9 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile @@ -57,8 +57,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v VERILOG_SOURCES += ../../rtl/common/i2c_single_reg.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py index 38dc2d30a..4922f0ca5 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -622,8 +622,8 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), os.path.join(rtl_dir, "common", "i2c_single_reg.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index 689393774..e2e88c7be 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -78,8 +78,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -137,7 +137,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile index 689393774..e2e88c7be 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile @@ -78,8 +78,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -137,7 +137,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile index 557016e18..03e9df753 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile @@ -79,8 +79,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -138,7 +138,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 92ff9bf1e..fc5517e70 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -520,13 +520,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -947,8 +950,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -983,8 +986,8 @@ assign front_led[1] = 1'b0; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -1008,8 +1011,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1144,8 +1147,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1561,13 +1564,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1580,8 +1586,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1608,8 +1614,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index 84a7dbc3c..afd5780c7 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -68,8 +68,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index a33e16d22..49b2987c3 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -638,8 +638,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_AU200/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_AU200/Makefile index 0e8ee0bda..dd4d524fc 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_AU200/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_AU200/Makefile @@ -58,8 +58,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_cdc.v SYN_FILES += lib/axi/rtl/axil_cdc_rd.v @@ -122,7 +122,7 @@ XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/Makefile index a2342a13b..e71b9a4e2 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/Makefile @@ -61,8 +61,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v @@ -132,7 +132,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_AU250/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_AU250/Makefile index 31887df11..2c62771be 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_AU250/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_AU250/Makefile @@ -58,8 +58,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_cdc.v SYN_FILES += lib/axi/rtl/axil_cdc_rd.v @@ -122,7 +122,7 @@ XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/Makefile index 6df9dc60b..f8e9cdc92 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/Makefile @@ -61,8 +61,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v @@ -132,7 +132,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/Makefile index 1757b983f..1e2590bad 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/Makefile @@ -58,8 +58,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -118,7 +118,7 @@ XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile index 21e8e675e..c99698d06 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile @@ -61,8 +61,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v @@ -128,7 +128,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index a06377c97..141ad5b6c 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -487,13 +487,16 @@ initial begin end // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -847,8 +850,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -874,8 +877,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -979,8 +982,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -1006,8 +1009,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1342,13 +1345,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1361,8 +1367,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1389,8 +1395,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile index 972993f64..dfa809ebf 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile @@ -56,8 +56,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py index 613555323..5e1e67e99 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -619,8 +619,8 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "stats_dma_latency.v"), os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_AU200/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_AU200/Makefile index dc7930da4..43fbeb4e2 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_AU200/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_AU200/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_cdc.v SYN_FILES += lib/axi/rtl/axil_cdc_rd.v @@ -141,7 +141,7 @@ XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/Makefile index dc7930da4..43fbeb4e2 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_cdc.v SYN_FILES += lib/axi/rtl/axil_cdc_rd.v @@ -141,7 +141,7 @@ XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_AU250/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_AU250/Makefile index 80eee5316..68e4d5b0f 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_AU250/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_AU250/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_cdc.v SYN_FILES += lib/axi/rtl/axil_cdc_rd.v @@ -141,7 +141,7 @@ XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/Makefile index 80eee5316..68e4d5b0f 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_cdc.v SYN_FILES += lib/axi/rtl/axil_cdc_rd.v @@ -141,7 +141,7 @@ XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/Makefile index 148471b46..4b2572738 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -137,7 +137,7 @@ XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/Makefile index 148471b46..4b2572738 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -137,7 +137,7 @@ XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v index 255995400..54ab880fb 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v @@ -532,13 +532,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -933,8 +936,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -966,8 +969,8 @@ assign led[2:1] = 0; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -991,8 +994,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1127,8 +1130,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1544,13 +1547,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1563,8 +1569,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1591,8 +1597,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile index a480035a9..d65dea17f 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile @@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py index 51914360e..f65c69d52 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -635,8 +635,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile index 9c1307ca7..830a8fe98 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile @@ -57,8 +57,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_cdc.v SYN_FILES += lib/axi/rtl/axil_cdc_rd.v @@ -120,7 +120,7 @@ XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile index aad7c2458..e8df59f39 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile @@ -60,8 +60,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v @@ -130,7 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v index e8aca3492..3013e7dd2 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -510,13 +510,16 @@ initial begin end // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -787,8 +790,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -814,8 +817,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -919,8 +922,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -946,8 +949,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1297,13 +1300,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1316,8 +1322,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1344,8 +1350,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile index f60a01ceb..eb8ef55cb 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile @@ -56,8 +56,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py index 7a50609ad..94109b468 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -611,8 +611,8 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "stats_dma_latency.v"), os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile index f838d19e0..a934f426e 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_cdc.v SYN_FILES += lib/axi/rtl/axil_cdc_rd.v @@ -139,7 +139,7 @@ XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile index f838d19e0..a934f426e 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_cdc.v SYN_FILES += lib/axi/rtl/axil_cdc_rd.v @@ -139,7 +139,7 @@ XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v index 5f1e04f27..450b1cc82 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v @@ -557,13 +557,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -878,8 +881,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -908,8 +911,8 @@ endgenerate wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -933,8 +936,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1069,8 +1072,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1501,13 +1504,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1520,8 +1526,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1548,8 +1554,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile index 50f7c51ea..299f0919d 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile @@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py index 6f10a3ca1..3cbb9cbdb 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -627,8 +627,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile index 82c64dd61..8ae9e12af 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile @@ -57,8 +57,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_cdc.v SYN_FILES += lib/axi/rtl/axil_cdc_rd.v @@ -120,7 +120,7 @@ XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile index b34764073..266db2e1a 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile @@ -60,8 +60,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v @@ -130,7 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v index 59a75879a..46846e17c 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v @@ -412,13 +412,16 @@ initial begin end // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -645,8 +648,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -672,8 +675,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -773,8 +776,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -800,8 +803,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1136,13 +1139,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1155,8 +1161,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1183,8 +1189,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile index ecc319484..ee2f891f3 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile @@ -56,8 +56,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py index 8b7301e34..453dc9a82 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -589,8 +589,8 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "stats_dma_latency.v"), os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile index 62da8db25..7564ec95e 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_cdc.v SYN_FILES += lib/axi/rtl/axil_cdc_rd.v @@ -139,7 +139,7 @@ XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile index 62da8db25..7564ec95e 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_cdc.v SYN_FILES += lib/axi/rtl/axil_cdc_rd.v @@ -139,7 +139,7 @@ XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v index 3a4ce9817..6ed0e18ee 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v @@ -451,13 +451,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -724,8 +727,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -750,8 +753,8 @@ assign qsfp_led_stat_y = 1'b0; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -775,8 +778,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -911,8 +914,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1328,13 +1331,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1347,8 +1353,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1375,8 +1381,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile index 14b9e4f45..3148af484 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile @@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py index f9b1835d9..31fea2759 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -605,8 +605,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/Makefile index 483a79be5..b8a5b8c8d 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/avst2axis.v SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile index 835e28189..ec83d94ee 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/avst2axis.v SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/Makefile index 3e0d54a03..f06e301c9 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench/Makefile @@ -61,8 +61,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/Makefile index 0a8e5f09e..c7ec69f5b 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_app_dma_bench_24AR0/Makefile @@ -61,8 +61,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v index 3f56b77a4..c2ee3b551 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v @@ -390,13 +390,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -589,8 +592,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -611,8 +614,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -699,8 +702,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -721,8 +724,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -978,13 +981,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -997,8 +1003,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1019,8 +1025,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile index e650a2c05..1aeddaa64 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile @@ -61,8 +61,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py index 7655e7f3f..a8a23107a 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -599,8 +599,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/Makefile index 9d0ab25fe..6ca79e59a 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/avst2axis.v SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/Makefile index 242375af0..af30819a5 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/avst2axis.v SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile index 463b39b4c..edc8a89ab 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/avst2axis.v SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile index 1e7027303..6152b1179 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/avst2axis.v SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v index ac1c5ed66..7ec84e90a 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v @@ -896,13 +896,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -1095,8 +1098,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -1122,8 +1125,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1217,8 +1220,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -1244,8 +1247,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1508,13 +1511,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1527,8 +1533,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1555,8 +1561,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile index 61cd4be5c..01b04245f 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile @@ -61,8 +61,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py index 32a85ff0e..3f394f9ae 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -583,8 +583,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/Makefile index 647453687..8e28b24af 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/Makefile @@ -58,8 +58,8 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/Makefile index f7f8e67d1..a61d0d3c7 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/Makefile @@ -60,8 +60,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v index 6118247da..af8321121 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v @@ -315,13 +315,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -420,8 +423,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -447,8 +450,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -542,8 +545,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -569,8 +572,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -827,13 +830,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -846,8 +852,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -874,8 +880,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile index bfcf723d5..24de73e3d 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile @@ -58,8 +58,8 @@ VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v VERILOG_SOURCES += ../../rtl/common/tdma_ber.v VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py index 7595b64eb..a3288c09f 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -583,8 +583,8 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "tdma_ber.v"), os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/Makefile index eb933f0e4..0f79736a7 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/Makefile @@ -58,8 +58,8 @@ SYN_FILES += rtl/common/avst2axis.v SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/Makefile index 16aba8a39..c8f691bd2 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/Makefile @@ -58,8 +58,8 @@ SYN_FILES += rtl/common/avst2axis.v SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v index 3712ceb5a..57dca4033 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v @@ -569,13 +569,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -674,8 +677,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -701,8 +704,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -796,8 +799,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -823,8 +826,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1085,13 +1088,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1104,8 +1110,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1132,8 +1138,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile index 69f6ba408..593962e07 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile @@ -58,8 +58,8 @@ VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v VERILOG_SOURCES += ../../rtl/common/tdma_ber.v VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py index 0eb16809c..5da409d42 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -575,8 +575,8 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "tdma_ber.v"), os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile index bd0055029..09be81c3d 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile @@ -75,8 +75,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile index 2016af126..7b67aef7e 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile @@ -75,8 +75,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile index 7bedb94b0..decffc1cb 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile @@ -75,8 +75,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile index bddf86ff1..c2b81a7e5 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile @@ -75,8 +75,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v index 8a7abee1e..b9bb75029 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v @@ -368,13 +368,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -593,8 +596,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -628,8 +631,8 @@ assign user_led[3] = ptp_pps_str; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -653,8 +656,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -789,8 +792,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1131,13 +1134,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1150,8 +1156,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1178,8 +1184,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile index 5a237ee25..a05e1928a 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile @@ -66,8 +66,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py index fb17b4d55..c0b6a96f6 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -546,8 +546,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/Makefile index 9ca85eee1..d0a9eba6e 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/Makefile index ec8821ad6..c9d53b6d5 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/Makefile index 28b7e1ed9..e095779e0 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/Makefile @@ -61,8 +61,8 @@ SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/Makefile index 5d41ad690..ff92a0d2d 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/Makefile @@ -61,8 +61,8 @@ SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v index c75259ed4..d410afc28 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v @@ -396,13 +396,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -620,8 +623,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -647,8 +650,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -742,8 +745,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -769,8 +772,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1033,13 +1036,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1052,8 +1058,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1080,8 +1086,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile index 7f3500b1c..662453415 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile @@ -62,8 +62,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py index e119c7a4c..6e31afe88 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -599,8 +599,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/Makefile index b4e56ffab..d47ee38ab 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/Makefile index 67cc5ad64..3b3110145 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/Makefile index bcde5365a..17adc6057 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/Makefile index 9edeffce7..fd39a4824 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/axis2avst.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v index 877de12a1..28c919996 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v @@ -902,13 +902,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -1126,8 +1129,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -1153,8 +1156,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1248,8 +1251,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -1275,8 +1278,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1539,13 +1542,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1558,8 +1564,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1586,8 +1592,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile index fd610d330..68283d2e5 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile @@ -62,8 +62,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py index 21509236f..305016f16 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -583,8 +583,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile index 1ce6d0bc4..9582eaa28 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile @@ -79,8 +79,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v @@ -143,7 +143,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile index c99f209cd..2b6034609 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile @@ -79,8 +79,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v @@ -143,7 +143,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile index 4e90ae131..abc85c845 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -134,7 +134,7 @@ XDC_FILES = fpga.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile index 5eafd72d2..dda35c0a6 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -134,7 +134,7 @@ XDC_FILES = fpga.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v index 4077b52e9..ee2846c9d 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v @@ -521,13 +521,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -946,8 +949,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -984,8 +987,8 @@ assign qsfp1_leg_red = 1'b0; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -1009,8 +1012,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1145,8 +1148,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1562,13 +1565,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1581,8 +1587,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1609,8 +1615,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile index 1bf4c8ee5..94c19b6c1 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile @@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py index bdeae2d79..aecf8bc5c 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py @@ -595,8 +595,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/KR260/fpga/fpga/Makefile b/fpga/mqnic/KR260/fpga/fpga/Makefile index 9d3e5f72d..46557cca4 100644 --- a/fpga/mqnic/KR260/fpga/fpga/Makefile +++ b/fpga/mqnic/KR260/fpga/fpga/Makefile @@ -73,8 +73,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -116,7 +116,7 @@ SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v XDC_FILES = fpga.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/Makefile b/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/Makefile index 7fdf57888..664d1bcca 100644 --- a/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v @@ -125,7 +125,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/KR260/fpga/rtl/fpga_core.v b/fpga/mqnic/KR260/fpga/rtl/fpga_core.v index f8f0a74cd..8d51e6108 100644 --- a/fpga/mqnic/KR260/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/KR260/fpga/rtl/fpga_core.v @@ -338,13 +338,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -552,8 +555,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -573,8 +576,8 @@ assign sfp_led = 0; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -598,8 +601,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -734,8 +737,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1116,13 +1119,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1135,8 +1141,8 @@ core_inst ( .tx_ptp_clk(0), .tx_ptp_rst(0), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_tx_tdata(axis_eth_tx_tdata), .m_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -1163,8 +1169,8 @@ core_inst ( .rx_ptp_clk(0), .rx_ptp_rst(0), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_rx_tdata(axis_eth_rx_tdata), .s_axis_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile b/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile index bfcde4236..c084dc402 100644 --- a/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile @@ -64,8 +64,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py index 79b9bbc07..78bf0da1f 100644 --- a/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py @@ -376,8 +376,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile index 4532cb5cc..b47310da0 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile @@ -74,8 +74,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -132,7 +132,7 @@ XDC_FILES = fpga.xdc XDC_FILES += pcie.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/Makefile index bae621a35..6bb79c060 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -134,7 +134,7 @@ XDC_FILES = fpga.xdc XDC_FILES += pcie.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v index f1b60a111..04a82c279 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -346,13 +346,16 @@ initial begin end // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -530,8 +533,8 @@ assign led[1] = 1'b0; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -555,8 +558,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -691,8 +694,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1093,13 +1096,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1112,8 +1118,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1140,8 +1146,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile index 3bc0dcfed..a9034a783 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile @@ -65,8 +65,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py index cb0daa267..7dd1aac51 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py @@ -585,8 +585,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile index b2b1a9151..1a25421f7 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -134,7 +134,7 @@ XDC_FILES = fpga.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/Makefile index 828250a71..21796aa08 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga_app_dma_bench/Makefile @@ -78,8 +78,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -136,7 +136,7 @@ XDC_FILES = fpga.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v index 8cd9a1839..dd617e276 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v @@ -348,13 +348,16 @@ initial begin end // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -705,8 +708,8 @@ assign sma_led[1] = 1'b0; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -730,8 +733,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -866,8 +869,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1268,13 +1271,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1287,8 +1293,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1315,8 +1321,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile index 70b04c775..259148750 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile @@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py index f98411eb2..6dc8d25d2 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py @@ -600,8 +600,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile index 031011057..4c2d8f39b 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -134,7 +134,7 @@ XDC_FILES = fpga.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile index 031011057..4c2d8f39b 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -134,7 +134,7 @@ XDC_FILES = fpga.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile index ff04ea793..446dc2c3b 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile @@ -79,8 +79,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v @@ -143,7 +143,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v index 9be1c3a87..cd0d0d9c8 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v @@ -527,13 +527,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -978,8 +981,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -1019,8 +1022,8 @@ assign sma_led_red = 1'b0; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -1044,8 +1047,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1180,8 +1183,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1597,13 +1600,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1616,8 +1622,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1644,8 +1650,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile index 07858540c..a1bfde8ea 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile @@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py index 4dc1e156e..6c7b704e0 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -635,8 +635,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile index 8c64e22e1..7922138d4 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -135,7 +135,7 @@ XDC_FILES = fpga.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile index 8c64e22e1..7922138d4 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -135,7 +135,7 @@ XDC_FILES = fpga.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/Makefile index 5f14795cb..3960a210a 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/Makefile @@ -79,8 +79,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -137,7 +137,7 @@ XDC_FILES = fpga.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v index 282eeda08..489ad15bb 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v @@ -383,13 +383,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -803,8 +806,8 @@ assign sma_led[1] = 1'b0; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -828,8 +831,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -964,8 +967,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1366,13 +1369,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1385,8 +1391,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1413,8 +1419,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile index 6f12f5773..092854fea 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile @@ -68,8 +68,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py index 8c785e102..efb68a976 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -628,8 +628,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile index a0c586685..f29e4dc46 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -136,7 +136,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile index a0c586685..f29e4dc46 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -136,7 +136,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile index e2953b626..e79c92116 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile @@ -80,8 +80,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v @@ -145,7 +145,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v index 191e4af25..394b075e4 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v @@ -448,13 +448,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -760,8 +763,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -790,8 +793,8 @@ assign led[7] = ptp_pps_str; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -815,8 +818,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -951,8 +954,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1368,13 +1371,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1387,8 +1393,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1415,8 +1421,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile index b73274d19..04594ed04 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile @@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py index 1df9e424d..ad82de85a 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -592,8 +592,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile index da12d2620..858de987f 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile @@ -58,8 +58,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -117,7 +117,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile index 5bb1362c7..69056d2a2 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile @@ -61,8 +61,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v @@ -127,7 +127,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v index 8f17b1971..48a5dc18c 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v @@ -470,13 +470,16 @@ initial begin end // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -812,8 +815,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -839,8 +842,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -944,8 +947,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -971,8 +974,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1307,13 +1310,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1326,8 +1332,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1354,8 +1360,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile index da31ede71..13b67290b 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile @@ -56,8 +56,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py index af5581be8..6c6370ecb 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -623,8 +623,8 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "stats_dma_latency.v"), os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile index df9c38a71..ce521f3b4 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -136,7 +136,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile index df9c38a71..ce521f3b4 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -136,7 +136,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v index b5731f462..9cadc5ba7 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v @@ -517,13 +517,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -895,8 +898,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -933,8 +936,8 @@ assign led[7] = ptp_pps_str; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -958,8 +961,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1094,8 +1097,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1511,13 +1514,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1530,8 +1536,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1558,8 +1564,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile index da5012058..6b2d41be9 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile @@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py index b11789151..76837f0a5 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -639,8 +639,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile index 430ac218f..8401a7a4f 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile @@ -57,8 +57,8 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -116,7 +116,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile index d4bd67a4c..169be442c 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile @@ -60,8 +60,8 @@ SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v @@ -126,7 +126,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v index 164187e9c..dfbcaa866 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v @@ -598,13 +598,16 @@ initial begin end // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -1155,8 +1158,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -1182,8 +1185,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1295,8 +1298,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -1322,8 +1325,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1658,13 +1661,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1677,8 +1683,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1705,8 +1711,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile index c37a5c157..e591f8aef 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile @@ -56,8 +56,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py index 2e8bd1140..83f32d151 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -619,8 +619,8 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "stats_dma_latency.v"), os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile index b01a601ba..eb5c63c05 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -135,7 +135,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile index b01a601ba..eb5c63c05 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -135,7 +135,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v index 3cbee0799..ed22b33b6 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v @@ -661,13 +661,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -1259,8 +1262,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -1308,8 +1311,8 @@ assign led[3] = !ptp_pps_str; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -1333,8 +1336,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1469,8 +1472,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1886,13 +1889,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1905,8 +1911,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1933,8 +1939,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile index 05782ff97..411bd9e95 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile @@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py index 407acccbe..71b3a70b5 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -636,8 +636,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga/Makefile b/fpga/mqnic/XUSP3S/fpga_25g/fpga/Makefile index c866d921b..9d457dc70 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -135,7 +135,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/Makefile index c866d921b..9d457dc70 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga_10g/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -135,7 +135,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/Makefile index daf9a142e..375c175d5 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/XUSP3S/fpga_25g/fpga_app_dma_bench/Makefile @@ -79,8 +79,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v @@ -144,7 +144,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v index c471587d4..be2e46f0a 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v @@ -656,13 +656,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -1254,8 +1257,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -1303,8 +1306,8 @@ assign led[3] = !ptp_pps_str; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -1328,8 +1331,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1464,8 +1467,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1881,13 +1884,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1900,8 +1906,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1928,8 +1934,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile index f76ded620..74cae1598 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/Makefile @@ -67,8 +67,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py index 1c76e0ece..1cfd089ce 100644 --- a/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUSP3S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -610,8 +610,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/ZCU102/fpga/fpga/Makefile b/fpga/mqnic/ZCU102/fpga/fpga/Makefile index 00eb5760b..a11a04848 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/Makefile +++ b/fpga/mqnic/ZCU102/fpga/fpga/Makefile @@ -73,8 +73,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -116,7 +116,7 @@ SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v XDC_FILES = fpga.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile index 45f52e5ab..c492a3992 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v @@ -125,7 +125,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v index c1500d7e8..14f061c88 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v @@ -432,13 +432,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -632,8 +635,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -657,8 +660,8 @@ assign led[7] = ptp_pps_str; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -682,8 +685,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -818,8 +821,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1215,13 +1218,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1234,8 +1240,8 @@ core_inst ( .tx_ptp_clk(0), .tx_ptp_rst(0), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_tx_tdata(axis_eth_tx_tdata), .m_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -1262,8 +1268,8 @@ core_inst ( .rx_ptp_clk(0), .rx_ptp_rst(0), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_rx_tdata(axis_eth_rx_tdata), .s_axis_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile index 6e64c4b78..1f7f63fc1 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile @@ -64,8 +64,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index c3cc4fa2d..0b4e0f62c 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -398,8 +398,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile index 23862a523..4c78c4d73 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile @@ -77,8 +77,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile index f11f4ee60..e095fe6c4 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile @@ -80,8 +80,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v @@ -143,7 +143,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v index b488ddf03..9a50aac22 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v @@ -407,13 +407,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -625,8 +628,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -646,8 +649,8 @@ assign led[7] = ptp_pps_str; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -666,8 +669,8 @@ wire [PORT_COUNT-1:0] eth_tx_status; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -780,8 +783,8 @@ generate .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1112,13 +1115,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1131,8 +1137,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1153,8 +1159,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile index 2c8ac2de8..54d76713e 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile @@ -63,8 +63,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py index 0b55db2d0..043c10680 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py @@ -590,8 +590,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile index d03db2aeb..a6c6f1497 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile @@ -73,8 +73,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -116,7 +116,7 @@ SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v XDC_FILES = fpga.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile index 0580e2859..f5a801543 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile @@ -76,8 +76,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v @@ -125,7 +125,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v index 744837950..cf90eb783 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v @@ -404,13 +404,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -590,8 +593,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -611,8 +614,8 @@ assign led[7] = ptp_pps_str; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -636,8 +639,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -772,8 +775,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1169,13 +1172,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1188,8 +1194,8 @@ core_inst ( .tx_ptp_clk(0), .tx_ptp_rst(0), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_tx_tdata(axis_eth_tx_tdata), .m_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -1216,8 +1222,8 @@ core_inst ( .rx_ptp_clk(0), .rx_ptp_rst(0), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_rx_tdata(axis_eth_rx_tdata), .s_axis_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile index 6e64c4b78..1f7f63fc1 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile @@ -64,8 +64,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py index 96320291b..c2edcc3a3 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py @@ -398,8 +398,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile index 7ba5bfe57..35fbe6c95 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += rtl/common/led_sreg_driver.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -118,7 +118,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile index 30b63b52c..8c2c6e3b5 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile @@ -62,8 +62,8 @@ SYN_FILES += rtl/common/led_sreg_driver.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v @@ -128,7 +128,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile index 954fa976b..38b76d7a9 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile @@ -63,8 +63,8 @@ SYN_FILES += rtl/common/led_sreg_driver.v SYN_FILES += app/template/rtl/mqnic_app_block.v SYN_FILES += lib/axi/rtl/axil_ram.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -122,7 +122,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile index c1774b069..130114bbd 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile @@ -61,8 +61,8 @@ SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += rtl/common/led_sreg_driver.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -120,7 +120,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index 647c268d2..02ba7b3be 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -474,13 +474,16 @@ initial begin end // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -869,8 +872,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -896,8 +899,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1001,8 +1004,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -1028,8 +1031,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1364,13 +1367,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1383,8 +1389,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1411,8 +1417,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile index 389f05eec..91ae8cd00 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile @@ -57,8 +57,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index 7ac2e051e..8cdecfa88 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -620,8 +620,8 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "stats_dma_latency.v"), os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile index 99aff6d08..7366caa0b 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile @@ -78,8 +78,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -137,7 +137,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile index 99aff6d08..7366caa0b 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile @@ -78,8 +78,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -137,7 +137,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile index 087df4441..97089b1b0 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile @@ -79,8 +79,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -138,7 +138,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index 9b633c2a8..360d202cb 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -529,13 +529,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -960,8 +963,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -997,8 +1000,8 @@ assign led_exp[1] = 1'b1; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -1022,8 +1025,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1158,8 +1161,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1575,13 +1578,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1594,8 +1600,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1622,8 +1628,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile index f3a73e6a5..acd127547 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile @@ -68,8 +68,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index 7fc68f42e..33f7fa179 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -636,8 +636,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile b/fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile index a4dfb95ca..45b58ad2a 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile @@ -59,8 +59,8 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v SYN_FILES += rtl/common/led_sreg_driver.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -118,7 +118,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile index fb9513df9..795cc21ef 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile @@ -62,8 +62,8 @@ SYN_FILES += rtl/common/led_sreg_driver.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v @@ -128,7 +128,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v index 3170cf53a..b351bb8c6 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v @@ -591,13 +591,16 @@ initial begin end // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -1122,8 +1125,8 @@ wire [PORT_COUNT-1:0] eth_tx_rst; wire [PORT_COUNT-1:0] eth_tx_ptp_clk; wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -1149,8 +1152,8 @@ wire [PORT_COUNT-1:0] eth_rx_rst; wire [PORT_COUNT-1:0] eth_rx_ptp_clk; wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1262,8 +1265,8 @@ mqnic_port_map_mac_axis_inst ( .tx_ptp_clk(eth_tx_ptp_clk), .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), + .tx_ptp_ts_96(eth_tx_ptp_ts_tod), + .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), .s_axis_tx_tdata(axis_eth_tx_tdata), .s_axis_tx_tkeep(axis_eth_tx_tkeep), @@ -1289,8 +1292,8 @@ mqnic_port_map_mac_axis_inst ( .rx_ptp_clk(eth_rx_ptp_clk), .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), + .rx_ptp_ts_96(eth_rx_ptp_ts_tod), + .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), .m_axis_rx_tdata(axis_eth_rx_tdata), .m_axis_rx_tkeep(axis_eth_rx_tkeep), @@ -1625,13 +1628,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1644,8 +1650,8 @@ core_inst ( .eth_tx_ptp_clk(eth_tx_ptp_clk), .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1672,8 +1678,8 @@ core_inst ( .eth_rx_ptp_clk(eth_rx_ptp_clk), .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile index 413c209cb..14825b959 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile @@ -57,8 +57,8 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py index c3d0f5999..5e53c5df9 100644 --- a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -615,8 +615,8 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "stats_dma_latency.v"), os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile index 4a68f5aba..948d37c77 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile @@ -78,8 +78,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -137,7 +137,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile index 4a68f5aba..948d37c77 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile @@ -78,8 +78,8 @@ SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v SYN_FILES += lib/eth/rtl/lfsr.v -SYN_FILES += lib/eth/rtl/ptp_clock.v -SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_td_phc.v +SYN_FILES += lib/eth/rtl/ptp_td_leaf.v SYN_FILES += lib/eth/rtl/ptp_perout.v SYN_FILES += lib/axi/rtl/axil_interconnect.v SYN_FILES += lib/axi/rtl/axil_crossbar.v @@ -137,7 +137,7 @@ XDC_FILES += placement.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl -XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v index d1c9f867a..123eac716 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v @@ -670,13 +670,16 @@ wire axil_csr_rvalid; wire axil_csr_rready; // PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; +wire ptp_sync_locked; +wire [63:0] ptp_sync_ts_rel; +wire ptp_sync_ts_rel_step; +wire [95:0] ptp_sync_ts_tod; +wire ptp_sync_ts_tod_step; +wire ptp_sync_pps; +wire ptp_sync_pps_str; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; @@ -1235,8 +1238,8 @@ if (TDMA_BER_ENABLE) begin .s_axil_rresp(axil_csr_rresp), .s_axil_rvalid(axil_csr_rvalid), .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step) ); end else begin @@ -1288,8 +1291,8 @@ assign led_bmc_red[1] = 0; wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; @@ -1313,8 +1316,8 @@ wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; wire [PORT_COUNT-1:0] eth_rx_clk; wire [PORT_COUNT-1:0] eth_rx_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; @@ -1449,8 +1452,8 @@ generate /* * PTP */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), @@ -1866,13 +1869,16 @@ core_inst ( .ptp_clk(ptp_clk), .ptp_rst(ptp_rst), .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), .ptp_pps(ptp_pps), .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_sync_pps_str(ptp_sync_pps_str), .ptp_perout_locked(ptp_perout_locked), .ptp_perout_error(ptp_perout_error), .ptp_perout_pulse(ptp_perout_pulse), @@ -1885,8 +1891,8 @@ core_inst ( .eth_tx_ptp_clk(0), .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), + .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), .m_axis_eth_tx_tdata(axis_eth_tx_tdata), .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), @@ -1913,8 +1919,8 @@ core_inst ( .eth_rx_ptp_clk(0), .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), + .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), .s_axis_eth_rx_tdata(axis_eth_rx_tdata), .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile index 4139d303c..1c0b44be1 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile @@ -68,8 +68,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py index a48c95514..67b67cc88 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -633,8 +633,8 @@ def test_fpga_core(request): os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_td_phc.v"), + os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), os.path.join(axi_rtl_dir, "axil_interconnect.v"), os.path.join(axi_rtl_dir, "axil_crossbar.v"), diff --git a/modules/mqnic/mqnic_hw.h b/modules/mqnic/mqnic_hw.h index 05ca11ee5..502771a9c 100644 --- a/modules/mqnic/mqnic_hw.h +++ b/modules/mqnic/mqnic_hw.h @@ -125,29 +125,37 @@ #define MQNIC_RB_CLK_INFO_CLK_FREQ 0x1C #define MQNIC_RB_CLK_INFO_FREQ_BASE 0x20 -#define MQNIC_RB_PHC_TYPE 0x0000C080 -#define MQNIC_RB_PHC_VER 0x00000100 -#define MQNIC_RB_PHC_REG_CTRL 0x0C -#define MQNIC_RB_PHC_REG_CUR_FNS 0x10 -#define MQNIC_RB_PHC_REG_CUR_NS 0x14 -#define MQNIC_RB_PHC_REG_CUR_SEC_L 0x18 -#define MQNIC_RB_PHC_REG_CUR_SEC_H 0x1C -#define MQNIC_RB_PHC_REG_GET_FNS 0x20 -#define MQNIC_RB_PHC_REG_GET_NS 0x24 -#define MQNIC_RB_PHC_REG_GET_SEC_L 0x28 -#define MQNIC_RB_PHC_REG_GET_SEC_H 0x2C -#define MQNIC_RB_PHC_REG_SET_FNS 0x30 -#define MQNIC_RB_PHC_REG_SET_NS 0x34 -#define MQNIC_RB_PHC_REG_SET_SEC_L 0x38 -#define MQNIC_RB_PHC_REG_SET_SEC_H 0x3C -#define MQNIC_RB_PHC_REG_PERIOD_FNS 0x40 -#define MQNIC_RB_PHC_REG_PERIOD_NS 0x44 -#define MQNIC_RB_PHC_REG_NOM_PERIOD_FNS 0x48 -#define MQNIC_RB_PHC_REG_NOM_PERIOD_NS 0x4C -#define MQNIC_RB_PHC_REG_ADJ_FNS 0x50 -#define MQNIC_RB_PHC_REG_ADJ_NS 0x54 -#define MQNIC_RB_PHC_REG_ADJ_COUNT 0x58 -#define MQNIC_RB_PHC_REG_ADJ_ACTIVE 0x5C +#define MQNIC_RB_PHC_TYPE 0x0000C080 +#define MQNIC_RB_PHC_VER 0x00000200 +#define MQNIC_RB_PHC_REG_CTRL 0x0C +#define MQNIC_RB_PHC_REG_CUR_FNS 0x10 +#define MQNIC_RB_PHC_REG_CUR_TOD_NS 0x14 +#define MQNIC_RB_PHC_REG_CUR_TOD_SEC_L 0x18 +#define MQNIC_RB_PHC_REG_CUR_TOD_SEC_H 0x1C +#define MQNIC_RB_PHC_REG_CUR_REL_NS_L 0x20 +#define MQNIC_RB_PHC_REG_CUR_REL_NS_H 0x24 +#define MQNIC_RB_PHC_REG_CUR_PTM_NS_L 0x28 +#define MQNIC_RB_PHC_REG_CUR_PTM_NS_H 0x2C +#define MQNIC_RB_PHC_REG_SNAP_FNS 0x30 +#define MQNIC_RB_PHC_REG_SNAP_TOD_NS 0x34 +#define MQNIC_RB_PHC_REG_SNAP_TOD_SEC_L 0x38 +#define MQNIC_RB_PHC_REG_SNAP_TOD_SEC_H 0x3C +#define MQNIC_RB_PHC_REG_SNAP_REL_NS_L 0x40 +#define MQNIC_RB_PHC_REG_SNAP_REL_NS_H 0x44 +#define MQNIC_RB_PHC_REG_SNAP_PTM_NS_L 0x48 +#define MQNIC_RB_PHC_REG_SNAP_PTM_NS_H 0x4C +#define MQNIC_RB_PHC_REG_OFFSET_TOD_NS 0x50 +#define MQNIC_RB_PHC_REG_SET_TOD_NS 0x54 +#define MQNIC_RB_PHC_REG_SET_TOD_SEC_L 0x58 +#define MQNIC_RB_PHC_REG_SET_TOD_SEC_H 0x5C +#define MQNIC_RB_PHC_REG_SET_REL_NS_L 0x60 +#define MQNIC_RB_PHC_REG_SET_REL_NS_H 0x64 +#define MQNIC_RB_PHC_REG_OFFSET_REL_NS 0x68 +#define MQNIC_RB_PHC_REG_OFFSET_FNS 0x6C +#define MQNIC_RB_PHC_REG_NOM_PERIOD_FNS 0x70 +#define MQNIC_RB_PHC_REG_NOM_PERIOD_NS 0x74 +#define MQNIC_RB_PHC_REG_PERIOD_FNS 0x78 +#define MQNIC_RB_PHC_REG_PERIOD_NS 0x7C #define MQNIC_RB_PHC_PEROUT_TYPE 0x0000C081 #define MQNIC_RB_PHC_PEROUT_VER 0x00000100 diff --git a/modules/mqnic/mqnic_ptp.c b/modules/mqnic/mqnic_ptp.c index 83c66180d..dcf030f36 100644 --- a/modules/mqnic/mqnic_ptp.c +++ b/modules/mqnic/mqnic_ptp.c @@ -15,8 +15,8 @@ ktime_t mqnic_read_cpl_ts(struct mqnic_dev *mdev, struct mqnic_ring *ring, if (unlikely(!ring->ts_valid || (ring->ts_s ^ ts_s) & 0xff00)) { // seconds MSBs do not match, update cached timestamp if (mdev->phc_rb) { - ring->ts_s = ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_CUR_SEC_L); - ring->ts_s |= (u64) ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_CUR_SEC_H) << 32; + ring->ts_s = ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_CUR_TOD_SEC_L); + ring->ts_s |= (u64) ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_CUR_TOD_SEC_H) << 32; ring->ts_valid = 1; } } @@ -65,10 +65,10 @@ static int mqnic_phc_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) { struct mqnic_dev *mdev = container_of(ptp, struct mqnic_dev, ptp_clock_info); - ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_GET_FNS); - ts->tv_nsec = ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_GET_NS); - ts->tv_sec = ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_GET_SEC_L); - ts->tv_sec |= (u64) ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_GET_SEC_H) << 32; + ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SNAP_FNS); + ts->tv_nsec = ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SNAP_TOD_NS); + ts->tv_sec = ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SNAP_TOD_SEC_L); + ts->tv_sec |= (u64) ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SNAP_TOD_SEC_H) << 32; return 0; } @@ -80,11 +80,11 @@ static int mqnic_phc_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, struct mqnic_dev *mdev = container_of(ptp, struct mqnic_dev, ptp_clock_info); ptp_read_system_prets(sts); - ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_GET_FNS); + ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SNAP_FNS); ptp_read_system_postts(sts); - ts->tv_nsec = ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_GET_NS); - ts->tv_sec = ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_GET_SEC_L); - ts->tv_sec |= (u64) ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_GET_SEC_H) << 32; + ts->tv_nsec = ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SNAP_TOD_NS); + ts->tv_sec = ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SNAP_TOD_SEC_L); + ts->tv_sec |= (u64) ioread32(mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SNAP_TOD_SEC_H) << 32; return 0; } @@ -94,10 +94,9 @@ static int mqnic_phc_settime(struct ptp_clock_info *ptp, const struct timespec64 { struct mqnic_dev *mdev = container_of(ptp, struct mqnic_dev, ptp_clock_info); - iowrite32(0, mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SET_FNS); - iowrite32(ts->tv_nsec, mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SET_NS); - iowrite32(ts->tv_sec & 0xffffffff, mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SET_SEC_L); - iowrite32(ts->tv_sec >> 32, mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SET_SEC_H); + iowrite32(ts->tv_nsec, mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SET_TOD_NS); + iowrite32(ts->tv_sec & 0xffffffff, mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SET_TOD_SEC_L); + iowrite32(ts->tv_sec >> 32, mdev->phc_rb->regs + MQNIC_RB_PHC_REG_SET_TOD_SEC_H); return 0; } @@ -109,14 +108,12 @@ static int mqnic_phc_adjtime(struct ptp_clock_info *ptp, s64 delta) dev_dbg(mdev->dev, "%s: delta: %lld", __func__, delta); - if (delta > 1000000000 || delta < -1000000000) { + if (delta > 536000000 || delta < -536000000) { mqnic_phc_gettime(ptp, &ts); ts = timespec64_add(ts, ns_to_timespec64(delta)); mqnic_phc_settime(ptp, &ts); } else { - iowrite32(0, mdev->phc_rb->regs + MQNIC_RB_PHC_REG_ADJ_FNS); - iowrite32(delta & 0xffffffff, mdev->phc_rb->regs + MQNIC_RB_PHC_REG_ADJ_NS); - iowrite32(1, mdev->phc_rb->regs + MQNIC_RB_PHC_REG_ADJ_COUNT); + iowrite32(delta & 0xffffffff, mdev->phc_rb->regs + MQNIC_RB_PHC_REG_OFFSET_TOD_NS); } return 0; diff --git a/utils/mqnic-config.c b/utils/mqnic-config.c index 66877fec8..fa8915a06 100644 --- a/utils/mqnic-config.c +++ b/utils/mqnic-config.c @@ -208,9 +208,9 @@ int main(int argc, char *argv[]) { printf("Configure port TDMA schedule\n"); - ts_now.tv_nsec = mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_NS); - ts_now.tv_sec = mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_SEC_L) + - (((int64_t)mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_SEC_H)) << 32); + ts_now.tv_nsec = mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_TOD_NS); + ts_now.tv_sec = mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_TOD_SEC_L) + + (((int64_t)mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_TOD_SEC_H)) << 32); // normalize start ts_start.tv_sec = start_nsec / NSEC_PER_SEC; diff --git a/utils/mqnic-dump.c b/utils/mqnic-dump.c index 896ffb1be..98c73cae5 100644 --- a/utils/mqnic-dump.c +++ b/utils/mqnic-dump.c @@ -108,9 +108,13 @@ int main(int argc, char *argv[]) uint32_t ns; uint32_t fns; - printf("PHC time: %ld.%09d s\n", mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_SEC_L) + - (((int64_t)mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_SEC_H)) << 32), - mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_NS)); + printf("PHC ctrl: 0x%08x\n", mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CTRL)); + + printf("PHC time (ToD): %ld.%09d s\n", mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_TOD_SEC_L) + + (((int64_t)mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_TOD_SEC_H)) << 32), + mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_TOD_NS)); + printf("PHC time (rel): %ld ns\n", mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_REL_NS_L) + + (((int64_t)mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_CUR_REL_NS_H)) << 32)); ns = mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_PERIOD_NS); fns = mqnic_reg_read32(dev->phc_rb->regs, MQNIC_RB_PHC_REG_PERIOD_FNS);