From a05d1a45509153b81b201319b222db0eaf25c043 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 14 Jan 2024 15:45:38 -0800 Subject: [PATCH 1/4] Rename Arista_7132LB to DCS7132LB Signed-off-by: Alex Forencich --- example/{Arista_7132LB => DCS7132LB}/fpga_25g/README.md | 0 example/{Arista_7132LB => DCS7132LB}/fpga_25g/common/vivado.mk | 0 example/{Arista_7132LB => DCS7132LB}/fpga_25g/fpga.xdc | 0 example/{Arista_7132LB => DCS7132LB}/fpga_25g/fpga/Makefile | 0 example/{Arista_7132LB => DCS7132LB}/fpga_25g/fpga/config.tcl | 0 example/{Arista_7132LB => DCS7132LB}/fpga_25g/fpga_10g/Makefile | 0 example/{Arista_7132LB => DCS7132LB}/fpga_25g/fpga_10g/config.tcl | 0 example/{Arista_7132LB => DCS7132LB}/fpga_25g/ip/eth_xcvr_gt.tcl | 0 example/{Arista_7132LB => DCS7132LB}/fpga_25g/lib/eth | 0 .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 0 .../fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 0 example/{Arista_7132LB => DCS7132LB}/fpga_25g/rtl/fpga.v | 0 example/{Arista_7132LB => DCS7132LB}/fpga_25g/rtl/fpga_core.v | 0 example/{Arista_7132LB => DCS7132LB}/fpga_25g/rtl/sync_signal.v | 0 .../{Arista_7132LB => DCS7132LB}/fpga_25g/tb/fpga_core/Makefile | 0 .../fpga_25g/tb/fpga_core/test_fpga_core.py | 0 .../fpga_25g/tb/fpga_core/test_fpga_core.v | 0 17 files changed, 0 insertions(+), 0 deletions(-) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/README.md (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/common/vivado.mk (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/fpga.xdc (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/fpga/Makefile (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/fpga/config.tcl (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/fpga_10g/Makefile (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/fpga_10g/config.tcl (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/ip/eth_xcvr_gt.tcl (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/lib/eth (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/rtl/eth_xcvr_phy_wrapper.v (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/rtl/fpga.v (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/rtl/fpga_core.v (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/rtl/sync_signal.v (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/tb/fpga_core/Makefile (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/tb/fpga_core/test_fpga_core.py (100%) rename example/{Arista_7132LB => DCS7132LB}/fpga_25g/tb/fpga_core/test_fpga_core.v (100%) diff --git a/example/Arista_7132LB/fpga_25g/README.md b/example/DCS7132LB/fpga_25g/README.md similarity index 100% rename from example/Arista_7132LB/fpga_25g/README.md rename to example/DCS7132LB/fpga_25g/README.md diff --git a/example/Arista_7132LB/fpga_25g/common/vivado.mk b/example/DCS7132LB/fpga_25g/common/vivado.mk similarity index 100% rename from example/Arista_7132LB/fpga_25g/common/vivado.mk rename to example/DCS7132LB/fpga_25g/common/vivado.mk diff --git a/example/Arista_7132LB/fpga_25g/fpga.xdc b/example/DCS7132LB/fpga_25g/fpga.xdc similarity index 100% rename from example/Arista_7132LB/fpga_25g/fpga.xdc rename to example/DCS7132LB/fpga_25g/fpga.xdc diff --git a/example/Arista_7132LB/fpga_25g/fpga/Makefile b/example/DCS7132LB/fpga_25g/fpga/Makefile similarity index 100% rename from example/Arista_7132LB/fpga_25g/fpga/Makefile rename to example/DCS7132LB/fpga_25g/fpga/Makefile diff --git a/example/Arista_7132LB/fpga_25g/fpga/config.tcl b/example/DCS7132LB/fpga_25g/fpga/config.tcl similarity index 100% rename from example/Arista_7132LB/fpga_25g/fpga/config.tcl rename to example/DCS7132LB/fpga_25g/fpga/config.tcl diff --git a/example/Arista_7132LB/fpga_25g/fpga_10g/Makefile b/example/DCS7132LB/fpga_25g/fpga_10g/Makefile similarity index 100% rename from example/Arista_7132LB/fpga_25g/fpga_10g/Makefile rename to example/DCS7132LB/fpga_25g/fpga_10g/Makefile diff --git a/example/Arista_7132LB/fpga_25g/fpga_10g/config.tcl b/example/DCS7132LB/fpga_25g/fpga_10g/config.tcl similarity index 100% rename from example/Arista_7132LB/fpga_25g/fpga_10g/config.tcl rename to example/DCS7132LB/fpga_25g/fpga_10g/config.tcl diff --git a/example/Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl b/example/DCS7132LB/fpga_25g/ip/eth_xcvr_gt.tcl similarity index 100% rename from example/Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl rename to example/DCS7132LB/fpga_25g/ip/eth_xcvr_gt.tcl diff --git a/example/Arista_7132LB/fpga_25g/lib/eth b/example/DCS7132LB/fpga_25g/lib/eth similarity index 100% rename from example/Arista_7132LB/fpga_25g/lib/eth rename to example/DCS7132LB/fpga_25g/lib/eth diff --git a/example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/DCS7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v similarity index 100% rename from example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v rename to example/DCS7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/DCS7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v rename to example/DCS7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/example/Arista_7132LB/fpga_25g/rtl/fpga.v b/example/DCS7132LB/fpga_25g/rtl/fpga.v similarity index 100% rename from example/Arista_7132LB/fpga_25g/rtl/fpga.v rename to example/DCS7132LB/fpga_25g/rtl/fpga.v diff --git a/example/Arista_7132LB/fpga_25g/rtl/fpga_core.v b/example/DCS7132LB/fpga_25g/rtl/fpga_core.v similarity index 100% rename from example/Arista_7132LB/fpga_25g/rtl/fpga_core.v rename to example/DCS7132LB/fpga_25g/rtl/fpga_core.v diff --git a/example/Arista_7132LB/fpga_25g/rtl/sync_signal.v b/example/DCS7132LB/fpga_25g/rtl/sync_signal.v similarity index 100% rename from example/Arista_7132LB/fpga_25g/rtl/sync_signal.v rename to example/DCS7132LB/fpga_25g/rtl/sync_signal.v diff --git a/example/Arista_7132LB/fpga_25g/tb/fpga_core/Makefile b/example/DCS7132LB/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from example/Arista_7132LB/fpga_25g/tb/fpga_core/Makefile rename to example/DCS7132LB/fpga_25g/tb/fpga_core/Makefile diff --git a/example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py b/example/DCS7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py similarity index 100% rename from example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py rename to example/DCS7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py diff --git a/example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v b/example/DCS7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v similarity index 100% rename from example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v rename to example/DCS7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v From 74936e83c58a0035b1c4ba6d47b9558a6dcb2fbc Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 14 Jan 2024 16:10:20 -0800 Subject: [PATCH 2/4] Add register on PRBS checker output in 10G PHY RX to improve timing performance Signed-off-by: Alex Forencich --- rtl/eth_phy_10g_rx_if.v | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/rtl/eth_phy_10g_rx_if.v b/rtl/eth_phy_10g_rx_if.v index 26eb8ed04..f9e0e953c 100644 --- a/rtl/eth_phy_10g_rx_if.v +++ b/rtl/eth_phy_10g_rx_if.v @@ -147,6 +147,7 @@ wire [57:0] scrambler_state; reg [30:0] prbs31_state_reg = 31'h7fffffff; wire [30:0] prbs31_state; wire [DATA_WIDTH+HDR_WIDTH-1:0] prbs31_data; +reg [DATA_WIDTH+HDR_WIDTH-1:0] prbs31_data_reg = 0; reg [6:0] rx_error_count_reg = 0; reg [5:0] rx_error_count_1_reg = 0; @@ -193,9 +194,9 @@ always @* begin rx_error_count_2_temp = 0; for (i = 0; i < DATA_WIDTH+HDR_WIDTH; i = i + 1) begin if (i & 1) begin - rx_error_count_1_temp = rx_error_count_1_temp + prbs31_data[i]; + rx_error_count_1_temp = rx_error_count_1_temp + prbs31_data_reg[i]; end else begin - rx_error_count_2_temp = rx_error_count_2_temp + prbs31_data[i]; + rx_error_count_2_temp = rx_error_count_2_temp + prbs31_data_reg[i]; end end end @@ -206,12 +207,19 @@ always @(posedge clk) begin encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data; encoded_rx_hdr_reg <= serdes_rx_hdr_int; - if (PRBS31_ENABLE && cfg_rx_prbs31_enable) begin - prbs31_state_reg <= prbs31_state; + if (PRBS31_ENABLE) begin + if (cfg_rx_prbs31_enable) begin + prbs31_state_reg <= prbs31_state; + prbs31_data_reg <= prbs31_data; + end else begin + prbs31_data_reg <= 0; + end rx_error_count_1_reg <= rx_error_count_1_temp; rx_error_count_2_reg <= rx_error_count_2_temp; rx_error_count_reg <= rx_error_count_1_reg + rx_error_count_2_reg; + end else begin + rx_error_count_reg <= 0; end end From f08eb74666225604c34f1e0d19dad885e242f749 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 14 Jan 2024 16:14:57 -0800 Subject: [PATCH 3/4] Optimize block type decoding in 10G PHY RX to reduce fanin Signed-off-by: Alex Forencich --- rtl/xgmii_baser_dec_64.v | 65 +++++++++++++++++++++++++++++----------- 1 file changed, 47 insertions(+), 18 deletions(-) diff --git a/rtl/xgmii_baser_dec_64.v b/rtl/xgmii_baser_dec_64.v index a164f1c0e..4d8e1fa68 100644 --- a/rtl/xgmii_baser_dec_64.v +++ b/rtl/xgmii_baser_dec_64.v @@ -199,19 +199,20 @@ always @* begin endcase end - if (encoded_rx_hdr == SYNC_DATA) begin + // use only four bits of block type for reduced fanin + if (encoded_rx_hdr[0] == 0) begin xgmii_rxd_next = encoded_rx_data; xgmii_rxc_next = 8'h00; rx_bad_block_next = 1'b0; - end else if (encoded_rx_hdr == SYNC_CTRL) begin - case (encoded_rx_data[7:0]) - BLOCK_TYPE_CTRL: begin + end else begin + case (encoded_rx_data[7:4]) + BLOCK_TYPE_CTRL[7:4]: begin // C7 C6 C5 C4 C3 C2 C1 C0 BT xgmii_rxd_next = decoded_ctrl; xgmii_rxc_next = 8'hff; rx_bad_block_next = decode_err != 0; end - BLOCK_TYPE_OS_4: begin + BLOCK_TYPE_OS_4[7:4]: begin // D7 D6 D5 O4 C3 C2 C1 C0 BT xgmii_rxd_next[31:0] = decoded_ctrl[31:0]; xgmii_rxc_next[3:0] = 4'hf; @@ -225,7 +226,7 @@ always @* begin rx_bad_block_next = 1'b1; end end - BLOCK_TYPE_START_4: begin + BLOCK_TYPE_START_4[7:4]: begin // D7 D6 D5 C3 C2 C1 C0 BT xgmii_rxd_next = {encoded_rx_data[63:40], XGMII_START, decoded_ctrl[31:0]}; xgmii_rxc_next = 8'h1f; @@ -233,7 +234,7 @@ always @* begin rx_sequence_error_next = frame_reg; frame_next = 1'b1; end - BLOCK_TYPE_OS_START: begin + BLOCK_TYPE_OS_START[7:4]: begin // D7 D6 D5 O0 D3 D2 D1 BT xgmii_rxd_next[31:8] = encoded_rx_data[31:8]; xgmii_rxc_next[3:0] = 4'hf; @@ -249,7 +250,7 @@ always @* begin rx_sequence_error_next = frame_reg; frame_next = 1'b1; end - BLOCK_TYPE_OS_04: begin + BLOCK_TYPE_OS_04[7:4]: begin // D7 D6 D5 O4 O0 D3 D2 D1 BT rx_bad_block_next = 1'b0; xgmii_rxd_next[31:8] = encoded_rx_data[31:8]; @@ -269,7 +270,7 @@ always @* begin rx_bad_block_next = 1'b1; end end - BLOCK_TYPE_START_0: begin + BLOCK_TYPE_START_0[7:4]: begin // D7 D6 D5 D4 D3 D2 D1 BT xgmii_rxd_next = {encoded_rx_data[63:8], XGMII_START}; xgmii_rxc_next = 8'h01; @@ -277,7 +278,7 @@ always @* begin rx_sequence_error_next = frame_reg; frame_next = 1'b1; end - BLOCK_TYPE_OS_0: begin + BLOCK_TYPE_OS_0[7:4]: begin // C7 C6 C5 C4 O0 D3 D2 D1 BT xgmii_rxd_next[31:8] = encoded_rx_data[31:8]; xgmii_rxc_next[3:0] = 4'h1; @@ -291,7 +292,7 @@ always @* begin xgmii_rxd_next[63:32] = decoded_ctrl[63:32]; xgmii_rxc_next[7:4] = 4'hf; end - BLOCK_TYPE_TERM_0: begin + BLOCK_TYPE_TERM_0[7:4]: begin // C7 C6 C5 C4 C3 C2 C1 BT xgmii_rxd_next = {decoded_ctrl[63:8], XGMII_TERM}; xgmii_rxc_next = 8'hff; @@ -299,7 +300,7 @@ always @* begin rx_sequence_error_next = !frame_reg; frame_next = 1'b0; end - BLOCK_TYPE_TERM_1: begin + BLOCK_TYPE_TERM_1[7:4]: begin // C7 C6 C5 C4 C3 C2 D0 BT xgmii_rxd_next = {decoded_ctrl[63:16], XGMII_TERM, encoded_rx_data[15:8]}; xgmii_rxc_next = 8'hfe; @@ -307,7 +308,7 @@ always @* begin rx_sequence_error_next = !frame_reg; frame_next = 1'b0; end - BLOCK_TYPE_TERM_2: begin + BLOCK_TYPE_TERM_2[7:4]: begin // C7 C6 C5 C4 C3 D1 D0 BT xgmii_rxd_next = {decoded_ctrl[63:24], XGMII_TERM, encoded_rx_data[23:8]}; xgmii_rxc_next = 8'hfc; @@ -315,7 +316,7 @@ always @* begin rx_sequence_error_next = !frame_reg; frame_next = 1'b0; end - BLOCK_TYPE_TERM_3: begin + BLOCK_TYPE_TERM_3[7:4]: begin // C7 C6 C5 C4 D2 D1 D0 BT xgmii_rxd_next = {decoded_ctrl[63:32], XGMII_TERM, encoded_rx_data[31:8]}; xgmii_rxc_next = 8'hf8; @@ -323,7 +324,7 @@ always @* begin rx_sequence_error_next = !frame_reg; frame_next = 1'b0; end - BLOCK_TYPE_TERM_4: begin + BLOCK_TYPE_TERM_4[7:4]: begin // C7 C6 C5 D3 D2 D1 D0 BT xgmii_rxd_next = {decoded_ctrl[63:40], XGMII_TERM, encoded_rx_data[39:8]}; xgmii_rxc_next = 8'hf0; @@ -331,7 +332,7 @@ always @* begin rx_sequence_error_next = !frame_reg; frame_next = 1'b0; end - BLOCK_TYPE_TERM_5: begin + BLOCK_TYPE_TERM_5[7:4]: begin // C7 C6 D4 D3 D2 D1 D0 BT xgmii_rxd_next = {decoded_ctrl[63:48], XGMII_TERM, encoded_rx_data[47:8]}; xgmii_rxc_next = 8'he0; @@ -339,7 +340,7 @@ always @* begin rx_sequence_error_next = !frame_reg; frame_next = 1'b0; end - BLOCK_TYPE_TERM_6: begin + BLOCK_TYPE_TERM_6[7:4]: begin // C7 D5 D4 D3 D2 D1 D0 BT xgmii_rxd_next = {decoded_ctrl[63:56], XGMII_TERM, encoded_rx_data[55:8]}; xgmii_rxc_next = 8'hc0; @@ -347,7 +348,7 @@ always @* begin rx_sequence_error_next = !frame_reg; frame_next = 1'b0; end - BLOCK_TYPE_TERM_7: begin + BLOCK_TYPE_TERM_7[7:4]: begin // D6 D5 D4 D3 D2 D1 D0 BT xgmii_rxd_next = {XGMII_TERM, encoded_rx_data[63:8]}; xgmii_rxc_next = 8'h80; @@ -362,6 +363,34 @@ always @* begin rx_bad_block_next = 1'b1; end endcase + end + + // check all block type bits to detect bad encodings + if (encoded_rx_hdr == SYNC_DATA) begin + end else if (encoded_rx_hdr == SYNC_CTRL) begin + case (encoded_rx_data[7:0]) + BLOCK_TYPE_CTRL: begin end + BLOCK_TYPE_OS_4: begin end + BLOCK_TYPE_START_4: begin end + BLOCK_TYPE_OS_START: begin end + BLOCK_TYPE_OS_04: begin end + BLOCK_TYPE_START_0: begin end + BLOCK_TYPE_OS_0: begin end + BLOCK_TYPE_TERM_0: begin end + BLOCK_TYPE_TERM_1: begin end + BLOCK_TYPE_TERM_2: begin end + BLOCK_TYPE_TERM_3: begin end + BLOCK_TYPE_TERM_4: begin end + BLOCK_TYPE_TERM_5: begin end + BLOCK_TYPE_TERM_6: begin end + BLOCK_TYPE_TERM_7: begin end + default: begin + // invalid block type + xgmii_rxd_next = {8{XGMII_ERROR}}; + xgmii_rxc_next = 8'hff; + rx_bad_block_next = 1'b1; + end + endcase end else begin // invalid header xgmii_rxd_next = {8{XGMII_ERROR}}; From b22db1d2d2456e0a122f8c53c3dde2260dcf0c6e Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 14 Jan 2024 19:17:00 -0800 Subject: [PATCH 4/4] Add CRC state registers where possible to 10G/25G MAC modules Signed-off-by: Alex Forencich --- rtl/axis_baser_tx_64.v | 49 ++++++++++++++++++++++++++---------------- rtl/axis_xgmii_tx_32.v | 38 +++++++++++++++++++------------- rtl/axis_xgmii_tx_64.v | 49 ++++++++++++++++++++++++++---------------- 3 files changed, 83 insertions(+), 53 deletions(-) diff --git a/rtl/axis_baser_tx_64.v b/rtl/axis_baser_tx_64.v index 2fc0b634e..dce320d7a 100644 --- a/rtl/axis_baser_tx_64.v +++ b/rtl/axis_baser_tx_64.v @@ -212,9 +212,8 @@ reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next; reg m_axis_ptp_ts_valid_int_reg = 1'b0, m_axis_ptp_ts_valid_int_next; reg m_axis_ptp_ts_borrow_reg = 1'b0, m_axis_ptp_ts_borrow_next; -reg [31:0] crc_state = 32'hFFFFFFFF; - -wire [31:0] crc_next[7:0]; +reg [31:0] crc_state_reg[7:0]; +wire [31:0] crc_state_next[7:0]; reg [DATA_WIDTH-1:0] encoded_tx_data_reg = {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL}; reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = SYNC_CTRL; @@ -252,9 +251,9 @@ generate ) eth_crc ( .data_in(s_tdata_reg[0 +: 8*(n+1)]), - .state_in(crc_state), + .state_in(crc_state_reg[7]), .data_out(), - .state_out(crc_next[n]) + .state_out(crc_state_next[n]) ); end @@ -288,57 +287,57 @@ end always @* begin casez (s_empty_reg) 3'd7: begin - fcs_output_data_0 = {24'd0, ~crc_next[0][31:0], s_tdata_reg[7:0]}; + fcs_output_data_0 = {24'd0, ~crc_state_next[0][31:0], s_tdata_reg[7:0]}; fcs_output_data_1 = 64'd0; fcs_output_type_0 = OUTPUT_TYPE_TERM_5; fcs_output_type_1 = OUTPUT_TYPE_IDLE; ifg_offset = 8'd3; end 3'd6: begin - fcs_output_data_0 = {16'd0, ~crc_next[1][31:0], s_tdata_reg[15:0]}; + fcs_output_data_0 = {16'd0, ~crc_state_next[1][31:0], s_tdata_reg[15:0]}; fcs_output_data_1 = 64'd0; fcs_output_type_0 = OUTPUT_TYPE_TERM_6; fcs_output_type_1 = OUTPUT_TYPE_IDLE; ifg_offset = 8'd2; end 3'd5: begin - fcs_output_data_0 = {8'd0, ~crc_next[2][31:0], s_tdata_reg[23:0]}; + fcs_output_data_0 = {8'd0, ~crc_state_next[2][31:0], s_tdata_reg[23:0]}; fcs_output_data_1 = 64'd0; fcs_output_type_0 = OUTPUT_TYPE_TERM_7; fcs_output_type_1 = OUTPUT_TYPE_IDLE; ifg_offset = 8'd1; end 3'd4: begin - fcs_output_data_0 = {~crc_next[3][31:0], s_tdata_reg[31:0]}; + fcs_output_data_0 = {~crc_state_next[3][31:0], s_tdata_reg[31:0]}; fcs_output_data_1 = 64'd0; fcs_output_type_0 = OUTPUT_TYPE_DATA; fcs_output_type_1 = OUTPUT_TYPE_TERM_0; ifg_offset = 8'd8; end 3'd3: begin - fcs_output_data_0 = {~crc_next[4][23:0], s_tdata_reg[39:0]}; - fcs_output_data_1 = {56'd0, ~crc_next[4][31:24]}; + fcs_output_data_0 = {~crc_state_next[4][23:0], s_tdata_reg[39:0]}; + fcs_output_data_1 = {56'd0, ~crc_state_reg[4][31:24]}; fcs_output_type_0 = OUTPUT_TYPE_DATA; fcs_output_type_1 = OUTPUT_TYPE_TERM_1; ifg_offset = 8'd7; end 3'd2: begin - fcs_output_data_0 = {~crc_next[5][15:0], s_tdata_reg[47:0]}; - fcs_output_data_1 = {48'd0, ~crc_next[5][31:16]}; + fcs_output_data_0 = {~crc_state_next[5][15:0], s_tdata_reg[47:0]}; + fcs_output_data_1 = {48'd0, ~crc_state_reg[5][31:16]}; fcs_output_type_0 = OUTPUT_TYPE_DATA; fcs_output_type_1 = OUTPUT_TYPE_TERM_2; ifg_offset = 8'd6; end 3'd1: begin - fcs_output_data_0 = {~crc_next[6][7:0], s_tdata_reg[55:0]}; - fcs_output_data_1 = {40'd0, ~crc_next[6][31:8]}; + fcs_output_data_0 = {~crc_state_next[6][7:0], s_tdata_reg[55:0]}; + fcs_output_data_1 = {40'd0, ~crc_state_reg[6][31:8]}; fcs_output_type_0 = OUTPUT_TYPE_DATA; fcs_output_type_1 = OUTPUT_TYPE_TERM_3; ifg_offset = 8'd5; end 3'd0: begin fcs_output_data_0 = s_tdata_reg; - fcs_output_data_1 = {32'd0, ~crc_next[7][31:0]}; + fcs_output_data_1 = {32'd0, ~crc_state_reg[7][31:0]}; fcs_output_type_0 = OUTPUT_TYPE_DATA; fcs_output_type_1 = OUTPUT_TYPE_TERM_4; ifg_offset = 8'd4; @@ -531,6 +530,8 @@ always @* begin output_data_next = fcs_output_data_0; output_type_next = fcs_output_type_0; + update_crc = 1'b1; + ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg; if (s_empty_reg <= 4) begin state_next = STATE_FCS_2; @@ -768,10 +769,20 @@ always @(posedge clk) begin end endcase + crc_state_reg[0] <= crc_state_next[0]; + crc_state_reg[1] <= crc_state_next[1]; + crc_state_reg[2] <= crc_state_next[2]; + crc_state_reg[3] <= crc_state_next[3]; + crc_state_reg[4] <= crc_state_next[4]; + crc_state_reg[5] <= crc_state_next[5]; + crc_state_reg[6] <= crc_state_next[6]; + + if (update_crc) begin + crc_state_reg[7] <= crc_state_next[7]; + end + if (reset_crc) begin - crc_state <= 32'hFFFFFFFF; - end else if (update_crc) begin - crc_state <= crc_next[7]; + crc_state_reg[7] <= 32'hFFFFFFFF; end if (rst) begin diff --git a/rtl/axis_xgmii_tx_32.v b/rtl/axis_xgmii_tx_32.v index a5933061a..86e504ec7 100644 --- a/rtl/axis_xgmii_tx_32.v +++ b/rtl/axis_xgmii_tx_32.v @@ -155,9 +155,8 @@ reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next; reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next; reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next; -reg [31:0] crc_state = 32'hFFFFFFFF; - -wire [31:0] crc_next[3:0]; +reg [31:0] crc_state_reg[3:0]; +wire [31:0] crc_state_next[3:0]; reg [DATA_WIDTH-1:0] xgmii_txd_reg = {CTRL_WIDTH{XGMII_IDLE}}, xgmii_txd_next; reg [CTRL_WIDTH-1:0] xgmii_txc_reg = {CTRL_WIDTH{1'b1}}, xgmii_txc_next; @@ -192,9 +191,9 @@ generate ) eth_crc ( .data_in(s_tdata_reg[0 +: 8*(n+1)]), - .state_in(crc_state), + .state_in(crc_state_reg[3]), .data_out(), - .state_out(crc_next[n]) + .state_out(crc_state_next[n]) ); end @@ -224,24 +223,24 @@ end always @* begin casez (s_empty_reg) 2'd3: begin - fcs_output_txd_0 = {~crc_next[0][23:0], s_tdata_reg[7:0]}; - fcs_output_txd_1 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_next[0][31:24]}; + fcs_output_txd_0 = {~crc_state_next[0][23:0], s_tdata_reg[7:0]}; + fcs_output_txd_1 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[0][31:24]}; fcs_output_txc_0 = 4'b0000; fcs_output_txc_1 = 4'b1110; ifg_offset = 8'd3; extra_cycle = 1'b0; end 2'd2: begin - fcs_output_txd_0 = {~crc_next[1][15:0], s_tdata_reg[15:0]}; - fcs_output_txd_1 = {XGMII_IDLE, XGMII_TERM, ~crc_next[1][31:16]}; + fcs_output_txd_0 = {~crc_state_next[1][15:0], s_tdata_reg[15:0]}; + fcs_output_txd_1 = {XGMII_IDLE, XGMII_TERM, ~crc_state_reg[1][31:16]}; fcs_output_txc_0 = 4'b0000; fcs_output_txc_1 = 4'b1100; ifg_offset = 8'd2; extra_cycle = 1'b0; end 2'd1: begin - fcs_output_txd_0 = {~crc_next[2][7:0], s_tdata_reg[23:0]}; - fcs_output_txd_1 = {XGMII_TERM, ~crc_next[2][31:8]}; + fcs_output_txd_0 = {~crc_state_next[2][7:0], s_tdata_reg[23:0]}; + fcs_output_txd_1 = {XGMII_TERM, ~crc_state_reg[2][31:8]}; fcs_output_txc_0 = 4'b0000; fcs_output_txc_1 = 4'b1000; ifg_offset = 8'd1; @@ -249,7 +248,7 @@ always @* begin end 2'd0: begin fcs_output_txd_0 = s_tdata_reg; - fcs_output_txd_1 = ~crc_next[3]; + fcs_output_txd_1 = ~crc_state_reg[3]; fcs_output_txc_0 = 4'b0000; fcs_output_txc_1 = 4'b0000; ifg_offset = 8'd4; @@ -323,6 +322,7 @@ always @* begin end STATE_PREAMBLE: begin // send preamble + reset_crc = 1'b1; s_tdata_next = s_axis_tdata_masked; s_empty_next = keep2empty(s_axis_tkeep); @@ -415,6 +415,8 @@ always @* begin xgmii_txd_next = fcs_output_txd_0; xgmii_txc_next = fcs_output_txc_0; + update_crc = 1'b1; + ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + deficit_idle_count_reg; state_next = STATE_FCS_2; end @@ -533,10 +535,16 @@ always @(posedge clk) begin m_axis_ptp_ts_tag_reg <= m_axis_ptp_ts_tag_next; m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_next; + crc_state_reg[0] <= crc_state_next[0]; + crc_state_reg[1] <= crc_state_next[1]; + crc_state_reg[2] <= crc_state_next[2]; + + if (update_crc) begin + crc_state_reg[3] <= crc_state_next[3]; + end + if (reset_crc) begin - crc_state <= 32'hFFFFFFFF; - end else if (update_crc) begin - crc_state <= crc_next[3]; + crc_state_reg[3] <= 32'hFFFFFFFF; end xgmii_txd_reg <= xgmii_txd_next; diff --git a/rtl/axis_xgmii_tx_64.v b/rtl/axis_xgmii_tx_64.v index c7ee3fd5b..c1c3714f3 100644 --- a/rtl/axis_xgmii_tx_64.v +++ b/rtl/axis_xgmii_tx_64.v @@ -160,9 +160,8 @@ reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next; reg m_axis_ptp_ts_valid_int_reg = 1'b0, m_axis_ptp_ts_valid_int_next; reg m_axis_ptp_ts_borrow_reg = 1'b0, m_axis_ptp_ts_borrow_next; -reg [31:0] crc_state = 32'hFFFFFFFF; - -wire [31:0] crc_next[7:0]; +reg [31:0] crc_state_reg[7:0]; +wire [31:0] crc_state_next[7:0]; reg [DATA_WIDTH-1:0] xgmii_txd_reg = {CTRL_WIDTH{XGMII_IDLE}}, xgmii_txd_next; reg [CTRL_WIDTH-1:0] xgmii_txc_reg = {CTRL_WIDTH{1'b1}}, xgmii_txc_next; @@ -197,9 +196,9 @@ generate ) eth_crc ( .data_in(s_tdata_reg[0 +: 8*(n+1)]), - .state_in(crc_state), + .state_in(crc_state_reg[7]), .data_out(), - .state_out(crc_next[n]) + .state_out(crc_state_next[n]) ); end @@ -233,57 +232,57 @@ end always @* begin casez (s_empty_reg) 3'd7: begin - fcs_output_txd_0 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_next[0][31:0], s_tdata_reg[7:0]}; + fcs_output_txd_0 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_state_next[0][31:0], s_tdata_reg[7:0]}; fcs_output_txd_1 = {8{XGMII_IDLE}}; fcs_output_txc_0 = 8'b11100000; fcs_output_txc_1 = 8'b11111111; ifg_offset = 8'd3; end 3'd6: begin - fcs_output_txd_0 = {XGMII_IDLE, XGMII_TERM, ~crc_next[1][31:0], s_tdata_reg[15:0]}; + fcs_output_txd_0 = {XGMII_IDLE, XGMII_TERM, ~crc_state_next[1][31:0], s_tdata_reg[15:0]}; fcs_output_txd_1 = {8{XGMII_IDLE}}; fcs_output_txc_0 = 8'b11000000; fcs_output_txc_1 = 8'b11111111; ifg_offset = 8'd2; end 3'd5: begin - fcs_output_txd_0 = {XGMII_TERM, ~crc_next[2][31:0], s_tdata_reg[23:0]}; + fcs_output_txd_0 = {XGMII_TERM, ~crc_state_next[2][31:0], s_tdata_reg[23:0]}; fcs_output_txd_1 = {8{XGMII_IDLE}}; fcs_output_txc_0 = 8'b10000000; fcs_output_txc_1 = 8'b11111111; ifg_offset = 8'd1; end 3'd4: begin - fcs_output_txd_0 = {~crc_next[3][31:0], s_tdata_reg[31:0]}; + fcs_output_txd_0 = {~crc_state_next[3][31:0], s_tdata_reg[31:0]}; fcs_output_txd_1 = {{7{XGMII_IDLE}}, XGMII_TERM}; fcs_output_txc_0 = 8'b00000000; fcs_output_txc_1 = 8'b11111111; ifg_offset = 8'd8; end 3'd3: begin - fcs_output_txd_0 = {~crc_next[4][23:0], s_tdata_reg[39:0]}; - fcs_output_txd_1 = {{6{XGMII_IDLE}}, XGMII_TERM, ~crc_next[4][31:24]}; + fcs_output_txd_0 = {~crc_state_next[4][23:0], s_tdata_reg[39:0]}; + fcs_output_txd_1 = {{6{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[4][31:24]}; fcs_output_txc_0 = 8'b00000000; fcs_output_txc_1 = 8'b11111110; ifg_offset = 8'd7; end 3'd2: begin - fcs_output_txd_0 = {~crc_next[5][15:0], s_tdata_reg[47:0]}; - fcs_output_txd_1 = {{5{XGMII_IDLE}}, XGMII_TERM, ~crc_next[5][31:16]}; + fcs_output_txd_0 = {~crc_state_next[5][15:0], s_tdata_reg[47:0]}; + fcs_output_txd_1 = {{5{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[5][31:16]}; fcs_output_txc_0 = 8'b00000000; fcs_output_txc_1 = 8'b11111100; ifg_offset = 8'd6; end 3'd1: begin - fcs_output_txd_0 = {~crc_next[6][7:0], s_tdata_reg[55:0]}; - fcs_output_txd_1 = {{4{XGMII_IDLE}}, XGMII_TERM, ~crc_next[6][31:8]}; + fcs_output_txd_0 = {~crc_state_next[6][7:0], s_tdata_reg[55:0]}; + fcs_output_txd_1 = {{4{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[6][31:8]}; fcs_output_txc_0 = 8'b00000000; fcs_output_txc_1 = 8'b11111000; ifg_offset = 8'd5; end 3'd0: begin fcs_output_txd_0 = s_tdata_reg; - fcs_output_txd_1 = {{3{XGMII_IDLE}}, XGMII_TERM, ~crc_next[7][31:0]}; + fcs_output_txd_1 = {{3{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[7][31:0]}; fcs_output_txc_0 = 8'b00000000; fcs_output_txc_1 = 8'b11110000; ifg_offset = 8'd4; @@ -480,6 +479,8 @@ always @* begin xgmii_txd_next = fcs_output_txd_0; xgmii_txc_next = fcs_output_txc_0; + update_crc = 1'b1; + ifg_count_next = (cfg_ifg > 8'd12 ? cfg_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + deficit_idle_count_reg; if (s_empty_reg <= 4) begin state_next = STATE_FCS_2; @@ -622,10 +623,20 @@ always @(posedge clk) begin m_axis_ptp_ts_valid_int_reg <= m_axis_ptp_ts_valid_int_next; m_axis_ptp_ts_borrow_reg <= m_axis_ptp_ts_borrow_next; + crc_state_reg[0] <= crc_state_next[0]; + crc_state_reg[1] <= crc_state_next[1]; + crc_state_reg[2] <= crc_state_next[2]; + crc_state_reg[3] <= crc_state_next[3]; + crc_state_reg[4] <= crc_state_next[4]; + crc_state_reg[5] <= crc_state_next[5]; + crc_state_reg[6] <= crc_state_next[6]; + + if (update_crc) begin + crc_state_reg[7] <= crc_state_next[7]; + end + if (reset_crc) begin - crc_state <= 32'hFFFFFFFF; - end else if (update_crc) begin - crc_state <= crc_next[7]; + crc_state_reg[7] <= 32'hFFFFFFFF; end swap_txd <= xgmii_txd_next[63:32];