From 37f26075da8ad4361c196d2f43d6253b8470c6fa Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Fri, 3 May 2024 22:00:33 -0700
Subject: [PATCH] Add ETH_RS_FEC_ENABLE to config.tcl for UltraScale+ 100G
 designs

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl             | 1 +
 .../250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl      | 1 +
 fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v                  | 5 +++--
 fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl        | 1 +
 .../ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl | 1 +
 fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl   | 1 +
 fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v             | 5 +++--
 fpga/mqnic/Alveo/fpga_100g/fpga_AU200/config.tcl         | 1 +
 .../Alveo/fpga_100g/fpga_AU200_app_dma_bench/config.tcl  | 1 +
 fpga/mqnic/Alveo/fpga_100g/fpga_AU250/config.tcl         | 1 +
 .../Alveo/fpga_100g/fpga_AU250_app_dma_bench/config.tcl  | 1 +
 fpga/mqnic/Alveo/fpga_100g/fpga_AU280/config.tcl         | 1 +
 .../Alveo/fpga_100g/fpga_AU280_app_dma_bench/config.tcl  | 1 +
 fpga/mqnic/Alveo/fpga_100g/fpga_AU50/config.tcl          | 1 +
 .../Alveo/fpga_100g/fpga_AU50_app_dma_bench/config.tcl   | 1 +
 fpga/mqnic/Alveo/fpga_100g/fpga_AU55N/config.tcl         | 1 +
 .../Alveo/fpga_100g/fpga_AU55N_app_dma_bench/config.tcl  | 1 +
 fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/config.tcl       | 1 +
 .../fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl      | 1 +
 fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v              | 5 +++--
 fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v              | 5 +++--
 fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v               | 3 ++-
 fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v               | 5 +++--
 fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl              | 1 +
 .../mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl | 1 +
 fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v                   | 5 +++--
 fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl              | 1 +
 .../mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl | 1 +
 fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v                   | 9 +++++----
 fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl               | 1 +
 fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl | 1 +
 fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl  | 1 +
 fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl          | 1 +
 fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v                    | 5 +++--
 fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl             | 1 +
 .../fb4CGg3/fpga_100g/fpga_app_dma_bench/config.tcl      | 1 +
 fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v                  | 9 +++++----
 37 files changed, 60 insertions(+), 23 deletions(-)

diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl
index dd2e6d2fe..7a60ddf08 100644
--- a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl
index 3dc015e43..4ce8b3f55 100644
--- a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
index bc682a3bc..c324f0129 100644
--- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
@@ -130,6 +130,7 @@ module fpga #
     parameter AXIS_ETH_RX_PIPELINE = 4,
     parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
     parameter ETH_RX_CLK_FROM_TX = 0,
+    parameter ETH_RS_FEC_ENABLE = 1,
 
     // Statistics counter subsystem
     parameter STAT_ENABLE = 1,
@@ -779,7 +780,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp0_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -953,7 +954,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp1_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
index 132a4c581..133c4a3fa 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "0"
 dict set params AXIS_ETH_RX_PIPELINE "0"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl
index 4b89f3103..26d170671 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "0"
 dict set params AXIS_ETH_RX_PIPELINE "0"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
index ad493e771..7c4f5042f 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "0"
 dict set params AXIS_ETH_RX_PIPELINE "0"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
index f39b7aeb3..aca860ceb 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
@@ -130,6 +130,7 @@ module fpga #
     parameter AXIS_ETH_RX_PIPELINE = 0,
     parameter AXIS_ETH_RX_FIFO_PIPELINE = 2,
     parameter ETH_RX_CLK_FROM_TX = 0,
+    parameter ETH_RS_FEC_ENABLE = 1,
 
     // Statistics counter subsystem
     parameter STAT_ENABLE = 1,
@@ -1014,7 +1015,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp_0_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -1188,7 +1189,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp_1_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU200/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200/config.tcl
index 9058acc60..9a592774f 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU200/config.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200/config.tcl
@@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/config.tcl
index f620c0aba..88eaf5139 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/config.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/config.tcl
@@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU250/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250/config.tcl
index 612a82bc4..1c4448156 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU250/config.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250/config.tcl
@@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/config.tcl
index 777dff560..0f0cc944f 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/config.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/config.tcl
@@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU280/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU280/config.tcl
index 4efd86bae..449f44d5f 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU280/config.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU280/config.tcl
@@ -159,6 +159,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU280_app_dma_bench/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU280_app_dma_bench/config.tcl
index 14db4d1d0..9b53586b6 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU280_app_dma_bench/config.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU280_app_dma_bench/config.tcl
@@ -159,6 +159,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU50/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50/config.tcl
index 6ec716274..21d6e4f49 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU50/config.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50/config.tcl
@@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/config.tcl
index 611795af1..9208cbd5f 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/config.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/config.tcl
@@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N/config.tcl
index 3a19ba943..bdd40cdee 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N/config.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N/config.tcl
@@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N_app_dma_bench/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N_app_dma_bench/config.tcl
index 904c3e50b..78bab4ca2 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N_app_dma_bench/config.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N_app_dma_bench/config.tcl
@@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/config.tcl
index e286947c0..ce77bc8f0 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/config.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/config.tcl
@@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl
index d9277291d..8972ed88e 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl
@@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
index 3783bf4d0..defd581c4 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
@@ -133,6 +133,7 @@ module fpga #
     parameter AXIS_ETH_RX_PIPELINE = 4,
     parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
     parameter ETH_RX_CLK_FROM_TX = 0,
+    parameter ETH_RS_FEC_ENABLE = 1,
 
     // Statistics counter subsystem
     parameter STAT_ENABLE = 1,
@@ -1223,7 +1224,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp0_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -1355,7 +1356,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp1_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v
index e3e4ed152..d40a42b97 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v
@@ -138,6 +138,7 @@ module fpga #
     parameter AXIS_ETH_RX_PIPELINE = 4,
     parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
     parameter ETH_RX_CLK_FROM_TX = 0,
+    parameter ETH_RS_FEC_ENABLE = 1,
 
     // Statistics counter subsystem
     parameter STAT_ENABLE = 1,
@@ -1102,7 +1103,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp0_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -1230,7 +1231,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp1_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v
index 9c06f7cb4..4964ca0ee 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v
@@ -131,6 +131,7 @@ module fpga #
     parameter AXIS_ETH_RX_PIPELINE = 4,
     parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
     parameter ETH_RX_CLK_FROM_TX = 0,
+    parameter ETH_RS_FEC_ENABLE = 1,
 
     // Statistics counter subsystem
     parameter STAT_ENABLE = 1,
@@ -1043,7 +1044,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v
index 418f8d119..ab0aa66d6 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v
@@ -131,6 +131,7 @@ module fpga #
     parameter AXIS_ETH_RX_PIPELINE = 4,
     parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
     parameter ETH_RX_CLK_FROM_TX = 0,
+    parameter ETH_RS_FEC_ENABLE = 1,
 
     // Statistics counter subsystem
     parameter STAT_ENABLE = 1,
@@ -1048,7 +1049,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp0_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -1173,7 +1174,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp1_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
index 5e14f1136..7ebc9d7f7 100644
--- a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl
index c6cbb5540..c05c33d78 100644
--- a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
index 2d347d347..7038ccb1a 100644
--- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
@@ -130,6 +130,7 @@ module fpga #
     parameter AXIS_ETH_RX_PIPELINE = 4,
     parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
     parameter ETH_RX_CLK_FROM_TX = 0,
+    parameter ETH_RS_FEC_ENABLE = 1,
 
     // Statistics counter subsystem
     parameter STAT_ENABLE = 1,
@@ -1001,7 +1002,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp1_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -1140,7 +1141,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp2_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
index a19d3efd4..7b6269461 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl
index a293b69e1..259ae3314 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
index 95b687fc5..e01562fa0 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
@@ -130,6 +130,7 @@ module fpga #
     parameter AXIS_ETH_RX_PIPELINE = 4,
     parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
     parameter ETH_RX_CLK_FROM_TX = 0,
+    parameter ETH_RS_FEC_ENABLE = 1,
 
     // Statistics counter subsystem
     parameter STAT_ENABLE = 1,
@@ -1105,7 +1106,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp0_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -1279,7 +1280,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp1_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -1453,7 +1454,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp2_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -1627,7 +1628,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp3_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
index 7093bd37e..ebcadadd6 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "0"
 dict set params AXIS_ETH_RX_PIPELINE "0"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl
index 74d3be742..c0ed851ca 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "0"
 dict set params AXIS_ETH_RX_PIPELINE "0"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl
index eaec0afe4..195959a5b 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "0"
 dict set params AXIS_ETH_RX_PIPELINE "0"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
index d0c24254b..c203ac95e 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "0"
 dict set params AXIS_ETH_RX_PIPELINE "0"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
index bd0deaca8..9fcd8d19d 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
@@ -130,6 +130,7 @@ module fpga #
     parameter AXIS_ETH_RX_PIPELINE = 0,
     parameter AXIS_ETH_RX_FIFO_PIPELINE = 2,
     parameter ETH_RX_CLK_FROM_TX = 0,
+    parameter ETH_RS_FEC_ENABLE = 1,
 
     // Statistics counter subsystem
     parameter STAT_ENABLE = 1,
@@ -1048,7 +1049,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp_0_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -1222,7 +1223,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp_1_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl
index 6fa58e61c..f7cfe70ff 100644
--- a/fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/config.tcl
index 71ae71871..03986eeed 100644
--- a/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
 dict set params ETH_RX_CLK_FROM_TX "0"
+dict set params ETH_RS_FEC_ENABLE "1"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"
diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v
index d1f39e356..c43a4ad76 100644
--- a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v
@@ -130,6 +130,7 @@ module fpga #
     parameter AXIS_ETH_RX_PIPELINE = 4,
     parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
     parameter ETH_RX_CLK_FROM_TX = 0,
+    parameter ETH_RS_FEC_ENABLE = 1,
 
     // Statistics counter subsystem
     parameter STAT_ENABLE = 1,
@@ -1034,7 +1035,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp_0_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -1216,7 +1217,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp_1_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -1398,7 +1399,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp_2_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),
@@ -1580,7 +1581,7 @@ cmac_gty_wrapper #(
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
     .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
-    .RS_FEC_ENABLE(1)
+    .RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
 )
 qsfp_3_cmac_inst (
     .xcvr_ctrl_clk(clk_125mhz_int),