From 2cde31a0663cbe127cfa56489188cfa26592ebc0 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Sun, 11 Feb 2024 21:50:59 -0800
Subject: [PATCH] Add support for truncated relative timestamps

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 .../rtl/mqnic_app_block_custom_port_demo.v    |  3 +-
 .../tb/mqnic_core_pcie_us/Makefile            |  3 +
 .../test_mqnic_core_pcie_us.py                | 24 +++---
 .../dma_bench/rtl/mqnic_app_block_dma_bench.v |  3 +-
 .../dma_bench/tb/mqnic_core_pcie_us/Makefile  |  3 +
 .../test_mqnic_core_pcie_us.py                | 24 +++---
 fpga/app/template/rtl/mqnic_app_block.v       |  3 +-
 .../template/tb/mqnic_core_pcie_us/Makefile   |  3 +
 .../test_mqnic_core_pcie_us.py                | 24 +++---
 fpga/common/rtl/mqnic_core.v                  | 58 +++++++------
 fpga/common/rtl/mqnic_core_axi.v              | 22 ++---
 fpga/common/rtl/mqnic_core_pcie.v             | 22 ++---
 fpga/common/rtl/mqnic_core_pcie_ptile.v       | 22 ++---
 fpga/common/rtl/mqnic_core_pcie_s10.v         | 22 ++---
 fpga/common/rtl/mqnic_core_pcie_us.v          | 22 ++---
 fpga/common/rtl/mqnic_interface.v             | 27 ++++--
 fpga/common/rtl/mqnic_interface_rx.v          | 20 ++++-
 fpga/common/rtl/mqnic_interface_tx.v          | 20 ++++-
 fpga/common/rtl/rx_engine.v                   | 83 +++++++++++++++++--
 fpga/common/rtl/tx_engine.v                   | 83 +++++++++++++++----
 fpga/common/tb/mqnic_core_axi/Makefile        |  3 +
 .../tb/mqnic_core_axi/test_mqnic_core_axi.py  | 22 +++--
 fpga/common/tb/mqnic_core_pcie_ptile/Makefile |  3 +
 .../test_mqnic_core_pcie_ptile.py             | 28 ++++---
 fpga/common/tb/mqnic_core_pcie_s10/Makefile   |  3 +
 .../test_mqnic_core_pcie_s10.py               | 28 ++++---
 fpga/common/tb/mqnic_core_pcie_us/Makefile    |  3 +
 .../test_mqnic_core_pcie_us.py                | 28 ++++---
 .../tb/mqnic_core_pcie_us_tdma/Makefile       |  3 +
 .../test_mqnic_core_pcie_us.py                | 28 ++++---
 fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile    |  2 +
 .../fpga_100g/fpga_app_dma_bench/Makefile     |  2 +
 .../250_SoC/fpga_100g/ip/cmac_usplus.tcl      |  3 +-
 fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v       |  6 +-
 fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v  | 51 ++++++------
 .../250_SoC/fpga_100g/tb/fpga_core/Makefile   |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |  1 +
 fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile     |  2 +
 fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile |  2 +
 fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v        |  6 +-
 fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v   | 28 ++++---
 .../250_SoC/fpga_25g/tb/fpga_core/Makefile    |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  1 +
 fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile     |  1 +
 fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile |  1 +
 fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v        |  6 +-
 fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v   | 28 ++++---
 .../520N_MX/fpga_25g/tb/fpga_core/Makefile    |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  1 +
 .../ADM_PCIE_9V3/fpga_100g/fpga/Makefile      |  2 +
 .../fpga_100g/fpga_app_dma_bench/Makefile     |  2 +
 .../ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile |  2 +
 .../ADM_PCIE_9V3/fpga_100g/ip/cmac_usplus.tcl |  3 +-
 fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v  |  6 +-
 .../ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v    | 51 ++++++------
 .../fpga_100g/tb/fpga_core/Makefile           |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |  1 +
 .../mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile |  2 +
 .../ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile   |  2 +
 .../ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile  |  2 +
 fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v   |  6 +-
 .../ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v     | 28 ++++---
 .../fpga_25g/tb/fpga_core/Makefile            |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  1 +
 .../mqnic/Alveo/fpga_100g/fpga_AU200/Makefile |  2 +
 .../fpga_AU200_app_dma_bench/Makefile         |  2 +
 .../mqnic/Alveo/fpga_100g/fpga_AU250/Makefile |  2 +
 .../fpga_AU250_app_dma_bench/Makefile         |  2 +
 .../mqnic/Alveo/fpga_100g/fpga_AU280/Makefile |  2 +
 .../fpga_AU280_app_dma_bench/Makefile         |  2 +
 fpga/mqnic/Alveo/fpga_100g/fpga_AU50/Makefile |  2 +
 .../fpga_AU50_app_dma_bench/Makefile          |  2 +
 .../mqnic/Alveo/fpga_100g/fpga_AU55N/Makefile |  2 +
 .../fpga_AU55N_app_dma_bench/Makefile         |  2 +
 .../Alveo/fpga_100g/fpga_VCU1525/Makefile     |  2 +
 .../fpga_VCU1525_app_dma_bench/Makefile       |  2 +
 fpga/mqnic/Alveo/fpga_100g/ip/cmac_usplus.tcl |  3 +-
 fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v   |  6 +-
 fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v   |  6 +-
 fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v    |  6 +-
 fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v    |  6 +-
 fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v    | 38 +++++----
 .../Alveo/fpga_100g/tb/fpga_core/Makefile     |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.v   |  6 +-
 fpga/mqnic/Alveo/fpga_25g/fpga_AU200/Makefile |  2 +
 .../Alveo/fpga_25g/fpga_AU200_10g/Makefile    |  2 +
 fpga/mqnic/Alveo/fpga_25g/fpga_AU250/Makefile |  2 +
 .../Alveo/fpga_25g/fpga_AU250_10g/Makefile    |  2 +
 fpga/mqnic/Alveo/fpga_25g/fpga_AU280/Makefile |  2 +
 .../Alveo/fpga_25g/fpga_AU280_10g/Makefile    |  2 +
 fpga/mqnic/Alveo/fpga_25g/fpga_AU50/Makefile  |  2 +
 .../Alveo/fpga_25g/fpga_AU50_10g/Makefile     |  2 +
 fpga/mqnic/Alveo/fpga_25g/fpga_AU55N/Makefile |  2 +
 .../Alveo/fpga_25g/fpga_AU55N_10g/Makefile    |  2 +
 .../Alveo/fpga_25g/fpga_VCU1525/Makefile      |  2 +
 .../Alveo/fpga_25g/fpga_VCU1525_10g/Makefile  |  2 +
 fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v    |  6 +-
 fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v    |  6 +-
 fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v     |  6 +-
 fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v     |  6 +-
 fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v     | 28 ++++---
 .../Alveo/fpga_25g/tb/fpga_core/Makefile      |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.v    |  6 +-
 .../DE10_Agilex/fpga_100g/fpga_100g/Makefile  |  1 +
 .../fpga_100g/fpga_100g_24AR0/Makefile        |  1 +
 .../fpga_100g_app_dma_bench/Makefile          |  1 +
 .../fpga_100g_app_dma_bench_24AR0/Makefile    |  1 +
 .../DE10_Agilex/fpga_100g/fpga_10g/Makefile   |  1 +
 .../fpga_100g/fpga_10g_24AR0/Makefile         |  1 +
 .../DE10_Agilex/fpga_100g/fpga_25g/Makefile   |  1 +
 .../fpga_100g/fpga_25g_24AR0/Makefile         |  1 +
 fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v   |  6 +-
 .../DE10_Agilex/fpga_100g/rtl/fpga_core.v     | 30 +++----
 .../fpga_100g/tb/fpga_core/Makefile           |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.v   |  6 +-
 .../fpga_100g/fpga_100g/Makefile              |  1 +
 .../fpga_100g_app_dma_bench/Makefile          |  1 +
 .../fpga_100g/fpga_10g/Makefile               |  1 +
 .../fpga_100g/fpga_25g/Makefile               |  1 +
 .../DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v      |  6 +-
 .../DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v | 30 +++----
 .../fpga_100g/tb/fpga_core/Makefile           |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.v   |  6 +-
 .../fpga_25g/fpga_10g_1sm21b/Makefile         |  1 +
 .../fpga_25g/fpga_10g_1sm21c/Makefile         |  1 +
 .../fpga_25g/fpga_1sm21b/Makefile             |  1 +
 .../fpga_25g/fpga_1sm21c/Makefile             |  1 +
 .../mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v |  6 +-
 .../DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v  | 28 ++++---
 .../fpga_25g/tb/fpga_core/Makefile            |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  1 +
 .../fpga_100g/fpga_100g/Makefile              |  1 +
 .../fpga_100g/fpga_100g_24AR0/Makefile        |  1 +
 .../fpga_100g_app_dma_bench/Makefile          |  1 +
 .../fpga_100g_app_dma_bench_24AR0/Makefile    |  1 +
 .../fpga_100g/fpga_10g/Makefile               |  1 +
 .../fpga_100g/fpga_10g_24AR0/Makefile         |  1 +
 .../fpga_100g/fpga_25g/Makefile               |  1 +
 .../fpga_100g/fpga_25g_24AR0/Makefile         |  1 +
 .../DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v      |  6 +-
 .../DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v | 30 +++----
 .../fpga_100g/tb/fpga_core/Makefile           |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.v   |  6 +-
 .../fpga/fpga_app_dma_bench_ku040/Makefile    |  2 +
 .../fpga/fpga_app_dma_bench_ku060/Makefile    |  2 +
 .../fpga/fpga_ku040/Makefile                  |  2 +
 .../fpga/fpga_ku060/Makefile                  |  2 +
 .../DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v    |  6 +-
 .../fpga/rtl/fpga_core.v                      | 28 ++++---
 .../fpga/tb/fpga_core/Makefile                |  1 +
 .../fpga/tb/fpga_core/test_fpga_core.py       |  1 +
 .../IA_420F/fpga_100g/fpga_100g/Makefile      |  1 +
 .../fpga_100g_app_dma_bench/Makefile          |  1 +
 .../mqnic/IA_420F/fpga_100g/fpga_10g/Makefile |  1 +
 .../mqnic/IA_420F/fpga_100g/fpga_25g/Makefile |  1 +
 fpga/mqnic/IA_420F/fpga_100g/rtl/fpga.v       |  6 +-
 fpga/mqnic/IA_420F/fpga_100g/rtl/fpga_core.v  | 30 +++----
 .../IA_420F/fpga_100g/tb/fpga_core/Makefile   |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.v   |  6 +-
 fpga/mqnic/KR260/fpga/fpga/Makefile           |  2 +
 .../KR260/fpga/fpga_app_dma_bench/Makefile    |  2 +
 fpga/mqnic/KR260/fpga/rtl/fpga.v              |  6 +-
 fpga/mqnic/KR260/fpga/rtl/fpga_core.v         | 28 ++++---
 fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile   |  1 +
 .../KR260/fpga/tb/fpga_core/test_fpga_core.py |  1 +
 fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile    |  2 +
 .../fpga/fpga_app_dma_bench/Makefile          |  2 +
 fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v       |  6 +-
 fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v  | 28 ++++---
 .../NetFPGA_SUME/fpga/tb/fpga_core/Makefile   |  1 +
 .../fpga/tb/fpga_core/test_fpga_core.py       |  1 +
 fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile |  2 +
 .../Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile    |  2 +
 .../fpga_25g/fpga_app_dma_bench/Makefile      |  2 +
 fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v    |  6 +-
 .../Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v      | 28 ++++---
 .../fpga_25g/tb/fpga_core/Makefile            |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  1 +
 .../Nexus_K3P_S/fpga_25g/fpga_K35/Makefile    |  2 +
 .../fpga_25g/fpga_K35_app_dma_bench/Makefile  |  2 +
 .../Nexus_K3P_S/fpga_25g/fpga_K3P/Makefile    |  2 +
 .../fpga_25g/fpga_K3P_10g/Makefile            |  2 +
 .../fpga_25g/fpga_K3P_app_dma_bench/Makefile  |  2 +
 .../Nexus_K3P_S/fpga_25g/rtl/fpga_core.v      | 28 ++++---
 .../mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k35.v |  6 +-
 .../mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k3p.v |  6 +-
 .../fpga_25g/tb/fpga_core/Makefile            |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  1 +
 fpga/mqnic/VCU108/fpga_25g/fpga/Makefile      |  2 +
 fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile  |  2 +
 .../fpga_25g/fpga_app_dma_bench/Makefile      |  2 +
 fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v         |  6 +-
 fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v    | 28 ++++---
 .../VCU108/fpga_25g/tb/fpga_core/Makefile     |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  1 +
 fpga/mqnic/VCU118/fpga_100g/fpga/Makefile     |  2 +
 .../fpga_100g/fpga_app_dma_bench/Makefile     |  2 +
 .../mqnic/VCU118/fpga_100g/ip/cmac_usplus.tcl |  3 +-
 fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v        |  6 +-
 fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v   | 51 ++++++------
 .../VCU118/fpga_100g/tb/fpga_core/Makefile    |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |  1 +
 fpga/mqnic/VCU118/fpga_25g/fpga/Makefile      |  2 +
 fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile  |  2 +
 fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v         |  6 +-
 fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v    | 28 ++++---
 .../VCU118/fpga_25g/tb/fpga_core/Makefile     |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  1 +
 fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile     |  2 +
 .../fpga_100g/fpga_app_dma_bench/Makefile     |  2 +
 .../mqnic/XUPP3R/fpga_100g/ip/cmac_usplus.tcl |  3 +-
 fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v        |  6 +-
 fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v   | 63 +++++++-------
 .../XUPP3R/fpga_100g/tb/fpga_core/Makefile    |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |  1 +
 .../XUPP3R/fpga_25g/fpga_XUPP3R/Makefile      |  2 +
 .../XUPP3R/fpga_25g/fpga_XUPP3R_10g/Makefile  |  2 +
 .../XUPP3R/fpga_25g/fpga_XUSP3S/Makefile      |  2 +
 .../XUPP3R/fpga_25g/fpga_XUSP3S_10g/Makefile  |  2 +
 .../fpga_XUSP3S_app_dma_bench/Makefile        |  2 +
 fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v    | 28 ++++---
 fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v  |  6 +-
 fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v  |  6 +-
 .../XUPP3R/fpga_25g/tb/fpga_core/Makefile     |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  1 +
 fpga/mqnic/ZCU102/fpga/fpga/Makefile          |  2 +
 .../fpga/fpga_app_custom_port_demo/Makefile   |  2 +
 .../ZCU102/fpga/fpga_app_dma_bench/Makefile   |  2 +
 fpga/mqnic/ZCU102/fpga/rtl/fpga.v             |  6 +-
 fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v        | 28 ++++---
 .../fpga/rtl/fpga_core_custom_port_demo.v     | 28 ++++---
 .../ZCU102/fpga/rtl/fpga_custom_port_demo.v   |  6 +-
 fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile  |  1 +
 .../fpga/tb/fpga_core/test_fpga_core.py       |  1 +
 .../fpga_core_app_custom_port_demo/Makefile   |  1 +
 .../test_fpga_core.py                         |  1 +
 fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile     |  2 +
 .../fpga_pcie/fpga_app_dma_bench/Makefile     |  2 +
 fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v        |  6 +-
 fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v   | 28 ++++---
 .../ZCU106/fpga_pcie/tb/fpga_core/Makefile    |  1 +
 .../fpga_pcie/tb/fpga_core/test_fpga_core.py  |  1 +
 fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile   |  2 +
 .../fpga_zynqmp/fpga_app_dma_bench/Makefile   |  2 +
 fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v      |  6 +-
 fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v | 28 ++++---
 .../ZCU106/fpga_zynqmp/tb/fpga_core/Makefile  |  1 +
 .../tb/fpga_core/test_fpga_core.py            |  1 +
 fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile      |  2 +
 .../fpga_100g/fpga_app_dma_bench/Makefile     |  2 +
 .../fpga_100g/fpga_app_template/Makefile      |  2 +
 fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile |  2 +
 fpga/mqnic/fb2CG/fpga_100g/ip/cmac_usplus.tcl |  3 +-
 fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v         |  6 +-
 fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v    | 51 ++++++------
 .../fb2CG/fpga_100g/tb/fpga_core/Makefile     |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |  1 +
 fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile       |  2 +
 fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile   |  2 +
 fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile  |  2 +
 fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v          |  6 +-
 fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v     | 26 +++---
 .../fb2CG/fpga_25g/tb/fpga_core/Makefile      |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  1 +
 fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile    |  2 +
 .../fpga_100g/fpga_app_dma_bench/Makefile     |  2 +
 .../fb4CGg3/fpga_100g/ip/cmac_usplus.tcl      |  3 +-
 fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v       |  6 +-
 fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v  | 63 +++++++-------
 .../fb4CGg3/fpga_100g/tb/fpga_core/Makefile   |  1 +
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  |  1 +
 fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile     |  2 +
 fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile |  2 +
 fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v        |  6 +-
 fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v   | 28 ++++---
 .../fb4CGg3/fpga_25g/tb/fpga_core/Makefile    |  1 +
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   |  1 +
 283 files changed, 1405 insertions(+), 792 deletions(-)

diff --git a/fpga/app/custom_port_demo/rtl/mqnic_app_block_custom_port_demo.v b/fpga/app/custom_port_demo/rtl/mqnic_app_block_custom_port_demo.v
index 554c3e86a..1afe1d417 100644
--- a/fpga/app/custom_port_demo/rtl/mqnic_app_block_custom_port_demo.v
+++ b/fpga/app/custom_port_demo/rtl/mqnic_app_block_custom_port_demo.v
@@ -36,13 +36,14 @@ module mqnic_app_block #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 4,
     parameter PTP_CLK_PERIOD_NS_DENOM = 1,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_PORT_CDC_PIPELINE = 0,
     parameter PTP_PEROUT_ENABLE = 0,
     parameter PTP_PEROUT_COUNT = 1,
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     parameter TX_TAG_WIDTH = 16,
     parameter MAX_TX_SIZE = 9214,
     parameter MAX_RX_SIZE = 9214,
diff --git a/fpga/app/custom_port_demo/tb/mqnic_core_pcie_us/Makefile b/fpga/app/custom_port_demo/tb/mqnic_core_pcie_us/Makefile
index 649b3e35b..dfb4ae8c6 100644
--- a/fpga/app/custom_port_demo/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/app/custom_port_demo/tb/mqnic_core_pcie_us/Makefile
@@ -62,6 +62,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
@@ -159,6 +160,8 @@ export PARAM_TDMA_INDEX_WIDTH := 6
 
 # Interface configuration
 export PARAM_PTP_TS_ENABLE := 1
+export PARAM_PTP_TS_FMT_TOD := 0
+export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),48,96)
 export PARAM_TX_CPL_ENABLE := $(PARAM_PTP_TS_ENABLE)
 export PARAM_TX_CPL_FIFO_DEPTH := 32
 export PARAM_TX_TAG_WIDTH := 16
diff --git a/fpga/app/custom_port_demo/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/custom_port_demo/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 175c19c6b..a42e2f46b 100644
--- a/fpga/app/custom_port_demo/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/app/custom_port_demo/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -759,18 +759,19 @@ async def run_test_nic(dut):
 
 
 @pytest.mark.parametrize(("if_count", "ports_per_if", "axis_pcie_data_width",
-        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
-            (1, 1, 256, 64, 64, 1),
-            (1, 1, 256, 64, 64, 0),
-            (2, 1, 256, 64, 64, 1),
-            (1, 2, 256, 64, 64, 1),
-            (1, 1, 256, 64, 128, 1),
-            (1, 1, 512, 64, 64, 1),
-            (1, 1, 512, 64, 128, 1),
-            (1, 1, 512, 512, 512, 1),
+        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable", "ptp_ts_fmt_tod"), [
+            (1, 1, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 64, 1, 1),
+            (1, 1, 256, 64, 64, 0, 0),
+            (2, 1, 256, 64, 64, 1, 0),
+            (1, 2, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 128, 1, 0),
+            (1, 1, 512, 64, 64, 1, 0),
+            (1, 1, 512, 64, 128, 1, 0),
+            (1, 1, 512, 512, 512, 1, 0),
         ])
 def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_width,
-        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
+        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable, ptp_ts_fmt_tod):
     dut = "mqnic_core_pcie_us"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -828,6 +829,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
@@ -928,6 +930,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
 
     # Interface configuration
     parameters['PTP_TS_ENABLE'] = ptp_ts_enable
+    parameters['PTP_TS_FMT_TOD'] = ptp_ts_fmt_tod
+    parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 48
     parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
     parameters['TX_CPL_FIFO_DEPTH'] = 32
     parameters['TX_TAG_WIDTH'] = 16
diff --git a/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v b/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v
index fe06c537b..7a3841c47 100644
--- a/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v
+++ b/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v
@@ -28,13 +28,14 @@ module mqnic_app_block #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 4,
     parameter PTP_CLK_PERIOD_NS_DENOM = 1,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_PORT_CDC_PIPELINE = 0,
     parameter PTP_PEROUT_ENABLE = 0,
     parameter PTP_PEROUT_COUNT = 1,
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     parameter TX_TAG_WIDTH = 16,
     parameter MAX_TX_SIZE = 9214,
     parameter MAX_RX_SIZE = 9214,
diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
index 3a1e2e380..6654471ae 100644
--- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
@@ -63,6 +63,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axi_vfifo_raw.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axi_vfifo_raw_rd.v
@@ -164,6 +165,8 @@ export PARAM_TDMA_INDEX_WIDTH := 6
 
 # Interface configuration
 export PARAM_PTP_TS_ENABLE := 1
+export PARAM_PTP_TS_FMT_TOD := 0
+export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),48,96)
 export PARAM_TX_CPL_ENABLE := $(PARAM_PTP_TS_ENABLE)
 export PARAM_TX_CPL_FIFO_DEPTH := 32
 export PARAM_TX_TAG_WIDTH := 16
diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 25aa6cf07..be013fde6 100644
--- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -950,18 +950,19 @@ async def run_test_nic(dut):
 
 
 @pytest.mark.parametrize(("if_count", "ports_per_if", "axis_pcie_data_width",
-        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
-            (1, 1, 256, 64, 64, 1),
-            (1, 1, 256, 64, 64, 0),
-            (2, 1, 256, 64, 64, 1),
-            (1, 2, 256, 64, 64, 1),
-            (1, 1, 256, 64, 128, 1),
-            (1, 1, 512, 64, 64, 1),
-            (1, 1, 512, 64, 128, 1),
-            (1, 1, 512, 512, 512, 1),
+        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable", "ptp_ts_fmt_tod"), [
+            (1, 1, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 64, 1, 1),
+            (1, 1, 256, 64, 64, 0, 0),
+            (2, 1, 256, 64, 64, 1, 0),
+            (1, 2, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 128, 1, 0),
+            (1, 1, 512, 64, 64, 1, 0),
+            (1, 1, 512, 64, 128, 1, 0),
+            (1, 1, 512, 512, 512, 1, 0),
         ])
 def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_width,
-        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
+        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable, ptp_ts_fmt_tod):
     dut = "mqnic_core_pcie_us"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -1017,6 +1018,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(axi_rtl_dir, "axi_vfifo_raw.v"),
@@ -1119,6 +1121,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
 
     # Interface configuration
     parameters['PTP_TS_ENABLE'] = ptp_ts_enable
+    parameters['PTP_TS_FMT_TOD'] = ptp_ts_fmt_tod
+    parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 48
     parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
     parameters['TX_CPL_FIFO_DEPTH'] = 32
     parameters['TX_TAG_WIDTH'] = 16
diff --git a/fpga/app/template/rtl/mqnic_app_block.v b/fpga/app/template/rtl/mqnic_app_block.v
index c220b63b9..ec40abff9 100644
--- a/fpga/app/template/rtl/mqnic_app_block.v
+++ b/fpga/app/template/rtl/mqnic_app_block.v
@@ -36,13 +36,14 @@ module mqnic_app_block #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 4,
     parameter PTP_CLK_PERIOD_NS_DENOM = 1,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_PORT_CDC_PIPELINE = 0,
     parameter PTP_PEROUT_ENABLE = 0,
     parameter PTP_PEROUT_COUNT = 1,
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     parameter TX_TAG_WIDTH = 16,
     parameter MAX_TX_SIZE = 9214,
     parameter MAX_RX_SIZE = 9214,
diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
index 574e84484..9cfc23671 100644
--- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
@@ -60,6 +60,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
@@ -158,6 +159,8 @@ export PARAM_TDMA_INDEX_WIDTH := 6
 
 # Interface configuration
 export PARAM_PTP_TS_ENABLE := 1
+export PARAM_PTP_TS_FMT_TOD := 0
+export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),48,96)
 export PARAM_TX_CPL_ENABLE := $(PARAM_PTP_TS_ENABLE)
 export PARAM_TX_CPL_FIFO_DEPTH := 32
 export PARAM_TX_TAG_WIDTH := 16
diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 08161a99a..c9a3af355 100644
--- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -753,18 +753,19 @@ async def run_test_nic(dut):
 
 
 @pytest.mark.parametrize(("if_count", "ports_per_if", "axis_pcie_data_width",
-        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
-            (1, 1, 256, 64, 64, 1),
-            (1, 1, 256, 64, 64, 0),
-            (2, 1, 256, 64, 64, 1),
-            (1, 2, 256, 64, 64, 1),
-            (1, 1, 256, 64, 128, 1),
-            (1, 1, 512, 64, 64, 1),
-            (1, 1, 512, 64, 128, 1),
-            (1, 1, 512, 512, 512, 1),
+        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable", "ptp_ts_fmt_tod"), [
+            (1, 1, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 64, 1, 1),
+            (1, 1, 256, 64, 64, 0, 0),
+            (2, 1, 256, 64, 64, 1, 0),
+            (1, 2, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 128, 1, 0),
+            (1, 1, 512, 64, 64, 1, 0),
+            (1, 1, 512, 64, 128, 1, 0),
+            (1, 1, 512, 512, 512, 1, 0),
         ])
 def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_width,
-        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
+        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable, ptp_ts_fmt_tod):
     dut = "mqnic_core_pcie_us"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -818,6 +819,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
@@ -917,6 +919,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
 
     # Interface configuration
     parameters['PTP_TS_ENABLE'] = ptp_ts_enable
+    parameters['PTP_TS_FMT_TOD'] = ptp_ts_fmt_tod
+    parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 48
     parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
     parameters['TX_CPL_FIFO_DEPTH'] = 32
     parameters['TX_TAG_WIDTH'] = 16
diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v
index 279768384..d5f601a44 100644
--- a/fpga/common/rtl/mqnic_core.v
+++ b/fpga/common/rtl/mqnic_core.v
@@ -46,7 +46,6 @@ module mqnic_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 4,
     parameter PTP_CLK_PERIOD_NS_DENOM = 1,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -81,6 +80,8 @@ module mqnic_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
@@ -413,8 +414,8 @@ module mqnic_core #
 
     input  wire [PORT_COUNT-1:0]                        tx_ptp_clk,
     input  wire [PORT_COUNT-1:0]                        tx_ptp_rst,
-    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]           tx_ptp_ts_tod,
-    output wire [PORT_COUNT-1:0]                        tx_ptp_ts_tod_step,
+    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]           tx_ptp_ts,
+    output wire [PORT_COUNT-1:0]                        tx_ptp_ts_step,
 
     output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0]        m_axis_tx_tdata,
     output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0]        m_axis_tx_tkeep,
@@ -441,8 +442,8 @@ module mqnic_core #
 
     input  wire [PORT_COUNT-1:0]                        rx_ptp_clk,
     input  wire [PORT_COUNT-1:0]                        rx_ptp_rst,
-    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]           rx_ptp_ts_tod,
-    output wire [PORT_COUNT-1:0]                        rx_ptp_ts_tod_step,
+    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]           rx_ptp_ts,
+    output wire [PORT_COUNT-1:0]                        rx_ptp_ts_step,
 
     input  wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0]        s_axis_rx_tdata,
     input  wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0]        s_axis_rx_tkeep,
@@ -3063,7 +3064,6 @@ generate
             // PTP configuration
             .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
             .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-            .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
             .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
             .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
@@ -3103,6 +3103,8 @@ generate
 
             // Interface configuration
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+            .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_CPL_ENABLE(TX_CPL_ENABLE),
             .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
             .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -3575,20 +3577,24 @@ generate
 
             wire [95:0] port_rx_ptp_ts_tod;
             wire port_rx_ptp_ts_tod_step;
+            wire [PTP_TS_WIDTH-1:0] port_rx_ptp_ts_rel;
+            wire port_rx_ptp_ts_rel_step;
 
             wire [95:0] port_tx_ptp_ts_tod;
             wire port_tx_ptp_ts_tod_step;
+            wire [PTP_TS_WIDTH-1:0] port_tx_ptp_ts_rel;
+            wire port_tx_ptp_ts_rel_step;
 
             if (PTP_TS_ENABLE) begin: ptp
 
                 // PTP CDC logic
                 ptp_td_leaf #(
-                    .TS_REL_EN(0),
-                    .TS_TOD_EN(1),
+                    .TS_REL_EN(!PTP_TS_FMT_TOD),
+                    .TS_TOD_EN(PTP_TS_FMT_TOD),
                     .TS_FNS_W(16),
-                    .TS_REL_NS_W(48),
+                    .TS_REL_NS_W(PTP_TS_WIDTH-16),
                     .TS_TOD_S_W(48),
-                    .TS_REL_W(64),
+                    .TS_REL_W(PTP_TS_WIDTH),
                     .TS_TOD_W(96),
                     .TD_SDI_PIPELINE(PTP_PORT_CDC_PIPELINE)
                 )
@@ -3607,8 +3613,8 @@ generate
                     /*
                      * Timestamp output
                      */
-                    .output_ts_rel(),
-                    .output_ts_rel_step(),
+                    .output_ts_rel(port_tx_ptp_ts_rel),
+                    .output_ts_rel_step(port_tx_ptp_ts_rel_step),
                     .output_ts_tod(port_tx_ptp_ts_tod),
                     .output_ts_tod_step(port_tx_ptp_ts_tod_step),
 
@@ -3625,12 +3631,12 @@ generate
                 );
 
                 ptp_td_leaf #(
-                    .TS_REL_EN(0),
-                    .TS_TOD_EN(1),
+                    .TS_REL_EN(!PTP_TS_FMT_TOD),
+                    .TS_TOD_EN(PTP_TS_FMT_TOD),
                     .TS_FNS_W(16),
-                    .TS_REL_NS_W(48),
+                    .TS_REL_NS_W(PTP_TS_WIDTH-16),
                     .TS_TOD_S_W(48),
-                    .TS_REL_W(64),
+                    .TS_REL_W(PTP_TS_WIDTH),
                     .TS_TOD_W(96),
                     .TD_SDI_PIPELINE(PTP_PORT_CDC_PIPELINE)
                 )
@@ -3649,8 +3655,8 @@ generate
                     /*
                      * Timestamp output
                      */
-                    .output_ts_rel(),
-                    .output_ts_rel_step(),
+                    .output_ts_rel(port_rx_ptp_ts_rel),
+                    .output_ts_rel_step(port_rx_ptp_ts_rel_step),
                     .output_ts_tod(port_rx_ptp_ts_tod),
                     .output_ts_tod_step(port_rx_ptp_ts_tod_step),
 
@@ -3670,17 +3676,20 @@ generate
 
                 assign port_tx_ptp_ts_tod = 0;
                 assign port_tx_ptp_ts_tod_step = 1'b0;
+                assign port_tx_ptp_ts_rel = 0;
+                assign port_tx_ptp_ts_rel_step = 1'b0;
 
                 assign port_rx_ptp_ts_tod = 0;
                 assign port_rx_ptp_ts_tod_step = 1'b0;
+                assign port_rx_ptp_ts_rel = 0;
+                assign port_rx_ptp_ts_rel_step = 1'b0;
 
             end
 
-            assign tx_ptp_ts_tod[(n*PORTS_PER_IF+m)*96 +: 96] = port_tx_ptp_ts_tod;
-            assign tx_ptp_ts_tod_step[n*PORTS_PER_IF+m] = port_tx_ptp_ts_tod_step;
-
-            assign rx_ptp_ts_tod[(n*PORTS_PER_IF+m)*96 +: 96] = port_rx_ptp_ts_tod;
-            assign rx_ptp_ts_tod_step[n*PORTS_PER_IF+m] = port_rx_ptp_ts_tod_step;
+            assign tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = PTP_TS_FMT_TOD ? port_tx_ptp_ts_tod : port_tx_ptp_ts_rel;
+            assign tx_ptp_ts_step[n*PORTS_PER_IF+m +: 1] = PTP_TS_FMT_TOD ? port_tx_ptp_ts_tod_step : port_tx_ptp_ts_rel_step;
+            assign rx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = PTP_TS_FMT_TOD ? port_rx_ptp_ts_tod : port_rx_ptp_ts_rel;
+            assign rx_ptp_ts_step[n*PORTS_PER_IF+m +: 1] = PTP_TS_FMT_TOD ? port_rx_ptp_ts_tod_step : port_rx_ptp_ts_rel_step;
 
         end
 
@@ -3707,13 +3716,14 @@ if (APP_ENABLE) begin : app
         // PTP configuration
         .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
         .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-        .PTP_TS_WIDTH(PTP_TS_WIDTH),
         .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
         .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
         .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
 
         // Interface configuration
         .PTP_TS_ENABLE(PTP_TS_ENABLE),
+        .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+        .PTP_TS_WIDTH(PTP_TS_WIDTH),
         .TX_TAG_WIDTH(TX_TAG_WIDTH),
         .MAX_TX_SIZE(MAX_TX_SIZE),
         .MAX_RX_SIZE(MAX_RX_SIZE),
diff --git a/fpga/common/rtl/mqnic_core_axi.v b/fpga/common/rtl/mqnic_core_axi.v
index e5df87460..0f7133f2f 100644
--- a/fpga/common/rtl/mqnic_core_axi.v
+++ b/fpga/common/rtl/mqnic_core_axi.v
@@ -46,7 +46,6 @@ module mqnic_core_axi #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 4,
     parameter PTP_CLK_PERIOD_NS_DENOM = 1,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -81,6 +80,8 @@ module mqnic_core_axi #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
@@ -375,8 +376,8 @@ module mqnic_core_axi #
 
     input  wire [PORT_COUNT-1:0]                      tx_ptp_clk,
     input  wire [PORT_COUNT-1:0]                      tx_ptp_rst,
-    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]         tx_ptp_ts_tod,
-    output wire [PORT_COUNT-1:0]                      tx_ptp_ts_tod_step,
+    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]         tx_ptp_ts,
+    output wire [PORT_COUNT-1:0]                      tx_ptp_ts_step,
 
     output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0]      m_axis_tx_tdata,
     output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0]      m_axis_tx_tkeep,
@@ -403,8 +404,8 @@ module mqnic_core_axi #
 
     input  wire [PORT_COUNT-1:0]                      rx_ptp_clk,
     input  wire [PORT_COUNT-1:0]                      rx_ptp_rst,
-    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]         rx_ptp_ts_tod,
-    output wire [PORT_COUNT-1:0]                      rx_ptp_ts_tod_step,
+    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]         rx_ptp_ts,
+    output wire [PORT_COUNT-1:0]                      rx_ptp_ts_step,
 
     input  wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0]      s_axis_rx_tdata,
     input  wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0]      s_axis_rx_tkeep,
@@ -991,7 +992,6 @@ mqnic_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -1026,6 +1026,8 @@ mqnic_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(TX_CPL_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1332,8 +1334,8 @@ core_inst (
 
     .tx_ptp_clk(tx_ptp_clk),
     .tx_ptp_rst(tx_ptp_rst),
-    .tx_ptp_ts_tod(tx_ptp_ts_tod),
-    .tx_ptp_ts_tod_step(tx_ptp_ts_tod_step),
+    .tx_ptp_ts(tx_ptp_ts),
+    .tx_ptp_ts_step(tx_ptp_ts_step),
 
     .m_axis_tx_tdata(m_axis_tx_tdata),
     .m_axis_tx_tkeep(m_axis_tx_tkeep),
@@ -1360,8 +1362,8 @@ core_inst (
 
     .rx_ptp_clk(rx_ptp_clk),
     .rx_ptp_rst(rx_ptp_rst),
-    .rx_ptp_ts_tod(rx_ptp_ts_tod),
-    .rx_ptp_ts_tod_step(rx_ptp_ts_tod_step),
+    .rx_ptp_ts(rx_ptp_ts),
+    .rx_ptp_ts_step(rx_ptp_ts_step),
 
     .s_axis_rx_tdata(s_axis_rx_tdata),
     .s_axis_rx_tkeep(s_axis_rx_tkeep),
diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v
index a9b5886b9..7b1bc173a 100644
--- a/fpga/common/rtl/mqnic_core_pcie.v
+++ b/fpga/common/rtl/mqnic_core_pcie.v
@@ -46,7 +46,6 @@ module mqnic_core_pcie #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 4,
     parameter PTP_CLK_PERIOD_NS_DENOM = 1,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -81,6 +80,8 @@ module mqnic_core_pcie #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
@@ -392,8 +393,8 @@ module mqnic_core_pcie #
 
     input  wire [PORT_COUNT-1:0]                         tx_ptp_clk,
     input  wire [PORT_COUNT-1:0]                         tx_ptp_rst,
-    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            tx_ptp_ts_tod,
-    output wire [PORT_COUNT-1:0]                         tx_ptp_ts_tod_step,
+    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            tx_ptp_ts,
+    output wire [PORT_COUNT-1:0]                         tx_ptp_ts_step,
 
     output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0]         m_axis_tx_tdata,
     output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0]         m_axis_tx_tkeep,
@@ -420,8 +421,8 @@ module mqnic_core_pcie #
 
     input  wire [PORT_COUNT-1:0]                         rx_ptp_clk,
     input  wire [PORT_COUNT-1:0]                         rx_ptp_rst,
-    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            rx_ptp_ts_tod,
-    output wire [PORT_COUNT-1:0]                         rx_ptp_ts_tod_step,
+    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            rx_ptp_ts,
+    output wire [PORT_COUNT-1:0]                         rx_ptp_ts_step,
 
     input  wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0]         s_axis_rx_tdata,
     input  wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0]         s_axis_rx_tkeep,
@@ -1623,7 +1624,6 @@ mqnic_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -1658,6 +1658,8 @@ mqnic_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(TX_CPL_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1988,8 +1990,8 @@ core_inst (
 
     .tx_ptp_clk(tx_ptp_clk),
     .tx_ptp_rst(tx_ptp_rst),
-    .tx_ptp_ts_tod(tx_ptp_ts_tod),
-    .tx_ptp_ts_tod_step(tx_ptp_ts_tod_step),
+    .tx_ptp_ts(tx_ptp_ts),
+    .tx_ptp_ts_step(tx_ptp_ts_step),
 
     .m_axis_tx_tdata(m_axis_tx_tdata),
     .m_axis_tx_tkeep(m_axis_tx_tkeep),
@@ -2016,8 +2018,8 @@ core_inst (
 
     .rx_ptp_clk(rx_ptp_clk),
     .rx_ptp_rst(rx_ptp_rst),
-    .rx_ptp_ts_tod(rx_ptp_ts_tod),
-    .rx_ptp_ts_tod_step(rx_ptp_ts_tod_step),
+    .rx_ptp_ts(rx_ptp_ts),
+    .rx_ptp_ts_step(rx_ptp_ts_step),
 
     .s_axis_rx_tdata(s_axis_rx_tdata),
     .s_axis_rx_tkeep(s_axis_rx_tkeep),
diff --git a/fpga/common/rtl/mqnic_core_pcie_ptile.v b/fpga/common/rtl/mqnic_core_pcie_ptile.v
index d55446d09..d4a074cf2 100644
--- a/fpga/common/rtl/mqnic_core_pcie_ptile.v
+++ b/fpga/common/rtl/mqnic_core_pcie_ptile.v
@@ -46,7 +46,6 @@ module mqnic_core_pcie_ptile #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 4,
     parameter PTP_CLK_PERIOD_NS_DENOM = 1,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -81,6 +80,8 @@ module mqnic_core_pcie_ptile #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
@@ -340,8 +341,8 @@ module mqnic_core_pcie_ptile #
 
     input  wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk,
     input  wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst,
-    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod,
-    output wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step,
+    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts,
+    output wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step,
 
     output wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     m_axis_eth_tx_tdata,
     output wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     m_axis_eth_tx_tkeep,
@@ -368,8 +369,8 @@ module mqnic_core_pcie_ptile #
 
     input  wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk,
     input  wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst,
-    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod,
-    output wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step,
+    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts,
+    output wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step,
 
     input  wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     s_axis_eth_rx_tdata,
     input  wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     s_axis_eth_rx_tkeep,
@@ -785,7 +786,6 @@ mqnic_core_pcie #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -820,6 +820,8 @@ mqnic_core_pcie #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(TX_CPL_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1129,8 +1131,8 @@ core_pcie_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_tx_tdata(m_axis_eth_tx_tdata),
     .m_axis_tx_tkeep(m_axis_eth_tx_tkeep),
@@ -1157,8 +1159,8 @@ core_pcie_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_rx_tdata(s_axis_eth_rx_tdata),
     .s_axis_rx_tkeep(s_axis_eth_rx_tkeep),
diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v
index da2393364..9bfaf3da5 100644
--- a/fpga/common/rtl/mqnic_core_pcie_s10.v
+++ b/fpga/common/rtl/mqnic_core_pcie_s10.v
@@ -46,7 +46,6 @@ module mqnic_core_pcie_s10 #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 4,
     parameter PTP_CLK_PERIOD_NS_DENOM = 1,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -81,6 +80,8 @@ module mqnic_core_pcie_s10 #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
@@ -336,8 +337,8 @@ module mqnic_core_pcie_s10 #
 
     input  wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk,
     input  wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst,
-    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod,
-    output wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step,
+    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts,
+    output wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step,
 
     output wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     m_axis_eth_tx_tdata,
     output wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     m_axis_eth_tx_tkeep,
@@ -364,8 +365,8 @@ module mqnic_core_pcie_s10 #
 
     input  wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk,
     input  wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst,
-    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod,
-    output wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step,
+    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts,
+    output wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step,
 
     input  wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     s_axis_eth_rx_tdata,
     input  wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     s_axis_eth_rx_tkeep,
@@ -794,7 +795,6 @@ mqnic_core_pcie #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -829,6 +829,8 @@ mqnic_core_pcie #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(TX_CPL_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1138,8 +1140,8 @@ core_pcie_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_tx_tdata(m_axis_eth_tx_tdata),
     .m_axis_tx_tkeep(m_axis_eth_tx_tkeep),
@@ -1166,8 +1168,8 @@ core_pcie_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_rx_tdata(s_axis_eth_rx_tdata),
     .s_axis_rx_tkeep(s_axis_eth_rx_tkeep),
diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v
index ce4270137..e13343136 100644
--- a/fpga/common/rtl/mqnic_core_pcie_us.v
+++ b/fpga/common/rtl/mqnic_core_pcie_us.v
@@ -46,7 +46,6 @@ module mqnic_core_pcie_us #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 4,
     parameter PTP_CLK_PERIOD_NS_DENOM = 1,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -81,6 +80,8 @@ module mqnic_core_pcie_us #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
@@ -396,8 +397,8 @@ module mqnic_core_pcie_us #
 
     input  wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk,
     input  wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst,
-    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod,
-    output wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step,
+    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts,
+    output wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step,
 
     output wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     m_axis_eth_tx_tdata,
     output wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     m_axis_eth_tx_tkeep,
@@ -424,8 +425,8 @@ module mqnic_core_pcie_us #
 
     input  wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk,
     input  wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst,
-    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod,
-    output wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step,
+    output wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts,
+    output wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step,
 
     input  wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     s_axis_eth_rx_tdata,
     input  wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     s_axis_eth_rx_tkeep,
@@ -914,7 +915,6 @@ mqnic_core_pcie #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -949,6 +949,8 @@ mqnic_core_pcie #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(TX_CPL_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1258,8 +1260,8 @@ core_pcie_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_tx_tdata(m_axis_eth_tx_tdata),
     .m_axis_tx_tkeep(m_axis_eth_tx_tkeep),
@@ -1286,8 +1288,8 @@ core_pcie_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_rx_tdata(s_axis_eth_rx_tdata),
     .s_axis_rx_tkeep(s_axis_eth_rx_tkeep),
diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v
index ce87bf474..94e94bc33 100644
--- a/fpga/common/rtl/mqnic_interface.v
+++ b/fpga/common/rtl/mqnic_interface.v
@@ -25,7 +25,6 @@ module mqnic_interface #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 4,
     parameter PTP_CLK_PERIOD_NS_DENOM = 1,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PEROUT_ENABLE = 0,
     parameter PTP_PEROUT_COUNT = 1,
@@ -65,6 +64,8 @@ module mqnic_interface #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
@@ -2524,9 +2525,6 @@ mqnic_interface_tx #(
     // Structural configuration
     .PORTS(PORTS),
 
-    // PTP configuration
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
-
     // Queue manager configuration
     .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
     .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
@@ -2552,6 +2550,8 @@ mqnic_interface_tx #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
     .MAX_TX_SIZE(MAX_TX_SIZE),
@@ -2699,6 +2699,13 @@ interface_tx_inst (
     .s_axis_tx_cpl_valid(if_tx_cpl_valid),
     .s_axis_tx_cpl_ready(if_tx_cpl_ready),
 
+    /*
+     * PTP clock
+     */
+    .ptp_clk(ptp_clk),
+    .ptp_rst(ptp_rst),
+    .ptp_td_sd(ptp_td_sd),
+
     /*
      * Configuration
      */
@@ -2722,9 +2729,6 @@ mqnic_interface_rx #(
     // Structural configuration
     .PORTS(PORTS),
 
-    // PTP configuration
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
-
     // Queue manager configuration
     .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
     .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH),
@@ -2750,6 +2754,8 @@ mqnic_interface_rx #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .RX_HASH_ENABLE(RX_HASH_ENABLE),
     .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
     .MAX_RX_SIZE(MAX_RX_SIZE),
@@ -2914,6 +2920,13 @@ interface_rx_inst (
     .s_axis_rx_tdest(if_rx_axis_tdest),
     .s_axis_rx_tuser(if_rx_axis_tuser),
 
+    /*
+     * PTP clock
+     */
+    .ptp_clk(ptp_clk),
+    .ptp_rst(ptp_rst),
+    .ptp_td_sd(ptp_td_sd),
+
     /*
      * Configuration
      */
diff --git a/fpga/common/rtl/mqnic_interface_rx.v b/fpga/common/rtl/mqnic_interface_rx.v
index d993b2bd6..c6356ae72 100644
--- a/fpga/common/rtl/mqnic_interface_rx.v
+++ b/fpga/common/rtl/mqnic_interface_rx.v
@@ -17,9 +17,6 @@ module mqnic_interface_rx #
     // Structural configuration
     parameter PORTS = 1,
 
-    // PTP configuration
-    parameter PTP_TS_WIDTH = 96,
-
     // Queue manager configuration (interface)
     parameter RX_QUEUE_INDEX_WIDTH = 8,
     parameter QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
@@ -45,6 +42,8 @@ module mqnic_interface_rx #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     parameter RX_HASH_ENABLE = 1,
     parameter RX_CHECKSUM_ENABLE = 1,
     parameter MAX_RX_SIZE = 9214,
@@ -209,6 +208,13 @@ module mqnic_interface_rx #
     input  wire [AXIS_RX_DEST_WIDTH-1:0]                s_axis_rx_tdest,
     input  wire [AXIS_RX_USER_WIDTH-1:0]                s_axis_rx_tuser,
 
+    /*
+     * PTP clock
+     */
+    input  wire                                         ptp_clk,
+    input  wire                                         ptp_rst,
+    input  wire                                         ptp_td_sd,
+
     /*
      * Configuration
      */
@@ -354,6 +360,7 @@ rx_engine #(
     .AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
     .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
     .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .RX_HASH_ENABLE(RX_HASH_ENABLE),
     .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
@@ -517,6 +524,13 @@ rx_engine_inst (
     .s_axis_rx_csum_valid(rx_csum_valid),
     .s_axis_rx_csum_ready(rx_csum_ready),
 
+    /*
+     * PTP clock
+     */
+    .ptp_clk(ptp_clk),
+    .ptp_rst(ptp_rst),
+    .ptp_td_sd(ptp_td_sd),
+
     /*
      * Configuration
      */
diff --git a/fpga/common/rtl/mqnic_interface_tx.v b/fpga/common/rtl/mqnic_interface_tx.v
index 066b41a61..06d9627af 100644
--- a/fpga/common/rtl/mqnic_interface_tx.v
+++ b/fpga/common/rtl/mqnic_interface_tx.v
@@ -17,9 +17,6 @@ module mqnic_interface_tx #
     // Structural configuration
     parameter PORTS = 1,
 
-    // PTP configuration
-    parameter PTP_TS_WIDTH = 96,
-
     // Queue manager configuration
     parameter TX_QUEUE_INDEX_WIDTH = 13,
     parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
@@ -45,6 +42,8 @@ module mqnic_interface_tx #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
     parameter TX_CHECKSUM_ENABLE = 1,
     parameter MAX_TX_SIZE = 9214,
@@ -192,6 +191,13 @@ module mqnic_interface_tx #
     input  wire                                         s_axis_tx_cpl_valid,
     output wire                                         s_axis_tx_cpl_ready,
 
+    /*
+     * PTP clock
+     */
+    input  wire                                         ptp_clk,
+    input  wire                                         ptp_rst,
+    input  wire                                         ptp_td_sd,
+
     /*
      * Configuration
      */
@@ -295,6 +301,7 @@ tx_engine #(
     .AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
     .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
     .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
@@ -432,6 +439,13 @@ tx_engine_inst (
     .s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
     .s_axis_tx_cpl_ready(s_axis_tx_cpl_ready),
 
+    /*
+     * PTP clock
+     */
+    .ptp_clk(ptp_clk),
+    .ptp_rst(ptp_rst),
+    .ptp_td_sd(ptp_td_sd),
+
     /*
      * Configuration
      */
diff --git a/fpga/common/rtl/rx_engine.v b/fpga/common/rtl/rx_engine.v
index c82652624..c669b650c 100644
--- a/fpga/common/rtl/rx_engine.v
+++ b/fpga/common/rtl/rx_engine.v
@@ -66,8 +66,10 @@ module rx_engine #
     parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
     // Enable PTP timestamping
     parameter PTP_TS_ENABLE = 1,
+    // PTP timestamp format
+    parameter PTP_TS_FMT_TOD = 1,
     // PTP timestamp width
-    parameter PTP_TS_WIDTH = 96,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     // Enable RX hashing
     parameter RX_HASH_ENABLE = 1,
     // Enable RX checksum offload
@@ -244,6 +246,13 @@ module rx_engine #
     input  wire                             s_axis_rx_csum_valid,
     output wire                             s_axis_rx_csum_ready,
 
+    /*
+     * PTP clock
+     */
+    input  wire                             ptp_clk,
+    input  wire                             ptp_rst,
+    input  wire                             ptp_td_sd,
+
     /*
      * Configuration
      */
@@ -361,7 +370,7 @@ reg [AXIS_RX_ID_WIDTH-1:0] desc_table_id[DESC_TABLE_SIZE-1:0];
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
 reg [CL_RX_BUFFER_SIZE+1-1:0] desc_table_buf_ptr[DESC_TABLE_SIZE-1:0];
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-reg [PTP_TS_WIDTH-1:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0];
+reg [95:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0];
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
 reg [31:0] desc_table_hash[DESC_TABLE_SIZE-1:0];
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
@@ -382,10 +391,12 @@ reg desc_table_start_en;
 reg [CL_DESC_TABLE_SIZE-1:0] desc_table_rx_finish_ptr;
 reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_rx_finish_len;
 reg [AXIS_RX_ID_WIDTH-1:0] desc_table_rx_finish_id;
-reg [PTP_TS_WIDTH-1:0] desc_table_rx_finish_ptp_ts;
 reg [31:0] desc_table_rx_finish_hash;
 reg [3:0] desc_table_rx_finish_hash_type;
 reg desc_table_rx_finish_en;
+reg [CL_DESC_TABLE_SIZE-1:0] desc_table_store_ts_ptr;
+reg [95:0] desc_table_store_ts_ptp_ts;
+reg desc_table_store_ts_en;
 reg [CL_DESC_TABLE_SIZE-1:0] desc_table_store_queue_ptr;
 reg [QUEUE_INDEX_WIDTH-1:0] desc_table_store_queue;
 reg desc_table_store_queue_en;
@@ -566,6 +577,55 @@ mqnic_rx_queue_map_inst (
     .resp_valid(queue_map_resp_valid)
 );
 
+wire [DMA_CLIENT_TAG_WIDTH-1:0] rx_ts_tag;
+wire [95:0] rx_ts_tod;
+wire rx_ts_valid;
+
+generate
+
+if (!PTP_TS_FMT_TOD) begin : rel2tod
+
+    ptp_td_rel2tod #(
+        .TS_FNS_W(16),
+        .TS_REL_NS_W(32),
+        .TS_TOD_S_W(48),
+        .TS_REL_W(48),
+        .TS_TOD_W(96),
+        .TS_TAG_W(DMA_CLIENT_TAG_WIDTH),
+        .TD_SDI_PIPELINE(2)
+    )
+    rel2tod_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * PTP clock interface
+         */
+        .ptp_clk(ptp_clk),
+        .ptp_rst(ptp_rst),
+        .ptp_td_sdi(ptp_td_sd),
+
+        /*
+         * Timestamp conversion
+         */
+        .input_ts_rel(s_axis_rx_desc_status_user >> TUSER_PTP_TS_OFFSET),
+        .input_ts_tag(s_axis_rx_desc_status_tag),
+        .input_ts_valid(s_axis_rx_desc_status_valid),
+        .output_ts_tod(rx_ts_tod),
+        .output_ts_tag(rx_ts_tag),
+        .output_ts_valid(rx_ts_valid)
+    );
+
+end else begin
+
+    assign rx_ts_tod = s_axis_rx_desc_status_user >> TUSER_PTP_TS_OFFSET;
+    assign rx_ts_tag = s_axis_rx_desc_status_tag;
+    assign rx_ts_valid = s_axis_rx_desc_status_valid;
+
+end
+
+endgenerate
+
 integer i;
 
 initial begin
@@ -632,10 +692,12 @@ always @* begin
     desc_table_rx_finish_ptr = s_axis_rx_desc_status_tag;
     desc_table_rx_finish_len = s_axis_rx_desc_status_len;
     desc_table_rx_finish_id = s_axis_rx_desc_status_id;
-    desc_table_rx_finish_ptp_ts = s_axis_rx_desc_status_user >> TUSER_PTP_TS_OFFSET;
     desc_table_rx_finish_hash = s_axis_rx_desc_status_user >> TUSER_HASH_OFFSET;
     desc_table_rx_finish_hash_type = s_axis_rx_desc_status_user >> TUSER_HASH_TYPE_OFFSET;
     desc_table_rx_finish_en = 1'b0;
+    desc_table_store_ts_ptr = rx_ts_tag;
+    desc_table_store_ts_ptp_ts = rx_ts_tod;
+    desc_table_store_ts_en = 1'b0;
     desc_table_store_queue_ptr = queue_map_resp_tag;
     desc_table_store_queue = queue_map_resp_queue;
     desc_table_store_queue_en = 1'b0;
@@ -707,12 +769,18 @@ always @* begin
         desc_table_rx_finish_ptr = s_axis_rx_desc_status_tag;
         desc_table_rx_finish_len = s_axis_rx_desc_status_len;
         desc_table_rx_finish_id = s_axis_rx_desc_status_id;
-        desc_table_rx_finish_ptp_ts = s_axis_rx_desc_status_user >> TUSER_PTP_TS_OFFSET;
         desc_table_rx_finish_hash = s_axis_rx_desc_status_user >> TUSER_HASH_OFFSET;
         desc_table_rx_finish_hash_type = s_axis_rx_desc_status_user >> TUSER_HASH_TYPE_OFFSET;
         desc_table_rx_finish_en = 1'b1;
     end
 
+    // store PTP TS
+    if (rx_ts_valid) begin
+        desc_table_store_ts_ptr = rx_ts_tag;
+        desc_table_store_ts_ptp_ts = rx_ts_tod;
+        desc_table_store_ts_en = 1'b1;
+    end
+
     // store queue
     if (queue_map_resp_valid) begin
         desc_table_store_queue_ptr = queue_map_resp_tag;
@@ -974,11 +1042,14 @@ always @(posedge clk) begin
     if (desc_table_rx_finish_en) begin
         desc_table_dma_len[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_len;
         desc_table_id[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_id;
-        desc_table_ptp_ts[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_ptp_ts;
         desc_table_hash[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_hash;
         desc_table_hash_type[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_hash_type;
     end
 
+    if (desc_table_store_ts_en) begin
+        desc_table_ptp_ts[desc_table_store_ts_ptr & DESC_PTR_MASK] <= desc_table_store_ts_ptp_ts;
+    end
+
     if (desc_table_store_queue_en) begin
         desc_table_queue[desc_table_store_queue_ptr & DESC_PTR_MASK] <= desc_table_store_queue;
         desc_table_rx_done[desc_table_store_queue_ptr & DESC_PTR_MASK] <= 1'b1;
diff --git a/fpga/common/rtl/tx_engine.v b/fpga/common/rtl/tx_engine.v
index 70e98213f..c5d6d97d2 100644
--- a/fpga/common/rtl/tx_engine.v
+++ b/fpga/common/rtl/tx_engine.v
@@ -64,8 +64,10 @@ module tx_engine #
     parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
     // Enable PTP timestamping
     parameter PTP_TS_ENABLE = 1,
+    // PTP timestamp format
+    parameter PTP_TS_FMT_TOD = 1,
     // PTP timestamp width
-    parameter PTP_TS_WIDTH = 96,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
     // Transmit tag width
     parameter TX_TAG_WIDTH = 16,
     // Enable TX checksum offload
@@ -207,6 +209,13 @@ module tx_engine #
     input  wire                             s_axis_tx_cpl_valid,
     output wire                             s_axis_tx_cpl_ready,
 
+    /*
+     * PTP clock
+     */
+    input  wire                             ptp_clk,
+    input  wire                             ptp_rst,
+    input  wire                             ptp_td_sd,
+
     /*
      * Configuration
      */
@@ -297,8 +306,6 @@ reg [7:0] m_axis_tx_csum_cmd_csum_start_reg = 7'd0, m_axis_tx_csum_cmd_csum_star
 reg [7:0] m_axis_tx_csum_cmd_csum_offset_reg = 7'd0, m_axis_tx_csum_cmd_csum_offset_next;
 reg m_axis_tx_csum_cmd_valid_reg = 1'b0, m_axis_tx_csum_cmd_valid_next;
 
-reg s_axis_tx_cpl_ready_reg = 1'b0, s_axis_tx_cpl_ready_next;
-
 reg [CL_TX_BUFFER_SIZE+1-1:0] buf_wr_ptr_reg = 0, buf_wr_ptr_next;
 reg [CL_TX_BUFFER_SIZE+1-1:0] buf_rd_ptr_reg = 0, buf_rd_ptr_next;
 
@@ -340,7 +347,7 @@ reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_len[DESC_TABLE_SIZE-1:0];
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
 reg [CL_TX_BUFFER_SIZE+1-1:0] desc_table_buf_ptr[DESC_TABLE_SIZE-1:0];
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-reg [PTP_TS_WIDTH-1:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0];
+reg [95:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0];
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
 reg desc_table_read_commit[DESC_TABLE_SIZE-1:0];
 (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
@@ -374,7 +381,7 @@ reg desc_table_tx_start_en;
 reg [CL_DESC_TABLE_SIZE-1:0] desc_table_tx_dma_finish_ptr;
 reg desc_table_tx_dma_finish_en;
 reg [CL_DESC_TABLE_SIZE-1:0] desc_table_tx_finish_ptr;
-reg [PTP_TS_WIDTH-1:0] desc_table_tx_finish_ts;
+reg [95:0] desc_table_tx_finish_ts;
 reg desc_table_tx_finish_en;
 reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_cpl_enqueue_start_ptr_reg = 0;
 reg desc_table_cpl_enqueue_start_en;
@@ -438,7 +445,7 @@ assign m_axis_tx_csum_cmd_csum_start = m_axis_tx_csum_cmd_csum_start_reg;
 assign m_axis_tx_csum_cmd_csum_offset = m_axis_tx_csum_cmd_csum_offset_reg;
 assign m_axis_tx_csum_cmd_valid = m_axis_tx_csum_cmd_valid_reg;
 
-assign s_axis_tx_cpl_ready = s_axis_tx_cpl_ready_reg;
+assign s_axis_tx_cpl_ready = 1'b1;
 
 // reg [15:0] stall_cnt = 0;
 // wire stalled = stall_cnt[12];
@@ -475,6 +482,55 @@ assign s_axis_tx_cpl_ready = s_axis_tx_cpl_ready_reg;
 //     .probe5(0)
 // );
 
+wire [TX_TAG_WIDTH-1:0] tx_cpl_tag;
+wire [95:0] tx_cpl_ts;
+wire tx_cpl_valid;
+
+generate
+
+if (!PTP_TS_FMT_TOD) begin : rel2tod
+
+    ptp_td_rel2tod #(
+        .TS_FNS_W(16),
+        .TS_REL_NS_W(32),
+        .TS_TOD_S_W(48),
+        .TS_REL_W(48),
+        .TS_TOD_W(96),
+        .TS_TAG_W(TX_TAG_WIDTH),
+        .TD_SDI_PIPELINE(2)
+    )
+    rel2tod_inst (
+        .clk(clk),
+        .rst(rst),
+
+        /*
+         * PTP clock interface
+         */
+        .ptp_clk(ptp_clk),
+        .ptp_rst(ptp_rst),
+        .ptp_td_sdi(ptp_td_sd),
+
+        /*
+         * Timestamp conversion
+         */
+        .input_ts_rel(s_axis_tx_cpl_ts),
+        .input_ts_tag(s_axis_tx_cpl_tag),
+        .input_ts_valid(s_axis_tx_cpl_valid),
+        .output_ts_tod(tx_cpl_ts),
+        .output_ts_tag(tx_cpl_tag),
+        .output_ts_valid(tx_cpl_valid)
+    );
+
+end else begin
+
+    assign tx_cpl_tag = s_axis_tx_cpl_tag;
+    assign tx_cpl_ts = s_axis_tx_cpl_ts;
+    assign tx_cpl_valid = s_axis_tx_cpl_valid;
+
+end
+
+endgenerate
+
 integer i;
 
 initial begin
@@ -539,8 +595,6 @@ always @* begin
     m_axis_tx_csum_cmd_csum_offset_next = m_axis_tx_csum_cmd_csum_offset_reg;
     m_axis_tx_csum_cmd_valid_next = m_axis_tx_csum_cmd_valid_reg && !m_axis_tx_csum_cmd_ready;
 
-    s_axis_tx_cpl_ready_next = 1'b0;
-
     buf_wr_ptr_next = buf_wr_ptr_reg;
     buf_rd_ptr_next = buf_rd_ptr_reg;
 
@@ -580,8 +634,8 @@ always @* begin
     desc_table_tx_start_en = 1'b0;
     desc_table_tx_dma_finish_ptr = s_axis_tx_desc_status_tag;
     desc_table_tx_dma_finish_en = 1'b0;
-    desc_table_tx_finish_ptr = s_axis_tx_cpl_tag;
-    desc_table_tx_finish_ts = s_axis_tx_cpl_ts;
+    desc_table_tx_finish_ptr = tx_cpl_tag;
+    desc_table_tx_finish_ts = tx_cpl_ts;
     desc_table_tx_finish_en = 1'b0;
     desc_table_cpl_enqueue_start_en = 1'b0;
     desc_table_cpl_write_done_ptr = s_axis_cpl_req_status_tag & DESC_PTR_MASK;
@@ -783,10 +837,9 @@ always @* begin
 
     // transmit done
     // wait for transmit completion; store PTP timestamp
-    s_axis_tx_cpl_ready_next = 1'b1;
-    if (s_axis_tx_cpl_valid && s_axis_tx_cpl_tag[TX_TAG_WIDTH-1]) begin
-        desc_table_tx_finish_ptr = s_axis_tx_cpl_tag;
-        desc_table_tx_finish_ts = s_axis_tx_cpl_ts;
+    if (tx_cpl_valid && tx_cpl_tag[TX_TAG_WIDTH-1]) begin
+        desc_table_tx_finish_ptr = tx_cpl_tag;
+        desc_table_tx_finish_ts = tx_cpl_ts;
         desc_table_tx_finish_en = 1'b1;
     end
 
@@ -876,7 +929,6 @@ always @(posedge clk) begin
     m_axis_tx_desc_user_reg <= m_axis_tx_desc_user_next;
     m_axis_tx_desc_valid_reg <= m_axis_tx_desc_valid_next;
 
-    s_axis_tx_cpl_ready_reg <= s_axis_tx_cpl_ready_next;
 
     m_axis_tx_csum_cmd_csum_enable_reg <= m_axis_tx_csum_cmd_csum_enable_next;
     m_axis_tx_csum_cmd_csum_start_reg <= m_axis_tx_csum_cmd_csum_start_next;
@@ -981,7 +1033,6 @@ always @(posedge clk) begin
         s_axis_desc_tready_reg <= 1'b0;
         m_axis_cpl_req_valid_reg <= 1'b0;
         m_axis_tx_desc_valid_reg <= 1'b0;
-        s_axis_tx_cpl_ready_reg <= 1'b0;
         m_axis_tx_csum_cmd_valid_reg <= 1'b0;
 
         buf_wr_ptr_reg <= 0;
diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile
index 1e61c1e99..895f59673 100644
--- a/fpga/common/tb/mqnic_core_axi/Makefile
+++ b/fpga/common/tb/mqnic_core_axi/Makefile
@@ -58,6 +58,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
@@ -142,6 +143,8 @@ export PARAM_TDMA_INDEX_WIDTH := 6
 
 # Interface configuration
 export PARAM_PTP_TS_ENABLE := 1
+export PARAM_PTP_TS_FMT_TOD := 0
+export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),48,96)
 export PARAM_TX_CPL_ENABLE := $(PARAM_PTP_TS_ENABLE)
 export PARAM_TX_CPL_FIFO_DEPTH := 32
 export PARAM_TX_TAG_WIDTH := 16
diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
index 6de7a638b..7bd3af1d2 100644
--- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
+++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
@@ -90,14 +90,14 @@ def __init__(self, dut):
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
                     tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
-                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
+                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_tx_ptp_ts_rel,
                     tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
                     tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
                     tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
                     rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
-                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
+                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_rx_ptp_ts_rel,
                     ifg=12, speed=eth_speed
                 )
 
@@ -545,15 +545,16 @@ async def run_test_nic(dut):
 
 
 @pytest.mark.parametrize(("if_count", "ports_per_if", "axi_data_width",
-        "axis_data_width", "axis_sync_data_width", "ptp_ts_enable"), [
-            (1, 1, 128, 64, 64, 1),
-            (1, 1, 128, 64, 64, 0),
-            (2, 1, 128, 64, 64, 1),
-            (1, 2, 128, 64, 64, 1),
-            (1, 1, 128, 64, 128, 1),
+        "axis_data_width", "axis_sync_data_width", "ptp_ts_enable", "ptp_ts_fmt_tod"), [
+            (1, 1, 128, 64, 64, 1, 0),
+            (1, 1, 128, 64, 64, 1, 1),
+            (1, 1, 128, 64, 64, 0, 0),
+            (2, 1, 128, 64, 64, 1, 0),
+            (1, 2, 128, 64, 64, 1, 0),
+            (1, 1, 128, 64, 128, 1, 0),
         ])
 def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width,
-        axis_data_width, axis_sync_data_width, ptp_ts_enable):
+        axis_data_width, axis_sync_data_width, ptp_ts_enable, ptp_ts_fmt_tod):
     dut = "mqnic_core_axi"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -605,6 +606,7 @@ def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width,
         os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
@@ -690,6 +692,8 @@ def test_mqnic_core_axi(request, if_count, ports_per_if, axi_data_width,
 
     # Interface configuration
     parameters['PTP_TS_ENABLE'] = ptp_ts_enable
+    parameters['PTP_TS_FMT_TOD'] = ptp_ts_fmt_tod
+    parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 48
     parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
     parameters['TX_CPL_FIFO_DEPTH'] = 32
     parameters['TX_TAG_WIDTH'] = 16
diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile
index 3abd8cb78..661c6fb0a 100644
--- a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile
@@ -59,6 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
@@ -157,6 +158,8 @@ export PARAM_TDMA_INDEX_WIDTH := 6
 
 # Interface configuration
 export PARAM_PTP_TS_ENABLE := 1
+export PARAM_PTP_TS_FMT_TOD := 0
+export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),48,96)
 export PARAM_TX_CPL_ENABLE := $(PARAM_PTP_TS_ENABLE)
 export PARAM_TX_CPL_FIFO_DEPTH := 32
 export PARAM_TX_TAG_WIDTH := 16
diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py
index dae0619e2..f83406c57 100644
--- a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py
+++ b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py
@@ -286,14 +286,14 @@ def __init__(self, dut, msix_count=32):
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
                     tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
-                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
+                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_tx_ptp_ts_rel,
                     tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
                     tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
                     tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
                     rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
-                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
+                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_rx_ptp_ts_rel,
                     ifg=12, speed=eth_speed
                 )
 
@@ -743,18 +743,19 @@ async def run_test_nic(dut):
 
 
 @pytest.mark.parametrize(("if_count", "ports_per_if", "pcie_data_width",
-        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
-            (1, 1, 256, 64, 64, 1),
-            (1, 1, 256, 64, 64, 0),
-            (2, 1, 256, 64, 64, 1),
-            (1, 2, 256, 64, 64, 1),
-            (1, 1, 256, 64, 128, 1),
-            (1, 1, 512, 64, 64, 1),
-            (1, 1, 512, 64, 128, 1),
-            (1, 1, 512, 512, 512, 1),
+        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable", "ptp_ts_fmt_tod"), [
+            (1, 1, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 64, 1, 1),
+            (1, 1, 256, 64, 64, 0, 0),
+            (2, 1, 256, 64, 64, 1, 0),
+            (1, 2, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 128, 1, 0),
+            (1, 1, 512, 64, 64, 1, 0),
+            (1, 1, 512, 64, 128, 1, 0),
+            (1, 1, 512, 512, 512, 1, 0),
         ])
 def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
-        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
+        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable, ptp_ts_fmt_tod):
     dut = "mqnic_core_pcie_ptile"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -807,6 +808,7 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
         os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
@@ -906,6 +908,8 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
 
     # Interface configuration
     parameters['PTP_TS_ENABLE'] = ptp_ts_enable
+    parameters['PTP_TS_FMT_TOD'] = ptp_ts_fmt_tod
+    parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 48
     parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
     parameters['TX_CPL_FIFO_DEPTH'] = 32
     parameters['TX_TAG_WIDTH'] = 16
diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile
index b776daa53..1a4b3a3eb 100644
--- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile
@@ -59,6 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
@@ -156,6 +157,8 @@ export PARAM_TDMA_INDEX_WIDTH := 6
 
 # Interface configuration
 export PARAM_PTP_TS_ENABLE := 1
+export PARAM_PTP_TS_FMT_TOD := 0
+export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),48,96)
 export PARAM_TX_CPL_ENABLE := $(PARAM_PTP_TS_ENABLE)
 export PARAM_TX_CPL_FIFO_DEPTH := 32
 export PARAM_TX_TAG_WIDTH := 16
diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
index 93955ad8e..37bed6c45 100644
--- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
+++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
@@ -234,14 +234,14 @@ def __init__(self, dut, msix_count=32):
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
                     tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
-                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
+                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_tx_ptp_ts_rel,
                     tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
                     tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
                     tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
                     rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
-                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
+                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_rx_ptp_ts_rel,
                     ifg=12, speed=eth_speed
                 )
 
@@ -691,18 +691,19 @@ async def run_test_nic(dut):
 
 
 @pytest.mark.parametrize(("if_count", "ports_per_if", "pcie_data_width",
-        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
-            (1, 1, 256, 64, 64, 1),
-            (1, 1, 256, 64, 64, 0),
-            (2, 1, 256, 64, 64, 1),
-            (1, 2, 256, 64, 64, 1),
-            (1, 1, 256, 64, 128, 1),
-            (1, 1, 512, 64, 64, 1),
-            (1, 1, 512, 64, 128, 1),
-            (1, 1, 512, 512, 512, 1),
+        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable", "ptp_ts_fmt_tod"), [
+            (1, 1, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 64, 1, 1),
+            (1, 1, 256, 64, 64, 0, 0),
+            (2, 1, 256, 64, 64, 1, 0),
+            (1, 2, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 128, 1, 0),
+            (1, 1, 512, 64, 64, 1, 0),
+            (1, 1, 512, 64, 128, 1, 0),
+            (1, 1, 512, 512, 512, 1, 0),
         ])
 def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
-        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
+        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable, ptp_ts_fmt_tod):
     dut = "mqnic_core_pcie_s10"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -755,6 +756,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
         os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
@@ -853,6 +855,8 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
 
     # Interface configuration
     parameters['PTP_TS_ENABLE'] = ptp_ts_enable
+    parameters['PTP_TS_FMT_TOD'] = ptp_ts_fmt_tod
+    parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 48
     parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
     parameters['TX_CPL_FIFO_DEPTH'] = 32
     parameters['TX_TAG_WIDTH'] = 16
diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile
index bb983a520..2538a8acd 100644
--- a/fpga/common/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile
@@ -59,6 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
@@ -156,6 +157,8 @@ export PARAM_TDMA_INDEX_WIDTH := 6
 
 # Interface configuration
 export PARAM_PTP_TS_ENABLE := 1
+export PARAM_PTP_TS_FMT_TOD := 0
+export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),48,96)
 export PARAM_TX_CPL_ENABLE := $(PARAM_PTP_TS_ENABLE)
 export PARAM_TX_CPL_FIFO_DEPTH := 32
 export PARAM_TX_TAG_WIDTH := 16
diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 860688de4..8f09fc8e8 100644
--- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -308,14 +308,14 @@ def __init__(self, dut, msix_count=32):
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
                     tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
-                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
+                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_tx_ptp_ts_rel,
                     tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
                     tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
                     tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
                     rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
-                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
+                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_rx_ptp_ts_rel,
                     ifg=12, speed=eth_speed
                 )
 
@@ -765,18 +765,19 @@ async def run_test_nic(dut):
 
 
 @pytest.mark.parametrize(("if_count", "ports_per_if", "axis_pcie_data_width",
-        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
-            (1, 1, 256, 64, 64, 1),
-            (1, 1, 256, 64, 64, 0),
-            (2, 1, 256, 64, 64, 1),
-            (1, 2, 256, 64, 64, 1),
-            (1, 1, 256, 64, 128, 1),
-            (1, 1, 512, 64, 64, 1),
-            (1, 1, 512, 64, 128, 1),
-            (1, 1, 512, 512, 512, 1),
+        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable", "ptp_ts_fmt_tod"), [
+            (1, 1, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 64, 1, 1),
+            (1, 1, 256, 64, 64, 0, 0),
+            (2, 1, 256, 64, 64, 1, 0),
+            (1, 2, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 128, 1, 0),
+            (1, 1, 512, 64, 64, 1, 0),
+            (1, 1, 512, 64, 128, 1, 0),
+            (1, 1, 512, 512, 512, 1, 0),
         ])
 def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_width,
-        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
+        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable, ptp_ts_fmt_tod):
     dut = "mqnic_core_pcie_us"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -829,6 +830,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
@@ -927,6 +929,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
 
     # Interface configuration
     parameters['PTP_TS_ENABLE'] = ptp_ts_enable
+    parameters['PTP_TS_FMT_TOD'] = ptp_ts_fmt_tod
+    parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 48
     parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
     parameters['TX_CPL_FIFO_DEPTH'] = 32
     parameters['TX_TAG_WIDTH'] = 16
diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
index 8d707d5b9..9289395a7 100644
--- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
@@ -61,6 +61,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
@@ -158,6 +159,8 @@ export PARAM_TDMA_INDEX_WIDTH := 6
 
 # Interface configuration
 export PARAM_PTP_TS_ENABLE := 1
+export PARAM_PTP_TS_FMT_TOD := 0
+export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),48,96)
 export PARAM_TX_CPL_ENABLE := $(PARAM_PTP_TS_ENABLE)
 export PARAM_TX_CPL_FIFO_DEPTH := 32
 export PARAM_TX_TAG_WIDTH := 16
diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
index c79db0550..ba14940b1 100644
--- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
+++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
@@ -308,14 +308,14 @@ def __init__(self, dut, msix_count=32):
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
                     tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
-                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
+                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_tx_ptp_ts_rel,
                     tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
                     tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
                     tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
                     rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
-                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
+                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod if core_inst.PTP_TS_FMT_TOD.value else iface.port[k].port_rx_ptp_ts_rel,
                     ifg=12, speed=eth_speed
                 )
 
@@ -809,18 +809,19 @@ async def run_test_nic(dut):
 
 
 @pytest.mark.parametrize(("if_count", "ports_per_if", "axis_pcie_data_width",
-        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
-            (1, 1, 256, 64, 64, 1),
-            (1, 1, 256, 64, 64, 0),
-            (2, 1, 256, 64, 64, 1),
-            (1, 2, 256, 64, 64, 1),
-            (1, 1, 256, 64, 128, 1),
-            (1, 1, 512, 64, 64, 1),
-            (1, 1, 512, 64, 128, 1),
-            (1, 1, 512, 512, 512, 1),
+        "axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable", "ptp_ts_fmt_tod"), [
+            (1, 1, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 64, 1, 1),
+            (1, 1, 256, 64, 64, 0, 0),
+            (2, 1, 256, 64, 64, 1, 0),
+            (1, 2, 256, 64, 64, 1, 0),
+            (1, 1, 256, 64, 128, 1, 0),
+            (1, 1, 512, 64, 64, 1, 0),
+            (1, 1, 512, 64, 128, 1, 0),
+            (1, 1, 512, 512, 512, 1, 0),
         ])
 def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_width,
-        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
+        axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable, ptp_ts_fmt_tod):
     dut = "mqnic_core_pcie_us"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -875,6 +876,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
@@ -973,6 +975,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
 
     # Interface configuration
     parameters['PTP_TS_ENABLE'] = ptp_ts_enable
+    parameters['PTP_TS_FMT_TOD'] = ptp_ts_fmt_tod
+    parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 48
     parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
     parameters['TX_CPL_FIFO_DEPTH'] = 32
     parameters['TX_TAG_WIDTH'] = 16
diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile
index 412c5be99..80267c503 100644
--- a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile
@@ -59,6 +59,7 @@ SYN_FILES += rtl/common/cmac_pad.v
 SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -116,6 +117,7 @@ XDC_FILES += placement.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile
index 9236ce876..f6b5b3fd4 100644
--- a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile
@@ -62,6 +62,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@@ -126,6 +127,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/250_SoC/fpga_100g/ip/cmac_usplus.tcl b/fpga/mqnic/250_SoC/fpga_100g/ip/cmac_usplus.tcl
index af9cc8265..87c9bc38f 100644
--- a/fpga/mqnic/250_SoC/fpga_100g/ip/cmac_usplus.tcl
+++ b/fpga/mqnic/250_SoC/fpga_100g/ip/cmac_usplus.tcl
@@ -12,7 +12,8 @@ set_property -dict [list \
     CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \
     CONFIG.RX_CHECK_ACK {1} \
     CONFIG.INCLUDE_RS_FEC {1} \
-    CONFIG.ENABLE_TIME_STAMPING {1}
+    CONFIG.ENABLE_TIME_STAMPING {1} \
+    CONFIG.PTP_TRANSPCLK_MODE {1}
 ] [get_ips cmac_usplus]
 
 # disable LOC constraint
diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
index 0b6b0e7ac..ce43b0868 100644
--- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
@@ -220,9 +220,10 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 512;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1245,7 +1246,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1278,6 +1278,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v
index 97269cb08..7d8cb40ef 100644
--- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v
@@ -37,7 +37,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 512,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -70,6 +69,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -770,8 +771,8 @@ wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -797,8 +798,8 @@ wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -816,15 +817,10 @@ wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_en;
 wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_req;
 wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_ack;
 
-wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp0_rx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp1_rx_ptp_time_int;
-
-assign qsfp0_tx_ptp_time = qsfp0_tx_ptp_time_int >> 16;
-assign qsfp1_tx_ptp_time = qsfp1_tx_ptp_time_int >> 16;
-assign qsfp0_rx_ptp_time = qsfp0_rx_ptp_time_int >> 16;
-assign qsfp1_rx_ptp_time = qsfp1_rx_ptp_time_int >> 16;
+assign qsfp0_tx_ptp_time[79:48] = 0;
+assign qsfp1_tx_ptp_time[79:48] = 0;
+assign qsfp0_rx_ptp_time[79:48] = 0;
+assign qsfp1_rx_ptp_time[79:48] = 0;
 
 mqnic_port_map_mac_axis #(
     .MAC_COUNT(2),
@@ -850,7 +846,7 @@ mqnic_port_map_mac_axis_inst (
 
     .mac_tx_ptp_clk(2'b00),
     .mac_tx_ptp_rst(2'b00),
-    .mac_tx_ptp_ts_96({qsfp1_tx_ptp_time_int, qsfp0_tx_ptp_time_int}),
+    .mac_tx_ptp_ts_96({qsfp1_tx_ptp_time[47:0], qsfp0_tx_ptp_time[47:0]}),
     .mac_tx_ptp_ts_step(),
 
     .m_axis_mac_tx_tdata({qsfp1_tx_axis_tdata, qsfp0_tx_axis_tdata}),
@@ -860,7 +856,7 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_mac_tx_tlast({qsfp1_tx_axis_tlast, qsfp0_tx_axis_tlast}),
     .m_axis_mac_tx_tuser({qsfp1_tx_axis_tuser, qsfp0_tx_axis_tuser}),
 
-    .s_axis_mac_tx_ptp_ts({{qsfp1_tx_ptp_ts, 16'd0}, {qsfp0_tx_ptp_ts, 16'd0}}),
+    .s_axis_mac_tx_ptp_ts({qsfp1_tx_ptp_ts[47:0], qsfp0_tx_ptp_ts[47:0]}),
     .s_axis_mac_tx_ptp_ts_tag({qsfp1_tx_ptp_ts_tag, qsfp0_tx_ptp_ts_tag}),
     .s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
@@ -877,7 +873,7 @@ mqnic_port_map_mac_axis_inst (
 
     .mac_rx_ptp_clk(2'b00),
     .mac_rx_ptp_rst(2'b00),
-    .mac_rx_ptp_ts_96({qsfp1_rx_ptp_time_int, qsfp0_rx_ptp_time_int}),
+    .mac_rx_ptp_ts_96({qsfp1_rx_ptp_time[47:0], qsfp0_rx_ptp_time[47:0]}),
     .mac_rx_ptp_ts_step(),
 
     .s_axis_mac_rx_tdata({qsfp1_rx_axis_tdata, qsfp0_rx_axis_tdata}),
@@ -885,7 +881,7 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tvalid({qsfp1_rx_axis_tvalid, qsfp0_rx_axis_tvalid}),
     .s_axis_mac_rx_tready(),
     .s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
-    .s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
+    .s_axis_mac_rx_tuser({qsfp1_rx_axis_tuser[48:0], qsfp0_rx_axis_tuser[48:0]}),
 
     .mac_rx_enable({qsfp1_rx_enable, qsfp0_rx_enable}),
     .mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}),
@@ -902,8 +898,8 @@ mqnic_port_map_mac_axis_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_96(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts_96(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .s_axis_tx_tdata(axis_eth_tx_tdata),
     .s_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -929,8 +925,8 @@ mqnic_port_map_mac_axis_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_96(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts_96(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .m_axis_rx_tdata(axis_eth_rx_tdata),
     .m_axis_rx_tkeep(axis_eth_rx_tkeep),
@@ -974,7 +970,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1009,6 +1004,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1287,8 +1284,8 @@ core_inst (
 
     .eth_tx_ptp_clk(eth_tx_ptp_clk),
     .eth_tx_ptp_rst(eth_tx_ptp_rst),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1315,8 +1312,8 @@ core_inst (
 
     .eth_rx_ptp_clk(eth_rx_ptp_clk),
     .eth_rx_ptp_rst(eth_rx_ptp_rst),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile
index 22c8a021e..6b3c5e5ef 100644
--- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile
@@ -58,6 +58,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
 VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py
index a043aa7e8..a94611eac 100644
--- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -621,6 +621,7 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile
index a554ed95a..5527b91f9 100644
--- a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -135,6 +136,7 @@ XDC_FILES += placement.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile
index a554ed95a..5527b91f9 100644
--- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -135,6 +136,7 @@ XDC_FILES += placement.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
index fdcc78fd8..159205080 100644
--- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
@@ -227,11 +227,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 512;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1364,7 +1365,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1397,6 +1397,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v
index 37940cb3c..b7a64ed49 100644
--- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 512,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -75,6 +74,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -891,8 +892,8 @@ assign led[3] = ptp_pps_str;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -916,8 +917,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -1005,7 +1006,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -1051,8 +1052,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -1177,7 +1178,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1212,6 +1212,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1490,8 +1492,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1518,8 +1520,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile
index cb1c6d148..4a644e7d7 100644
--- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile
@@ -69,6 +69,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
index e9608bf26..f37d35859 100644
--- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -637,6 +637,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile b/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile
index 9f3d57b99..ef31c3b39 100644
--- a/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/520N_MX/fpga_25g/fpga/Makefile
@@ -76,6 +76,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile
index 7953d0bbe..f135f45a2 100644
--- a/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/520N_MX/fpga_25g/fpga_10g/Makefile
@@ -76,6 +76,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v
index e87a6f75e..16734c142 100644
--- a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v
@@ -191,11 +191,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // PCIe interface configuration
@@ -1281,7 +1282,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1316,6 +1316,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v
index b828ee6d5..ba49c409b 100644
--- a/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 32,
     parameter PTP_CLK_PERIOD_NS_DENOM = 5,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -75,6 +74,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -665,8 +666,8 @@ assign led_qsfp[3] = 1'b1;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -690,8 +691,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -779,7 +780,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -825,8 +826,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -951,7 +952,6 @@ mqnic_core_pcie_s10 #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -986,6 +986,8 @@ mqnic_core_pcie_s10 #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1189,8 +1191,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1217,8 +1219,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile
index 84aaf6a89..df6bc383e 100644
--- a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile
@@ -67,6 +67,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py
index b657b1f9a..8a2638cb4 100644
--- a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -545,6 +545,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
index cdd5edff6..340427958 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += rtl/common/i2c_single_reg.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -119,6 +120,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile
index 680e8ccb6..4cfb0ec90 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile
@@ -64,6 +64,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@@ -129,6 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
index 36af63381..7300d3c4e 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += rtl/common/i2c_single_reg.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -121,6 +122,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/cmac_usplus.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/cmac_usplus.tcl
index af9cc8265..87c9bc38f 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/cmac_usplus.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/cmac_usplus.tcl
@@ -12,7 +12,8 @@ set_property -dict [list \
     CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \
     CONFIG.RX_CHECK_ACK {1} \
     CONFIG.INCLUDE_RS_FEC {1} \
-    CONFIG.ENABLE_TIME_STAMPING {1}
+    CONFIG.ENABLE_TIME_STAMPING {1} \
+    CONFIG.PTP_TRANSPCLK_MODE {1}
 ] [get_ips cmac_usplus]
 
 # disable LOC constraint
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
index f4f6e6eba..5972e36b6 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
@@ -247,9 +247,10 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1605,7 +1606,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1638,6 +1638,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
index 28866d600..2e2eb7ef0 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
@@ -37,7 +37,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 1024,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -70,6 +69,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -860,8 +861,8 @@ wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -887,8 +888,8 @@ wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -906,15 +907,10 @@ wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_en;
 wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_req;
 wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_ack;
 
-wire [PTP_TS_WIDTH-1:0] qsfp_0_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_1_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_0_rx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_1_rx_ptp_time_int;
-
-assign qsfp_0_tx_ptp_time = qsfp_0_tx_ptp_time_int >> 16;
-assign qsfp_1_tx_ptp_time = qsfp_1_tx_ptp_time_int >> 16;
-assign qsfp_0_rx_ptp_time = qsfp_0_rx_ptp_time_int >> 16;
-assign qsfp_1_rx_ptp_time = qsfp_1_rx_ptp_time_int >> 16;
+assign qsfp_0_tx_ptp_time[79:48] = 0;
+assign qsfp_1_tx_ptp_time[79:48] = 0;
+assign qsfp_0_rx_ptp_time[79:48] = 0;
+assign qsfp_1_rx_ptp_time[79:48] = 0;
 
 mqnic_port_map_mac_axis #(
     .MAC_COUNT(2),
@@ -940,7 +936,7 @@ mqnic_port_map_mac_axis_inst (
 
     .mac_tx_ptp_clk(2'b00),
     .mac_tx_ptp_rst(2'b00),
-    .mac_tx_ptp_ts_96({qsfp_1_tx_ptp_time_int, qsfp_0_tx_ptp_time_int}),
+    .mac_tx_ptp_ts_96({qsfp_1_tx_ptp_time[47:0], qsfp_0_tx_ptp_time[47:0]}),
     .mac_tx_ptp_ts_step(),
 
     .m_axis_mac_tx_tdata({qsfp_1_tx_axis_tdata, qsfp_0_tx_axis_tdata}),
@@ -950,7 +946,7 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_mac_tx_tlast({qsfp_1_tx_axis_tlast, qsfp_0_tx_axis_tlast}),
     .m_axis_mac_tx_tuser({qsfp_1_tx_axis_tuser, qsfp_0_tx_axis_tuser}),
 
-    .s_axis_mac_tx_ptp_ts({{qsfp_1_tx_ptp_ts, 16'd0}, {qsfp_0_tx_ptp_ts, 16'd0}}),
+    .s_axis_mac_tx_ptp_ts({qsfp_1_tx_ptp_ts[47:0], qsfp_0_tx_ptp_ts[47:0]}),
     .s_axis_mac_tx_ptp_ts_tag({qsfp_1_tx_ptp_ts_tag, qsfp_0_tx_ptp_ts_tag}),
     .s_axis_mac_tx_ptp_ts_valid({qsfp_1_tx_ptp_ts_valid, qsfp_0_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
@@ -967,7 +963,7 @@ mqnic_port_map_mac_axis_inst (
 
     .mac_rx_ptp_clk(2'b00),
     .mac_rx_ptp_rst(2'b00),
-    .mac_rx_ptp_ts_96({qsfp_1_rx_ptp_time_int, qsfp_0_rx_ptp_time_int}),
+    .mac_rx_ptp_ts_96({qsfp_1_rx_ptp_time[47:0], qsfp_0_rx_ptp_time[47:0]}),
     .mac_rx_ptp_ts_step(),
 
     .s_axis_mac_rx_tdata({qsfp_1_rx_axis_tdata, qsfp_0_rx_axis_tdata}),
@@ -975,7 +971,7 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tvalid({qsfp_1_rx_axis_tvalid, qsfp_0_rx_axis_tvalid}),
     .s_axis_mac_rx_tready(),
     .s_axis_mac_rx_tlast({qsfp_1_rx_axis_tlast, qsfp_0_rx_axis_tlast}),
-    .s_axis_mac_rx_tuser({{qsfp_1_rx_axis_tuser[80:1], 16'd0, qsfp_1_rx_axis_tuser[0]}, {qsfp_0_rx_axis_tuser[80:1], 16'd0, qsfp_0_rx_axis_tuser[0]}}),
+    .s_axis_mac_rx_tuser({qsfp_1_rx_axis_tuser[48:0], qsfp_0_rx_axis_tuser[48:0]}),
 
     .mac_rx_enable({qsfp_1_rx_enable, qsfp_0_rx_enable}),
     .mac_rx_status({qsfp_1_rx_status, qsfp_0_rx_status}),
@@ -992,8 +988,8 @@ mqnic_port_map_mac_axis_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_96(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts_96(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .s_axis_tx_tdata(axis_eth_tx_tdata),
     .s_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -1019,8 +1015,8 @@ mqnic_port_map_mac_axis_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_96(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts_96(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .m_axis_rx_tdata(axis_eth_rx_tdata),
     .m_axis_rx_tkeep(axis_eth_rx_tkeep),
@@ -1064,7 +1060,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1099,6 +1094,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1377,8 +1374,8 @@ core_inst (
 
     .eth_tx_ptp_clk(eth_tx_ptp_clk),
     .eth_tx_ptp_rst(eth_tx_ptp_rst),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1405,8 +1402,8 @@ core_inst (
 
     .eth_rx_ptp_clk(eth_rx_ptp_clk),
     .eth_rx_ptp_rst(eth_rx_ptp_rst),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
index 60b02e6f9..0afd0d595 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
@@ -59,6 +59,7 @@ VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
 VERILOG_SOURCES += ../../rtl/common/i2c_single_reg.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
index 4922f0ca5..e844f145f 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -624,6 +624,7 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "i2c_single_reg.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
index c5329a135..8df788999 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -137,6 +138,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
index c5329a135..8df788999 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -137,6 +138,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
index 7bb49aab8..3fcd4f8d9 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
@@ -80,6 +80,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -138,6 +139,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
index 98e705616..f366018b4 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
@@ -254,11 +254,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h2;
 parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1728,7 +1729,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1761,6 +1761,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
index da5054d08..61a98a27b 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 1024,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -75,6 +74,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -980,8 +981,8 @@ assign front_led[1] = 1'b0;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -1005,8 +1006,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -1094,7 +1095,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -1140,8 +1141,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -1266,7 +1267,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1301,6 +1301,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1579,8 +1581,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1607,8 +1609,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
index afd5780c7..d19191656 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
@@ -70,6 +70,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
index 49b2987c3..1623e8944 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -640,6 +640,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU200/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200/Makefile
index 7cd0e5779..5a853c970 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU200/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/cmac_pad.v
 SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -123,6 +124,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/Makefile
index 8b1201b45..6be359134 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@@ -133,6 +134,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU250/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250/Makefile
index d1d91143e..a56e8bd00 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU250/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/cmac_pad.v
 SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -123,6 +124,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/Makefile
index 02329da53..a3fe9c3f6 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@@ -133,6 +134,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU280/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU280/Makefile
index acc4e4b32..649878496 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU280/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU280/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/cmac_pad.v
 SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -122,6 +123,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU280_app_dma_bench/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU280_app_dma_bench/Makefile
index 3f2581100..9877ed352 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU280_app_dma_bench/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU280_app_dma_bench/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@@ -132,6 +133,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU50/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50/Makefile
index b3d65a1bc..55363932b 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU50/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/cmac_pad.v
 SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -122,6 +123,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/Makefile
index 2fa42a90f..dcc166d47 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@@ -132,6 +133,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N/Makefile
index 55cb2d6fd..21ea5cacc 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/cmac_pad.v
 SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -122,6 +123,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N_app_dma_bench/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N_app_dma_bench/Makefile
index abfba1bfb..7b5a64a3a 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N_app_dma_bench/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU55N_app_dma_bench/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@@ -132,6 +133,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/Makefile
index 07a2fa1da..3f8fe6973 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/cmac_pad.v
 SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -119,6 +120,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile
index 9eab57e34..2f9c2f879 100644
--- a/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@@ -129,6 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_100g/ip/cmac_usplus.tcl b/fpga/mqnic/Alveo/fpga_100g/ip/cmac_usplus.tcl
index af9cc8265..87c9bc38f 100644
--- a/fpga/mqnic/Alveo/fpga_100g/ip/cmac_usplus.tcl
+++ b/fpga/mqnic/Alveo/fpga_100g/ip/cmac_usplus.tcl
@@ -12,7 +12,8 @@ set_property -dict [list \
     CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \
     CONFIG.RX_CHECK_ACK {1} \
     CONFIG.INCLUDE_RS_FEC {1} \
-    CONFIG.ENABLE_TIME_STAMPING {1}
+    CONFIG.ENABLE_TIME_STAMPING {1} \
+    CONFIG.PTP_TRANSPCLK_MODE {1}
 ] [get_ips cmac_usplus]
 
 # disable LOC constraint
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
index bd04118ab..bdfc22d4c 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
@@ -281,9 +281,10 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -2077,7 +2078,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -2110,6 +2110,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v
index 1987b2fd4..36787864a 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v
@@ -237,9 +237,10 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1811,7 +1812,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1844,6 +1844,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v
index ccda81510..d0fe5af24 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v
@@ -185,9 +185,10 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1303,7 +1304,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1336,6 +1336,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v
index 5fe4954af..a0fda0687 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v
@@ -190,9 +190,10 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1430,7 +1431,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1463,6 +1463,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v
index 48da7e07a..dfaab59f2 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v
@@ -46,7 +46,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 1024,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -79,6 +78,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -833,8 +834,8 @@ wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -860,8 +861,8 @@ wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -890,11 +891,11 @@ generate
 
 for (n = 0; n < QSFP_CNT; n = n + 1) begin
     assign qsfp_tx_axis_tuser_int[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH] = qsfp_tx_axis_tuser[n*(16+1) +: 16+1];
-    assign qsfp_tx_ptp_time[n*80 +: 80] = qsfp_tx_ptp_time_int[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] >> 16;
-    assign qsfp_tx_ptp_ts_int[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = {qsfp_tx_ptp_ts[n*80 +: 80], 16'd0};
+    assign qsfp_tx_ptp_time[n*80 +: 80] = qsfp_tx_ptp_time_int[n*PTP_TS_WIDTH +: PTP_TS_WIDTH];
+    assign qsfp_tx_ptp_ts_int[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = qsfp_tx_ptp_ts[n*80 +: PTP_TS_WIDTH];
 
-    assign qsfp_rx_axis_tuser_int[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH] = {qsfp_rx_axis_tuser[n*81+1 +: 80], 16'd0, qsfp_rx_axis_tuser[n*81+0 +: 1]};
-    assign qsfp_rx_ptp_time[n*80 +: 80] = qsfp_rx_ptp_time_int[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] >> 16;
+    assign qsfp_rx_axis_tuser_int[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH] = qsfp_rx_axis_tuser[n*81 +: AXIS_ETH_RX_USER_WIDTH];
+    assign qsfp_rx_ptp_time[n*80 +: 80] = qsfp_rx_ptp_time_int[n*PTP_TS_WIDTH +: PTP_TS_WIDTH];
 end
 
 endgenerate
@@ -975,8 +976,8 @@ mqnic_port_map_mac_axis_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_96(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts_96(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .s_axis_tx_tdata(axis_eth_tx_tdata),
     .s_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -1002,8 +1003,8 @@ mqnic_port_map_mac_axis_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_96(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts_96(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .m_axis_rx_tdata(axis_eth_rx_tdata),
     .m_axis_rx_tkeep(axis_eth_rx_tkeep),
@@ -1047,7 +1048,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1082,6 +1082,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1375,8 +1377,8 @@ core_inst (
 
     .eth_tx_ptp_clk(eth_tx_ptp_clk),
     .eth_tx_ptp_rst(eth_tx_ptp_rst),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1403,8 +1405,8 @@ core_inst (
 
     .eth_rx_ptp_clk(eth_rx_ptp_clk),
     .eth_rx_ptp_rst(eth_rx_ptp_rst),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/Makefile
index 748f3fd78..7b5ce4b63 100644
--- a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/Makefile
@@ -59,6 +59,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
 VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.py
index 3ee7864d2..c087d6c52 100644
--- a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -622,6 +622,7 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v
index 56ecf45ff..c68a307c9 100644
--- a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v
+++ b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v
@@ -65,7 +65,6 @@ module test_fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 1024,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -98,6 +97,8 @@ module test_fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -657,7 +658,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -690,6 +690,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU200/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200/Makefile
index 4c102934f..71152e045 100644
--- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU200/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -142,6 +143,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/Makefile
index 4c102934f..71152e045 100644
--- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -142,6 +143,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU250/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250/Makefile
index 09da593c4..38c771dc0 100644
--- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU250/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -142,6 +143,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/Makefile
index 09da593c4..38c771dc0 100644
--- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -142,6 +143,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU280/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU280/Makefile
index 1fd1b8469..64348b6b2 100644
--- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU280/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU280/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -141,6 +142,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU280_10g/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU280_10g/Makefile
index 1fd1b8469..64348b6b2 100644
--- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU280_10g/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU280_10g/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -141,6 +142,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU50/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50/Makefile
index 57c800d0a..f71c352ec 100644
--- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU50/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -141,6 +142,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/Makefile
index 57c800d0a..f71c352ec 100644
--- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU50_10g/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -141,6 +142,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N/Makefile
index b0e313ce0..dc853e07c 100644
--- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -141,6 +142,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N_10g/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N_10g/Makefile
index b0e313ce0..dc853e07c 100644
--- a/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N_10g/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU55N_10g/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_cdc.v
 SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
@@ -141,6 +142,7 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/Makefile
index 570e09770..55c62528f 100644
--- a/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -138,6 +139,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile
index 570e09770..55c62528f 100644
--- a/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -138,6 +139,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v
index 7a6679cb1..035ae3023 100644
--- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v
+++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v
@@ -286,11 +286,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -2138,7 +2139,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -2171,6 +2171,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v
index 20eef659e..cb1fde5d0 100644
--- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v
+++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v
@@ -242,11 +242,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1874,7 +1875,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1909,6 +1909,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v
index b23489551..fc6eafc9b 100644
--- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v
+++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v
@@ -190,11 +190,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1324,7 +1325,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1357,6 +1357,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v
index a0772c7ef..59c2688d9 100644
--- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v
+++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v
@@ -195,11 +195,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1494,7 +1495,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1527,6 +1527,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v
index fb8efa571..a7fbd2511 100644
--- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v
@@ -47,7 +47,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 1024,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -82,6 +81,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -890,8 +891,8 @@ assign qsfp_led_stat_y = 0;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -915,8 +916,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -1003,7 +1004,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -1049,8 +1050,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -1175,7 +1176,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1210,6 +1210,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1488,8 +1490,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1516,8 +1518,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/Makefile
index 2e051b0ad..a6c01f7c9 100644
--- a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/Makefile
@@ -70,6 +70,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py
index fc6b0897e..949fac7b9 100644
--- a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -629,6 +629,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v
index 5c3887e29..dada05419 100644
--- a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v
+++ b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v
@@ -66,7 +66,6 @@ module test_fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 1024,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -101,6 +100,8 @@ module test_fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -554,7 +555,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -589,6 +589,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/Makefile
index 792103d92..d5e7803cc 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/Makefile
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/Makefile
index 5c28d542a..6a3f75857 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/Makefile
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/Makefile
index 0e08bd1d0..de9e78a03 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/Makefile
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile
index 3aeb1cda1..4f6b1e8c6 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/Makefile
index 8aa6739d3..f94ee500a 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/Makefile
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/Makefile
index a8a69d712..6003ccf54 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/Makefile
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/Makefile
index e16daa5fe..068c970f2 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/Makefile
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/Makefile
index 5ac6486a7..1a7662a37 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/Makefile
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v
index 3429793f1..3c17f4cae 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v
@@ -195,10 +195,11 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 2048;
 parameter PTP_CLK_PERIOD_NS_DENOM = 825;
-parameter PTP_TS_WIDTH = 96;
 parameter PTP_TAG_WIDTH = 8;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 1;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = PTP_TAG_WIDTH;
 
 // PCIe interface configuration
@@ -788,7 +789,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(MAC_100G ? 0 : 1),
@@ -823,6 +823,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v
index 9294a6d5b..46b8c7145 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v
@@ -42,7 +42,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 2048,
     parameter PTP_CLK_PERIOD_NS_DENOM = 825,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -77,6 +76,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 8,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -518,8 +519,8 @@ wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -540,8 +541,8 @@ wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -628,8 +629,8 @@ mqnic_port_map_mac_axis_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_96(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts_96(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .s_axis_tx_tdata(axis_eth_tx_tdata),
     .s_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -650,8 +651,8 @@ mqnic_port_map_mac_axis_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_96(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts_96(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .m_axis_rx_tdata(axis_eth_rx_tdata),
     .m_axis_rx_tkeep(axis_eth_rx_tkeep),
@@ -688,7 +689,6 @@ mqnic_core_pcie_ptile #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -723,6 +723,8 @@ mqnic_core_pcie_ptile #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -929,8 +931,8 @@ core_inst (
 
     .eth_tx_ptp_clk(eth_tx_ptp_clk),
     .eth_tx_ptp_rst(eth_tx_ptp_rst),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -951,8 +953,8 @@ core_inst (
 
     .eth_rx_ptp_clk(eth_rx_ptp_clk),
     .eth_rx_ptp_rst(eth_rx_ptp_rst),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile
index 6b83ebd11..5f18c5bb4 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile
@@ -14,6 +14,7 @@ TOPLEVEL = test_$(DUT)
 MODULE   = test_$(DUT)
 VERILOG_SOURCES += $(TOPLEVEL).v
 VERILOG_SOURCES += ../../rtl/$(DUT).v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_ptile.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
 VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py
index e93d3ce42..dd5279e92 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -603,6 +603,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.v
index 00bbeed07..aec0ed9b1 100644
--- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.v
+++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.v
@@ -61,7 +61,6 @@ module test_fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 2048,
     parameter PTP_CLK_PERIOD_NS_DENOM = 825,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -96,6 +95,8 @@ module test_fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 8,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -451,7 +452,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -486,6 +486,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g/Makefile
index dd09941a7..4254b126b 100644
--- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g/Makefile
+++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g_app_dma_bench/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g_app_dma_bench/Makefile
index 9668268d7..4e1b54346 100644
--- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g_app_dma_bench/Makefile
+++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g_app_dma_bench/Makefile
@@ -62,6 +62,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_10g/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_10g/Makefile
index 86ff4198d..25e79ee48 100644
--- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_10g/Makefile
+++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_10g/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_25g/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_25g/Makefile
index 10b29fa05..85c000d3f 100644
--- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_25g/Makefile
+++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_25g/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v
index 44ec0cf3f..18e839e64 100644
--- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v
@@ -188,10 +188,11 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 4096;
 parameter PTP_CLK_PERIOD_NS_DENOM = 825;
-parameter PTP_TS_WIDTH = 96;
 parameter PTP_TAG_WIDTH = 8;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 1;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = PTP_TAG_WIDTH;
 
 // PCIe interface configuration
@@ -757,7 +758,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(MAC_100G ? 0 : 1),
@@ -792,6 +792,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v
index 67d24c59c..503402504 100644
--- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v
@@ -42,7 +42,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 4096,
     parameter PTP_CLK_PERIOD_NS_DENOM = 825,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -77,6 +76,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 8,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -409,8 +410,8 @@ wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -436,8 +437,8 @@ wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -531,8 +532,8 @@ mqnic_port_map_mac_axis_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_96(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts_96(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .s_axis_tx_tdata(axis_eth_tx_tdata),
     .s_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -558,8 +559,8 @@ mqnic_port_map_mac_axis_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_96(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts_96(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .m_axis_rx_tdata(axis_eth_rx_tdata),
     .m_axis_rx_tkeep(axis_eth_rx_tkeep),
@@ -603,7 +604,6 @@ mqnic_core_pcie_ptile #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -638,6 +638,8 @@ mqnic_core_pcie_ptile #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -838,8 +840,8 @@ core_inst (
 
     .eth_tx_ptp_clk(eth_tx_ptp_clk),
     .eth_tx_ptp_rst(eth_tx_ptp_rst),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -866,8 +868,8 @@ core_inst (
 
     .eth_rx_ptp_clk(eth_rx_ptp_clk),
     .eth_rx_ptp_rst(eth_rx_ptp_rst),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile
index 5bbc17fda..7e90c0167 100644
--- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile
@@ -61,6 +61,7 @@ VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py
index 10a1f4045..1eaf309f2 100644
--- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -590,6 +590,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.v
index 9937a4270..f7578e312 100644
--- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.v
+++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.v
@@ -61,7 +61,6 @@ module test_fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 4096,
     parameter PTP_CLK_PERIOD_NS_DENOM = 825,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -96,6 +95,8 @@ module test_fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 8,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -436,7 +437,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -471,6 +471,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile
index 09be81c3d..7ea6cc5a4 100644
--- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile
+++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21b/Makefile
@@ -77,6 +77,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile
index 7b67aef7e..f4f6a1f04 100644
--- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile
+++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_10g_1sm21c/Makefile
@@ -77,6 +77,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile
index decffc1cb..7107f65ec 100644
--- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile
+++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/Makefile
@@ -77,6 +77,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile
index c2b81a7e5..c36be1de2 100644
--- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile
+++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/Makefile
@@ -77,6 +77,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v
index 0a240c502..f8175c6bc 100644
--- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v
@@ -188,11 +188,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // PCIe interface configuration
@@ -978,7 +979,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1013,6 +1013,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v
index 63aa47f41..b8a2f73cc 100644
--- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 32,
     parameter PTP_CLK_PERIOD_NS_DENOM = 5,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -75,6 +74,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -631,8 +632,8 @@ assign user_led[3] = ptp_pps_str;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -656,8 +657,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -745,7 +746,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -791,8 +792,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -917,7 +918,6 @@ mqnic_core_pcie_s10 #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -952,6 +952,8 @@ mqnic_core_pcie_s10 #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1155,8 +1157,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1183,8 +1185,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile
index a05e1928a..f527ac2f3 100644
--- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile
@@ -68,6 +68,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py
index c0b6a96f6..64b4db207 100644
--- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -548,6 +548,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g/Makefile
index 54324b6c6..ee77b93e2 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/i2c_single_reg.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_24AR0/Makefile
index 592f6a130..f72c4b198 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_24AR0/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_24AR0/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/i2c_single_reg.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench/Makefile
index b61a113ae..d4cc0ec3b 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile
index 3557a60b2..aa640236b 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g/Makefile
index 85f017b92..73328d1e9 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/i2c_single_reg.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g_24AR0/Makefile
index 1d2972807..9701929f5 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g_24AR0/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g_24AR0/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/i2c_single_reg.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/Makefile
index 6d27231b9..16ac7b174 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/i2c_single_reg.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/Makefile
index e29413cf6..9b18ecff2 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/i2c_single_reg.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v
index bbe8b071d..c74bc19e3 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v
@@ -202,10 +202,11 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 2048;
 parameter PTP_CLK_PERIOD_NS_DENOM = 825;
-parameter PTP_TS_WIDTH = 96;
 parameter PTP_TAG_WIDTH = 8;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 1;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = PTP_TAG_WIDTH;
 
 // PCIe interface configuration
@@ -785,7 +786,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(MAC_100G ? 0 : 1),
@@ -820,6 +820,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v
index 4870c206c..f44b766c8 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v
@@ -42,7 +42,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 2048,
     parameter PTP_CLK_PERIOD_NS_DENOM = 825,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -77,6 +76,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 8,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -549,8 +550,8 @@ wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -576,8 +577,8 @@ wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -671,8 +672,8 @@ mqnic_port_map_mac_axis_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_96(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts_96(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .s_axis_tx_tdata(axis_eth_tx_tdata),
     .s_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -698,8 +699,8 @@ mqnic_port_map_mac_axis_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_96(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts_96(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .m_axis_rx_tdata(axis_eth_rx_tdata),
     .m_axis_rx_tkeep(axis_eth_rx_tkeep),
@@ -743,7 +744,6 @@ mqnic_core_pcie_ptile #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -778,6 +778,8 @@ mqnic_core_pcie_ptile #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -984,8 +986,8 @@ core_inst (
 
     .eth_tx_ptp_clk(eth_tx_ptp_clk),
     .eth_tx_ptp_rst(eth_tx_ptp_rst),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1012,8 +1014,8 @@ core_inst (
 
     .eth_rx_ptp_clk(eth_rx_ptp_clk),
     .eth_rx_ptp_rst(eth_rx_ptp_rst),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile
index aa89d5370..f2c760db6 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile
@@ -65,6 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py
index 56ee875e5..ce1f54d71 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -601,6 +601,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.v
index cce71d238..90a4dfdd3 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.v
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.v
@@ -61,7 +61,6 @@ module test_fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 2048,
     parameter PTP_CLK_PERIOD_NS_DENOM = 825,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -96,6 +95,8 @@ module test_fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 8,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -457,7 +458,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -492,6 +492,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile
index 9582eaa28..a1dd0c11d 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile
@@ -81,6 +81,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
@@ -144,6 +145,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile
index 2b6034609..c17f12cb7 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile
@@ -81,6 +81,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
@@ -144,6 +145,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
index abc85c845..adeb6c2ea 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -135,6 +136,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
index dda35c0a6..b24c064d1 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -135,6 +136,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
index 606e942e6..fa41a0250 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
@@ -245,11 +245,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 32;
 parameter PTP_CLK_PERIOD_NS_DENOM = 5;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1572,7 +1573,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1605,6 +1605,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
index 138d4e9f1..1eec0c1d5 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 32,
     parameter PTP_CLK_PERIOD_NS_DENOM = 5,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -75,6 +74,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -987,8 +988,8 @@ assign qsfp1_leg_red = 1'b0;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -1012,8 +1013,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -1101,7 +1102,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -1147,8 +1148,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -1273,7 +1274,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1308,6 +1308,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1586,8 +1588,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1614,8 +1616,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
index 94c19b6c1..e458b275f 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
@@ -69,6 +69,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
index aecf8bc5c..50672b581 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
@@ -597,6 +597,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/IA_420F/fpga_100g/fpga_100g/Makefile b/fpga/mqnic/IA_420F/fpga_100g/fpga_100g/Makefile
index f37eb261a..9135291cf 100644
--- a/fpga/mqnic/IA_420F/fpga_100g/fpga_100g/Makefile
+++ b/fpga/mqnic/IA_420F/fpga_100g/fpga_100g/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/IA_420F/fpga_100g/fpga_100g_app_dma_bench/Makefile b/fpga/mqnic/IA_420F/fpga_100g/fpga_100g_app_dma_bench/Makefile
index f9cba4e77..2af1953a6 100644
--- a/fpga/mqnic/IA_420F/fpga_100g/fpga_100g_app_dma_bench/Makefile
+++ b/fpga/mqnic/IA_420F/fpga_100g/fpga_100g_app_dma_bench/Makefile
@@ -62,6 +62,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/IA_420F/fpga_100g/fpga_10g/Makefile b/fpga/mqnic/IA_420F/fpga_100g/fpga_10g/Makefile
index 8610cfb50..ecba26c46 100644
--- a/fpga/mqnic/IA_420F/fpga_100g/fpga_10g/Makefile
+++ b/fpga/mqnic/IA_420F/fpga_100g/fpga_10g/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/IA_420F/fpga_100g/fpga_25g/Makefile b/fpga/mqnic/IA_420F/fpga_100g/fpga_25g/Makefile
index 82f6c154a..56de8684a 100644
--- a/fpga/mqnic/IA_420F/fpga_100g/fpga_25g/Makefile
+++ b/fpga/mqnic/IA_420F/fpga_100g/fpga_25g/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/IA_420F/fpga_100g/rtl/fpga.v b/fpga/mqnic/IA_420F/fpga_100g/rtl/fpga.v
index acd014931..1a9f86566 100644
--- a/fpga/mqnic/IA_420F/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/IA_420F/fpga_100g/rtl/fpga.v
@@ -179,10 +179,11 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 2048;
 parameter PTP_CLK_PERIOD_NS_DENOM = 825;
-parameter PTP_TS_WIDTH = 96;
 parameter PTP_TAG_WIDTH = 8;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 1;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = PTP_TAG_WIDTH;
 
 // PCIe interface configuration
@@ -622,7 +623,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(MAC_100G ? 0 : 1),
@@ -657,6 +657,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/IA_420F/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/IA_420F/fpga_100g/rtl/fpga_core.v
index 409a61f2b..8c2f83a31 100644
--- a/fpga/mqnic/IA_420F/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/IA_420F/fpga_100g/rtl/fpga_core.v
@@ -42,7 +42,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 2048,
     parameter PTP_CLK_PERIOD_NS_DENOM = 825,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -77,6 +76,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 8,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -408,8 +409,8 @@ wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -435,8 +436,8 @@ wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -530,8 +531,8 @@ mqnic_port_map_mac_axis_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_96(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts_96(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .s_axis_tx_tdata(axis_eth_tx_tdata),
     .s_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -557,8 +558,8 @@ mqnic_port_map_mac_axis_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_96(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts_96(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .m_axis_rx_tdata(axis_eth_rx_tdata),
     .m_axis_rx_tkeep(axis_eth_rx_tkeep),
@@ -602,7 +603,6 @@ mqnic_core_pcie_ptile #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -637,6 +637,8 @@ mqnic_core_pcie_ptile #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -843,8 +845,8 @@ core_inst (
 
     .eth_tx_ptp_clk(eth_tx_ptp_clk),
     .eth_tx_ptp_rst(eth_tx_ptp_rst),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -871,8 +873,8 @@ core_inst (
 
     .eth_rx_ptp_clk(eth_rx_ptp_clk),
     .eth_rx_ptp_rst(eth_rx_ptp_rst),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/Makefile
index aa89d5370..f2c760db6 100644
--- a/fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/Makefile
@@ -65,6 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/test_fpga_core.py
index e09ab5f7d..68c3d4119 100644
--- a/fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -593,6 +593,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/test_fpga_core.v
index 201ad3af4..bd5009ea8 100644
--- a/fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/test_fpga_core.v
+++ b/fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/test_fpga_core.v
@@ -61,7 +61,6 @@ module test_fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 2048,
     parameter PTP_CLK_PERIOD_NS_DENOM = 825,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_SEPARATE_TX_CLOCK = 0,
@@ -96,6 +95,8 @@ module test_fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 1,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 8,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -437,7 +438,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
@@ -472,6 +472,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/KR260/fpga/fpga/Makefile b/fpga/mqnic/KR260/fpga/fpga/Makefile
index 46557cca4..6cb8e41b3 100644
--- a/fpga/mqnic/KR260/fpga/fpga/Makefile
+++ b/fpga/mqnic/KR260/fpga/fpga/Makefile
@@ -75,6 +75,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -117,6 +118,7 @@ XDC_FILES = fpga.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/Makefile b/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/Makefile
index 664d1bcca..79ba7d678 100644
--- a/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/KR260/fpga/fpga_app_dma_bench/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
@@ -126,6 +127,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/KR260/fpga/rtl/fpga.v b/fpga/mqnic/KR260/fpga/rtl/fpga.v
index 097ae1040..96a1c1a35 100644
--- a/fpga/mqnic/KR260/fpga/rtl/fpga.v
+++ b/fpga/mqnic/KR260/fpga/rtl/fpga.v
@@ -173,11 +173,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 32;
 parameter PTP_CLK_PERIOD_NS_DENOM = 5;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // Ethernet interface configuration
@@ -671,7 +672,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -704,6 +704,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/KR260/fpga/rtl/fpga_core.v b/fpga/mqnic/KR260/fpga/rtl/fpga_core.v
index 8a1bc301a..d67a601c0 100644
--- a/fpga/mqnic/KR260/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/KR260/fpga/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 32,
     parameter PTP_CLK_PERIOD_NS_DENOM = 5,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -75,6 +74,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -576,8 +577,8 @@ assign sfp_led = 0;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -601,8 +602,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -690,7 +691,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -736,8 +737,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -862,7 +863,6 @@ mqnic_core_axi #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -897,6 +897,8 @@ mqnic_core_axi #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1140,8 +1142,8 @@ core_inst (
 
     .tx_ptp_clk(0),
     .tx_ptp_rst(0),
-    .tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_tx_tdata(axis_eth_tx_tdata),
     .m_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -1168,8 +1170,8 @@ core_inst (
 
     .rx_ptp_clk(0),
     .rx_ptp_rst(0),
-    .rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_rx_tdata(axis_eth_rx_tdata),
     .s_axis_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile b/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile
index c084dc402..97db8d9af 100644
--- a/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile
@@ -66,6 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py
index 78bf0da1f..cae9fc5cf 100644
--- a/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py
@@ -378,6 +378,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
index b47310da0..3863da163 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
@@ -76,6 +76,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -133,6 +134,7 @@ XDC_FILES += pcie.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/Makefile
index 6bb79c060..217e30c35 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -135,6 +136,7 @@ XDC_FILES += pcie.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
index 7c52124b6..d7e3a1e8e 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
@@ -214,11 +214,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 32;
 parameter PTP_CLK_PERIOD_NS_DENOM = 5;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // PCIe interface configuration
@@ -1294,7 +1295,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1327,6 +1327,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
index cc976a559..13dceacb3 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
@@ -37,7 +37,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 32,
     parameter PTP_CLK_PERIOD_NS_DENOM = 5,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -72,6 +71,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -533,8 +534,8 @@ assign led[1] = 1'b0;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -558,8 +559,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -647,7 +648,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -693,8 +694,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -819,7 +820,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -854,6 +854,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1117,8 +1119,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1145,8 +1147,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
index a9034a783..19c4a371a 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
@@ -67,6 +67,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
index 7dd1aac51..00a6930ff 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
@@ -587,6 +587,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile
index 4c2d8f39b..eb507766d 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -135,6 +136,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile
index 4c2d8f39b..eb507766d 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -135,6 +136,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile
index 446dc2c3b..915263748 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile
@@ -81,6 +81,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
@@ -144,6 +145,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v
index ad80c27bb..68e327833 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v
@@ -239,11 +239,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 4;
 parameter PTP_CLK_PERIOD_NS_DENOM = 1;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h2;
 parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1587,7 +1588,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1620,6 +1620,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
index de2c90180..bdbe5c9f1 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 1024,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -75,6 +74,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -1022,8 +1023,8 @@ assign sma_led_red = 1'b0;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -1047,8 +1048,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -1136,7 +1137,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -1182,8 +1183,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -1308,7 +1309,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1343,6 +1343,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1621,8 +1623,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1649,8 +1651,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile
index a1bfde8ea..2545fcdd4 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile
@@ -69,6 +69,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
index 6c7b704e0..c1074cba0 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -637,6 +637,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K35/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K35/Makefile
index ea9a351d1..587c0a2d4 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K35/Makefile
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K35/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -135,6 +136,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K35_app_dma_bench/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K35_app_dma_bench/Makefile
index 40c3b17d8..693fff98d 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K35_app_dma_bench/Makefile
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K35_app_dma_bench/Makefile
@@ -80,6 +80,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -137,6 +138,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P/Makefile
index e0ab6d820..0cff399f6 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P/Makefile
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -136,6 +137,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_10g/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_10g/Makefile
index e0ab6d820..0cff399f6 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_10g/Makefile
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_10g/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -136,6 +137,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_app_dma_bench/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_app_dma_bench/Makefile
index c08734533..fa9585cfe 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_app_dma_bench/Makefile
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_K3P_app_dma_bench/Makefile
@@ -81,6 +81,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -138,6 +139,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
index bd67815a1..4624a73da 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
@@ -41,7 +41,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 1024,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -76,6 +75,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -807,8 +808,8 @@ assign sma_led[1] = 1'b0;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -832,8 +833,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -921,7 +922,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -967,8 +968,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -1093,7 +1094,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1128,6 +1128,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1391,8 +1393,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1419,8 +1421,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k35.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k35.v
index 37b3dfcec..208461c3a 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k35.v
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k35.v
@@ -209,11 +209,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // PCIe interface configuration
@@ -1036,7 +1037,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1069,6 +1069,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k3p.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k3p.v
index 13c211e78..bf6f5f540 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k3p.v
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k3p.v
@@ -208,11 +208,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 4;
 parameter PTP_CLK_PERIOD_NS_DENOM = 1;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h2;
 parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // PCIe interface configuration
@@ -1151,7 +1152,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1184,6 +1184,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile
index 092854fea..b52955887 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile
@@ -70,6 +70,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
index efb68a976..b5896aad3 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -630,6 +630,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile
index f29e4dc46..25cfa15bd 100644
--- a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -137,6 +138,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile
index f29e4dc46..25cfa15bd 100644
--- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -137,6 +138,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile
index e79c92116..941867bc4 100644
--- a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile
@@ -82,6 +82,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
@@ -146,6 +147,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v
index 9f9bf4694..94c5f3612 100644
--- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v
@@ -254,11 +254,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 32;
 parameter PTP_CLK_PERIOD_NS_DENOM = 5;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1498,7 +1499,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1531,6 +1531,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v
index fe4147164..22b7809ea 100644
--- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 32,
     parameter PTP_CLK_PERIOD_NS_DENOM = 5,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -75,6 +74,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -793,8 +794,8 @@ assign led[7] = ptp_pps_str;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -818,8 +819,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -907,7 +908,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -953,8 +954,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -1079,7 +1080,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1114,6 +1114,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1392,8 +1394,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1420,8 +1422,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile
index 04594ed04..8518fb184 100644
--- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile
@@ -69,6 +69,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py
index ad82de85a..20d0f1199 100644
--- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -594,6 +594,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
index 858de987f..bcb204a3b 100644
--- a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
@@ -60,6 +60,7 @@ SYN_FILES += rtl/common/cmac_pad.v
 SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -118,6 +119,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile
index 69056d2a2..79a6cd03c 100644
--- a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@@ -128,6 +129,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus.tcl b/fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus.tcl
index af9cc8265..87c9bc38f 100644
--- a/fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus.tcl
+++ b/fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus.tcl
@@ -12,7 +12,8 @@ set_property -dict [list \
     CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \
     CONFIG.RX_CHECK_ACK {1} \
     CONFIG.INCLUDE_RS_FEC {1} \
-    CONFIG.ENABLE_TIME_STAMPING {1}
+    CONFIG.ENABLE_TIME_STAMPING {1} \
+    CONFIG.PTP_TRANSPCLK_MODE {1}
 ] [get_ips cmac_usplus]
 
 # disable LOC constraint
diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
index 4603dab8b..48d1bdf16 100644
--- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
@@ -264,9 +264,10 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 32;
 parameter PTP_CLK_PERIOD_NS_DENOM = 5;
-parameter PTP_TS_WIDTH = 96;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1560,7 +1561,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1593,6 +1593,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
index 4acce5e06..fc6ab7d39 100644
--- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
@@ -37,7 +37,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 32,
     parameter PTP_CLK_PERIOD_NS_DENOM = 5,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -70,6 +69,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -815,8 +816,8 @@ wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -842,8 +843,8 @@ wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -861,15 +862,10 @@ wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_en;
 wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_req;
 wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_ack;
 
-wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp2_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp1_rx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp2_rx_ptp_time_int;
-
-assign qsfp1_tx_ptp_time = qsfp1_tx_ptp_time_int >> 16;
-assign qsfp2_tx_ptp_time = qsfp2_tx_ptp_time_int >> 16;
-assign qsfp1_rx_ptp_time = qsfp1_rx_ptp_time_int >> 16;
-assign qsfp2_rx_ptp_time = qsfp2_rx_ptp_time_int >> 16;
+assign qsfp1_tx_ptp_time[79:48] = 0;
+assign qsfp2_tx_ptp_time[79:48] = 0;
+assign qsfp1_rx_ptp_time[79:48] = 0;
+assign qsfp2_rx_ptp_time[79:48] = 0;
 
 mqnic_port_map_mac_axis #(
     .MAC_COUNT(2),
@@ -895,7 +891,7 @@ mqnic_port_map_mac_axis_inst (
 
     .mac_tx_ptp_clk(2'b00),
     .mac_tx_ptp_rst(2'b00),
-    .mac_tx_ptp_ts_96({qsfp2_tx_ptp_time_int, qsfp1_tx_ptp_time_int}),
+    .mac_tx_ptp_ts_96({qsfp2_tx_ptp_time[47:0], qsfp1_tx_ptp_time[47:0]}),
     .mac_tx_ptp_ts_step(),
 
     .m_axis_mac_tx_tdata({qsfp2_tx_axis_tdata, qsfp1_tx_axis_tdata}),
@@ -905,7 +901,7 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_mac_tx_tlast({qsfp2_tx_axis_tlast, qsfp1_tx_axis_tlast}),
     .m_axis_mac_tx_tuser({qsfp2_tx_axis_tuser, qsfp1_tx_axis_tuser}),
 
-    .s_axis_mac_tx_ptp_ts({{qsfp2_tx_ptp_ts, 16'd0}, {qsfp1_tx_ptp_ts, 16'd0}}),
+    .s_axis_mac_tx_ptp_ts({qsfp2_tx_ptp_ts[47:0], qsfp1_tx_ptp_ts[47:0]}),
     .s_axis_mac_tx_ptp_ts_tag({qsfp2_tx_ptp_ts_tag, qsfp1_tx_ptp_ts_tag}),
     .s_axis_mac_tx_ptp_ts_valid({qsfp2_tx_ptp_ts_valid, qsfp1_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
@@ -922,7 +918,7 @@ mqnic_port_map_mac_axis_inst (
 
     .mac_rx_ptp_clk(2'b00),
     .mac_rx_ptp_rst(2'b00),
-    .mac_rx_ptp_ts_96({qsfp2_rx_ptp_time_int, qsfp1_rx_ptp_time_int}),
+    .mac_rx_ptp_ts_96({qsfp2_rx_ptp_time[47:0], qsfp1_rx_ptp_time[47:0]}),
     .mac_rx_ptp_ts_step(),
 
     .s_axis_mac_rx_tdata({qsfp2_rx_axis_tdata, qsfp1_rx_axis_tdata}),
@@ -930,7 +926,7 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tvalid({qsfp2_rx_axis_tvalid, qsfp1_rx_axis_tvalid}),
     .s_axis_mac_rx_tready(),
     .s_axis_mac_rx_tlast({qsfp2_rx_axis_tlast, qsfp1_rx_axis_tlast}),
-    .s_axis_mac_rx_tuser({{qsfp2_rx_axis_tuser[80:1], 16'd0, qsfp2_rx_axis_tuser[0]}, {qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}}),
+    .s_axis_mac_rx_tuser({qsfp2_rx_axis_tuser[48:0], qsfp1_rx_axis_tuser[48:0]}),
 
     .mac_rx_enable({qsfp2_rx_enable, qsfp1_rx_enable}),
     .mac_rx_status({qsfp2_rx_status, qsfp1_rx_status}),
@@ -947,8 +943,8 @@ mqnic_port_map_mac_axis_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_96(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts_96(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .s_axis_tx_tdata(axis_eth_tx_tdata),
     .s_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -974,8 +970,8 @@ mqnic_port_map_mac_axis_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_96(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts_96(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .m_axis_rx_tdata(axis_eth_rx_tdata),
     .m_axis_rx_tkeep(axis_eth_rx_tkeep),
@@ -1019,7 +1015,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1054,6 +1049,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1332,8 +1329,8 @@ core_inst (
 
     .eth_tx_ptp_clk(eth_tx_ptp_clk),
     .eth_tx_ptp_rst(eth_tx_ptp_rst),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1360,8 +1357,8 @@ core_inst (
 
     .eth_rx_ptp_clk(eth_rx_ptp_clk),
     .eth_rx_ptp_rst(eth_rx_ptp_rst),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
index 13b67290b..291218945 100644
--- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
@@ -58,6 +58,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
 VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
index 6c6370ecb..9c61ba2a2 100644
--- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -625,6 +625,7 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile
index ce521f3b4..006a5fc59 100644
--- a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -137,6 +138,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile
index ce521f3b4..006a5fc59 100644
--- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -137,6 +138,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
index 1010c2a4d..3ef2d8331 100644
--- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
@@ -271,11 +271,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 32;
 parameter PTP_CLK_PERIOD_NS_DENOM = 5;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1679,7 +1680,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1712,6 +1712,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
index f4785493a..fcb1c8df7 100644
--- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 32,
     parameter PTP_CLK_PERIOD_NS_DENOM = 5,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -75,6 +74,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -936,8 +937,8 @@ assign led[7] = ptp_pps_str;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -961,8 +962,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -1050,7 +1051,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -1096,8 +1097,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -1222,7 +1223,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1257,6 +1257,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1535,8 +1537,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1563,8 +1565,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
index 6b2d41be9..e85ba3eff 100644
--- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
@@ -69,6 +69,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
index 76837f0a5..63e546858 100644
--- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -641,6 +641,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile
index 8401a7a4f..b32a6361c 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile
@@ -59,6 +59,7 @@ SYN_FILES += rtl/common/cmac_pad.v
 SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -117,6 +118,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile
index 169be442c..3400b1a63 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile
@@ -62,6 +62,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@@ -127,6 +128,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/ip/cmac_usplus.tcl b/fpga/mqnic/XUPP3R/fpga_100g/ip/cmac_usplus.tcl
index af9cc8265..87c9bc38f 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/ip/cmac_usplus.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_100g/ip/cmac_usplus.tcl
@@ -12,7 +12,8 @@ set_property -dict [list \
     CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \
     CONFIG.RX_CHECK_ACK {1} \
     CONFIG.INCLUDE_RS_FEC {1} \
-    CONFIG.ENABLE_TIME_STAMPING {1}
+    CONFIG.ENABLE_TIME_STAMPING {1} \
+    CONFIG.PTP_TRANSPCLK_MODE {1}
 ] [get_ips cmac_usplus]
 
 # disable LOC constraint
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
index 40bd3d3fe..2e74ed13a 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
@@ -327,9 +327,10 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 512;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -2276,7 +2277,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -2309,6 +2309,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
index 4280fe018..501562ef7 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
@@ -37,7 +37,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 512,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -70,6 +69,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -1158,8 +1159,8 @@ wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -1185,8 +1186,8 @@ wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -1204,23 +1205,14 @@ wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_en;
 wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_req;
 wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_ack;
 
-wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp2_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp3_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp0_rx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp1_rx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp2_rx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp3_rx_ptp_time_int;
-
-assign qsfp0_tx_ptp_time = qsfp0_tx_ptp_time_int >> 16;
-assign qsfp1_tx_ptp_time = qsfp1_tx_ptp_time_int >> 16;
-assign qsfp2_tx_ptp_time = qsfp2_tx_ptp_time_int >> 16;
-assign qsfp3_tx_ptp_time = qsfp3_tx_ptp_time_int >> 16;
-assign qsfp0_rx_ptp_time = qsfp0_rx_ptp_time_int >> 16;
-assign qsfp1_rx_ptp_time = qsfp1_rx_ptp_time_int >> 16;
-assign qsfp2_rx_ptp_time = qsfp2_rx_ptp_time_int >> 16;
-assign qsfp3_rx_ptp_time = qsfp3_rx_ptp_time_int >> 16;
+assign qsfp0_tx_ptp_time[79:48] = 0;
+assign qsfp1_tx_ptp_time[79:48] = 0;
+assign qsfp2_tx_ptp_time[79:48] = 0;
+assign qsfp3_tx_ptp_time[79:48] = 0;
+assign qsfp0_rx_ptp_time[79:48] = 0;
+assign qsfp1_rx_ptp_time[79:48] = 0;
+assign qsfp2_rx_ptp_time[79:48] = 0;
+assign qsfp3_rx_ptp_time[79:48] = 0;
 
 mqnic_port_map_mac_axis #(
     .MAC_COUNT(4),
@@ -1246,7 +1238,7 @@ mqnic_port_map_mac_axis_inst (
 
     .mac_tx_ptp_clk(4'b0000),
     .mac_tx_ptp_rst(4'b0000),
-    .mac_tx_ptp_ts_96({qsfp3_tx_ptp_time_int, qsfp2_tx_ptp_time_int, qsfp1_tx_ptp_time_int, qsfp0_tx_ptp_time_int}),
+    .mac_tx_ptp_ts_96({qsfp3_tx_ptp_time[47:0], qsfp2_tx_ptp_time[47:0], qsfp1_tx_ptp_time[47:0], qsfp0_tx_ptp_time[47:0]}),
     .mac_tx_ptp_ts_step(),
 
     .m_axis_mac_tx_tdata({qsfp3_tx_axis_tdata, qsfp2_tx_axis_tdata, qsfp1_tx_axis_tdata, qsfp0_tx_axis_tdata}),
@@ -1256,7 +1248,7 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_mac_tx_tlast({qsfp3_tx_axis_tlast, qsfp2_tx_axis_tlast, qsfp1_tx_axis_tlast, qsfp0_tx_axis_tlast}),
     .m_axis_mac_tx_tuser({qsfp3_tx_axis_tuser, qsfp2_tx_axis_tuser, qsfp1_tx_axis_tuser, qsfp0_tx_axis_tuser}),
 
-    .s_axis_mac_tx_ptp_ts({{qsfp3_tx_ptp_ts, 16'd0}, {qsfp2_tx_ptp_ts, 16'd0}, {qsfp1_tx_ptp_ts, 16'd0}, {qsfp0_tx_ptp_ts, 16'd0}}),
+    .s_axis_mac_tx_ptp_ts({qsfp3_tx_ptp_ts[47:0], qsfp2_tx_ptp_ts[47:0], qsfp1_tx_ptp_ts[47:0], qsfp0_tx_ptp_ts[47:0]}),
     .s_axis_mac_tx_ptp_ts_tag({qsfp3_tx_ptp_ts_tag, qsfp2_tx_ptp_ts_tag, qsfp1_tx_ptp_ts_tag, qsfp0_tx_ptp_ts_tag}),
     .s_axis_mac_tx_ptp_ts_valid({qsfp3_tx_ptp_ts_valid, qsfp2_tx_ptp_ts_valid, qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
@@ -1273,7 +1265,7 @@ mqnic_port_map_mac_axis_inst (
 
     .mac_rx_ptp_clk(4'b0000),
     .mac_rx_ptp_rst(4'b0000),
-    .mac_rx_ptp_ts_96({qsfp3_rx_ptp_time_int, qsfp2_rx_ptp_time_int, qsfp1_rx_ptp_time_int, qsfp0_rx_ptp_time_int}),
+    .mac_rx_ptp_ts_96({qsfp3_rx_ptp_time[47:0], qsfp2_rx_ptp_time[47:0], qsfp1_rx_ptp_time[47:0], qsfp0_rx_ptp_time[47:0]}),
     .mac_rx_ptp_ts_step(),
 
     .s_axis_mac_rx_tdata({qsfp3_rx_axis_tdata, qsfp2_rx_axis_tdata, qsfp1_rx_axis_tdata, qsfp0_rx_axis_tdata}),
@@ -1281,7 +1273,7 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tvalid({qsfp3_rx_axis_tvalid, qsfp2_rx_axis_tvalid, qsfp1_rx_axis_tvalid, qsfp0_rx_axis_tvalid}),
     .s_axis_mac_rx_tready(),
     .s_axis_mac_rx_tlast({qsfp3_rx_axis_tlast, qsfp2_rx_axis_tlast, qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}),
-    .s_axis_mac_rx_tuser({{qsfp3_rx_axis_tuser[80:1], 16'd0, qsfp3_rx_axis_tuser[0]}, {qsfp2_rx_axis_tuser[80:1], 16'd0, qsfp2_rx_axis_tuser[0]}, {qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}),
+    .s_axis_mac_rx_tuser({qsfp3_rx_axis_tuser[48:0], qsfp2_rx_axis_tuser[48:0], qsfp1_rx_axis_tuser[48:0], qsfp0_rx_axis_tuser[48:0]}),
 
     .mac_rx_enable({qsfp3_rx_enable, qsfp2_rx_enable, qsfp1_rx_enable, qsfp0_rx_enable}),
     .mac_rx_status({qsfp3_rx_status, qsfp2_rx_status, qsfp1_rx_status, qsfp0_rx_status}),
@@ -1298,8 +1290,8 @@ mqnic_port_map_mac_axis_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_96(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts_96(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .s_axis_tx_tdata(axis_eth_tx_tdata),
     .s_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -1325,8 +1317,8 @@ mqnic_port_map_mac_axis_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_96(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts_96(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .m_axis_rx_tdata(axis_eth_rx_tdata),
     .m_axis_rx_tkeep(axis_eth_rx_tkeep),
@@ -1370,7 +1362,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1405,6 +1396,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1683,8 +1676,8 @@ core_inst (
 
     .eth_tx_ptp_clk(eth_tx_ptp_clk),
     .eth_tx_ptp_rst(eth_tx_ptp_rst),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1711,8 +1704,8 @@ core_inst (
 
     .eth_rx_ptp_clk(eth_rx_ptp_clk),
     .eth_rx_ptp_rst(eth_rx_ptp_rst),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
index e591f8aef..0afcc1bcc 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
@@ -58,6 +58,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
 VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
index 83f32d151..dba3f9939 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -621,6 +621,7 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/Makefile
index ee72d9ea9..fa2ff4a68 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -136,6 +137,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/Makefile
index ee72d9ea9..fa2ff4a68 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUPP3R_10g/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -136,6 +137,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/Makefile
index 8026e9413..4e18e796e 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -136,6 +137,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/Makefile
index 8026e9413..4e18e796e 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_10g/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -136,6 +137,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/Makefile
index 938e19bfd..49d8cb503 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S_app_dma_bench/Makefile
@@ -81,6 +81,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
@@ -145,6 +146,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
index ef407f024..138fdea65 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
@@ -42,7 +42,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 512,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -77,6 +76,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -1313,8 +1314,8 @@ assign led[3] = !ptp_pps_str;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -1338,8 +1339,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -1427,7 +1428,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -1473,8 +1474,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -1599,7 +1600,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1634,6 +1634,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1912,8 +1914,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1940,8 +1942,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v
index 5fb47e4ca..344f6a0da 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v
+++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xupp3r.v
@@ -334,11 +334,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 512;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -2507,7 +2508,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -2540,6 +2540,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v
index 677a39d57..12fbe97d5 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v
+++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_xusp3s.v
@@ -340,11 +340,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 512;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -2530,7 +2531,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -2563,6 +2563,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
index 411bd9e95..3fcab9f61 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
@@ -69,6 +69,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
index 71b3a70b5..9ab44af30 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -638,6 +638,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/ZCU102/fpga/fpga/Makefile b/fpga/mqnic/ZCU102/fpga/fpga/Makefile
index a11a04848..cdd133e14 100644
--- a/fpga/mqnic/ZCU102/fpga/fpga/Makefile
+++ b/fpga/mqnic/ZCU102/fpga/fpga/Makefile
@@ -75,6 +75,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -117,6 +118,7 @@ XDC_FILES = fpga.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ZCU102/fpga/fpga_app_custom_port_demo/Makefile b/fpga/mqnic/ZCU102/fpga/fpga_app_custom_port_demo/Makefile
index 3eba9d557..ee12d9990 100644
--- a/fpga/mqnic/ZCU102/fpga/fpga_app_custom_port_demo/Makefile
+++ b/fpga/mqnic/ZCU102/fpga/fpga_app_custom_port_demo/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -120,6 +121,7 @@ XDC_FILES = fpga.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile
index c492a3992..31c7bcabe 100644
--- a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
@@ -126,6 +127,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v
index 31e825f38..02ac688a5 100644
--- a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v
+++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v
@@ -218,11 +218,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 32;
 parameter PTP_CLK_PERIOD_NS_DENOM = 5;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -988,7 +989,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1021,6 +1021,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v
index 21dd8b1de..34d52e47b 100644
--- a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v
@@ -41,7 +41,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 32,
     parameter PTP_CLK_PERIOD_NS_DENOM = 5,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -76,6 +75,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -660,8 +661,8 @@ assign led[7] = ptp_pps_str;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -685,8 +686,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -774,7 +775,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -820,8 +821,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -946,7 +947,6 @@ mqnic_core_axi #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -981,6 +981,8 @@ mqnic_core_axi #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1239,8 +1241,8 @@ core_inst (
 
     .tx_ptp_clk(0),
     .tx_ptp_rst(0),
-    .tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_tx_tdata(axis_eth_tx_tdata),
     .m_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -1267,8 +1269,8 @@ core_inst (
 
     .rx_ptp_clk(0),
     .rx_ptp_rst(0),
-    .rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_rx_tdata(axis_eth_rx_tdata),
     .s_axis_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core_custom_port_demo.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core_custom_port_demo.v
index 4297669c4..9be4bfc6b 100644
--- a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core_custom_port_demo.v
+++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core_custom_port_demo.v
@@ -49,7 +49,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 32,
     parameter PTP_CLK_PERIOD_NS_DENOM = 5,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -84,6 +83,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -798,8 +799,8 @@ assign led[7] = ptp_pps_str;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -823,8 +824,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -912,7 +913,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -958,8 +959,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -1084,7 +1085,6 @@ mqnic_core_axi #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1119,6 +1119,8 @@ mqnic_core_axi #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1382,8 +1384,8 @@ core_inst (
 
     .tx_ptp_clk(0),
     .tx_ptp_rst(0),
-    .tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_tx_tdata(axis_eth_tx_tdata),
     .m_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -1410,8 +1412,8 @@ core_inst (
 
     .rx_ptp_clk(0),
     .rx_ptp_rst(0),
-    .rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_rx_tdata(axis_eth_rx_tdata),
     .s_axis_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga_custom_port_demo.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga_custom_port_demo.v
index 6e4e1f6f9..15be7b099 100644
--- a/fpga/mqnic/ZCU102/fpga/rtl/fpga_custom_port_demo.v
+++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga_custom_port_demo.v
@@ -231,11 +231,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 32;
 parameter PTP_CLK_PERIOD_NS_DENOM = 5;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1001,7 +1002,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1034,6 +1034,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile
index 1f7f63fc1..cd4e46bf1 100644
--- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile
@@ -66,6 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
index 0b4e0f62c..25774d336 100644
--- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
@@ -400,6 +400,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/Makefile
index b20bcbf77..a683e92d0 100644
--- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/Makefile
+++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/Makefile
@@ -68,6 +68,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/test_fpga_core.py
index 5a93c6a77..a0410cc28 100644
--- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/test_fpga_core.py
+++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/test_fpga_core.py
@@ -405,6 +405,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
index 4c78c4d73..62fe13a16 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -135,6 +136,7 @@ XDC_FILES = fpga.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile
index e095fe6c4..94e787ba6 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile
@@ -82,6 +82,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
@@ -144,6 +145,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
index 79cfc9941..4ff4d6d30 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
+++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
@@ -219,11 +219,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 32;
 parameter PTP_CLK_PERIOD_NS_DENOM = 5;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1041,7 +1042,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1074,6 +1074,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
index e49c2fbd9..810c1708b 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
+++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 32,
     parameter PTP_CLK_PERIOD_NS_DENOM = 5,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -75,6 +74,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -651,8 +652,8 @@ assign led[7] = ptp_pps_str;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -676,8 +677,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -765,7 +766,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -811,8 +812,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -937,7 +938,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -972,6 +972,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1250,8 +1252,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1278,8 +1280,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
index ecefcd38e..36afd564d 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
@@ -69,6 +69,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
index bab18d1a7..d57546310 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
@@ -626,6 +626,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile
index a6c6f1497..82e49d8e2 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile
@@ -75,6 +75,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -117,6 +118,7 @@ XDC_FILES = fpga.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile
index f5a801543..fdc225113 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile
@@ -78,6 +78,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
@@ -126,6 +127,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
index c3ab59eae..8a5210925 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
@@ -208,11 +208,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 32;
 parameter PTP_CLK_PERIOD_NS_DENOM = 5;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h6;
 parameter IF_PTP_PERIOD_FNS = 16'h6666;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -909,7 +910,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -942,6 +942,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
index 33eb225e0..2281de49c 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
@@ -41,7 +41,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 32,
     parameter PTP_CLK_PERIOD_NS_DENOM = 5,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -76,6 +75,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -614,8 +615,8 @@ assign led[7] = ptp_pps_str;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -639,8 +640,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -728,7 +729,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -774,8 +775,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -900,7 +901,6 @@ mqnic_core_axi #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -935,6 +935,8 @@ mqnic_core_axi #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1193,8 +1195,8 @@ core_inst (
 
     .tx_ptp_clk(0),
     .tx_ptp_rst(0),
-    .tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_tx_tdata(axis_eth_tx_tdata),
     .m_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -1221,8 +1223,8 @@ core_inst (
 
     .rx_ptp_clk(0),
     .rx_ptp_rst(0),
-    .rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_rx_tdata(axis_eth_rx_tdata),
     .s_axis_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile
index 1f7f63fc1..cd4e46bf1 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile
@@ -66,6 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py
index c2edcc3a3..f28820d21 100644
--- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py
@@ -400,6 +400,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile
index 35fbe6c95..2283429c3 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += rtl/common/led_sreg_driver.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -119,6 +120,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile
index 8c2c6e3b5..26e3c8ace 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile
@@ -64,6 +64,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@@ -129,6 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile
index 38b76d7a9..e9606ce56 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile
@@ -65,6 +65,7 @@ SYN_FILES += lib/axi/rtl/axil_ram.v
 
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -123,6 +124,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile
index 130114bbd..b75317a69 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile
@@ -63,6 +63,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += rtl/common/led_sreg_driver.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -121,6 +122,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_100g/ip/cmac_usplus.tcl b/fpga/mqnic/fb2CG/fpga_100g/ip/cmac_usplus.tcl
index af9cc8265..87c9bc38f 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/ip/cmac_usplus.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/ip/cmac_usplus.tcl
@@ -12,7 +12,8 @@ set_property -dict [list \
     CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \
     CONFIG.RX_CHECK_ACK {1} \
     CONFIG.INCLUDE_RS_FEC {1} \
-    CONFIG.ENABLE_TIME_STAMPING {1}
+    CONFIG.ENABLE_TIME_STAMPING {1} \
+    CONFIG.PTP_TRANSPCLK_MODE {1}
 ] [get_ips cmac_usplus]
 
 # disable LOC constraint
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
index fa08d12f8..ec16a8f7d 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
@@ -293,9 +293,10 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -1925,7 +1926,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -1958,6 +1958,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
index e993b22b0..2659c30a8 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
@@ -37,7 +37,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 1024,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -70,6 +69,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -872,8 +873,8 @@ wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -899,8 +900,8 @@ wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -918,15 +919,10 @@ wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_en;
 wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_req;
 wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_ack;
 
-wire [PTP_TS_WIDTH-1:0] qsfp_0_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_1_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_0_rx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_1_rx_ptp_time_int;
-
-assign qsfp_0_tx_ptp_time = qsfp_0_tx_ptp_time_int >> 16;
-assign qsfp_1_tx_ptp_time = qsfp_1_tx_ptp_time_int >> 16;
-assign qsfp_0_rx_ptp_time = qsfp_0_rx_ptp_time_int >> 16;
-assign qsfp_1_rx_ptp_time = qsfp_1_rx_ptp_time_int >> 16;
+assign qsfp_0_tx_ptp_time[79:48] = 0;
+assign qsfp_1_tx_ptp_time[79:48] = 0;
+assign qsfp_0_rx_ptp_time[79:48] = 0;
+assign qsfp_1_rx_ptp_time[79:48] = 0;
 
 mqnic_port_map_mac_axis #(
     .MAC_COUNT(2),
@@ -952,7 +948,7 @@ mqnic_port_map_mac_axis_inst (
 
     .mac_tx_ptp_clk(2'b00),
     .mac_tx_ptp_rst(2'b00),
-    .mac_tx_ptp_ts_96({qsfp_1_tx_ptp_time_int, qsfp_0_tx_ptp_time_int}),
+    .mac_tx_ptp_ts_96({qsfp_1_tx_ptp_time[47:0], qsfp_0_tx_ptp_time[47:0]}),
     .mac_tx_ptp_ts_step(),
 
     .m_axis_mac_tx_tdata({qsfp_1_tx_axis_tdata, qsfp_0_tx_axis_tdata}),
@@ -962,7 +958,7 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_mac_tx_tlast({qsfp_1_tx_axis_tlast, qsfp_0_tx_axis_tlast}),
     .m_axis_mac_tx_tuser({qsfp_1_tx_axis_tuser, qsfp_0_tx_axis_tuser}),
 
-    .s_axis_mac_tx_ptp_ts({{qsfp_1_tx_ptp_ts, 16'd0}, {qsfp_0_tx_ptp_ts, 16'd0}}),
+    .s_axis_mac_tx_ptp_ts({qsfp_1_tx_ptp_ts[47:0], qsfp_0_tx_ptp_ts[47:0]}),
     .s_axis_mac_tx_ptp_ts_tag({qsfp_1_tx_ptp_ts_tag, qsfp_0_tx_ptp_ts_tag}),
     .s_axis_mac_tx_ptp_ts_valid({qsfp_1_tx_ptp_ts_valid, qsfp_0_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
@@ -979,7 +975,7 @@ mqnic_port_map_mac_axis_inst (
 
     .mac_rx_ptp_clk(2'b00),
     .mac_rx_ptp_rst(2'b00),
-    .mac_rx_ptp_ts_96({qsfp_1_rx_ptp_time_int, qsfp_0_rx_ptp_time_int}),
+    .mac_rx_ptp_ts_96({qsfp_1_rx_ptp_time[47:0], qsfp_0_rx_ptp_time[47:0]}),
     .mac_rx_ptp_ts_step(),
 
     .s_axis_mac_rx_tdata({qsfp_1_rx_axis_tdata, qsfp_0_rx_axis_tdata}),
@@ -987,7 +983,7 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tvalid({qsfp_1_rx_axis_tvalid, qsfp_0_rx_axis_tvalid}),
     .s_axis_mac_rx_tready(),
     .s_axis_mac_rx_tlast({qsfp_1_rx_axis_tlast, qsfp_0_rx_axis_tlast}),
-    .s_axis_mac_rx_tuser({{qsfp_1_rx_axis_tuser[80:1], 16'd0, qsfp_1_rx_axis_tuser[0]}, {qsfp_0_rx_axis_tuser[80:1], 16'd0, qsfp_0_rx_axis_tuser[0]}}),
+    .s_axis_mac_rx_tuser({qsfp_1_rx_axis_tuser[48:0], qsfp_0_rx_axis_tuser[48:0]}),
 
     .mac_rx_enable({qsfp_1_rx_enable, qsfp_0_rx_enable}),
     .mac_rx_status({qsfp_1_rx_status, qsfp_0_rx_status}),
@@ -1004,8 +1000,8 @@ mqnic_port_map_mac_axis_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_96(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts_96(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .s_axis_tx_tdata(axis_eth_tx_tdata),
     .s_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -1031,8 +1027,8 @@ mqnic_port_map_mac_axis_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_96(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts_96(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .m_axis_rx_tdata(axis_eth_rx_tdata),
     .m_axis_rx_tkeep(axis_eth_rx_tkeep),
@@ -1076,7 +1072,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1111,6 +1106,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1389,8 +1386,8 @@ core_inst (
 
     .eth_tx_ptp_clk(eth_tx_ptp_clk),
     .eth_tx_ptp_rst(eth_tx_ptp_rst),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1417,8 +1414,8 @@ core_inst (
 
     .eth_rx_ptp_clk(eth_rx_ptp_clk),
     .eth_rx_ptp_rst(eth_rx_ptp_rst),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
index 91ae8cd00..862b296ad 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
@@ -59,6 +59,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
 VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
index 8cdecfa88..006af7b53 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -622,6 +622,7 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile
index 9dc810a94..e88a47d90 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -137,6 +138,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile
index 9dc810a94..e88a47d90 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile
@@ -79,6 +79,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -137,6 +138,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile
index 9777add8d..8dd498bc8 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile
@@ -80,6 +80,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -138,6 +139,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
index 75fef11d9..30c952dc2 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
@@ -301,11 +301,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h2;
 parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -2056,7 +2057,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -2091,6 +2091,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
index b3baac528..17262290c 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 1024,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -75,6 +74,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -994,8 +995,8 @@ assign led_exp[1] = 1'b1;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -1019,8 +1020,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -1154,8 +1155,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -1280,7 +1281,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1315,6 +1315,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1593,8 +1595,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1621,8 +1623,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
index acd127547..cb8a317c5 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
@@ -70,6 +70,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
index 33f7fa179..8263e5549 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -638,6 +638,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile b/fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile
index 45b58ad2a..24d947b5b 100644
--- a/fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/fb4CGg3/fpga_100g/fpga/Makefile
@@ -61,6 +61,7 @@ SYN_FILES += rtl/common/mac_ts_insert.v
 SYN_FILES += rtl/common/led_sreg_driver.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -119,6 +120,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile
index 795cc21ef..235e8b919 100644
--- a/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/Makefile
@@ -64,6 +64,7 @@ SYN_FILES += app/dma_bench/rtl/dma_bench.v
 SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
@@ -129,6 +130,7 @@ XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/ip/cmac_usplus.tcl b/fpga/mqnic/fb4CGg3/fpga_100g/ip/cmac_usplus.tcl
index af9cc8265..87c9bc38f 100644
--- a/fpga/mqnic/fb4CGg3/fpga_100g/ip/cmac_usplus.tcl
+++ b/fpga/mqnic/fb4CGg3/fpga_100g/ip/cmac_usplus.tcl
@@ -12,7 +12,8 @@ set_property -dict [list \
     CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \
     CONFIG.RX_CHECK_ACK {1} \
     CONFIG.INCLUDE_RS_FEC {1} \
-    CONFIG.ENABLE_TIME_STAMPING {1}
+    CONFIG.ENABLE_TIME_STAMPING {1} \
+    CONFIG.PTP_TRANSPCLK_MODE {1}
 ] [get_ips cmac_usplus]
 
 # disable LOC constraint
diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v
index a80ec0bd6..411d854d7 100644
--- a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v
@@ -310,9 +310,10 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -2163,7 +2164,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -2196,6 +2196,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v
index eaf26be98..a6af9674f 100644
--- a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v
@@ -37,7 +37,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 1024,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -70,6 +69,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -1125,8 +1126,8 @@ wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -1152,8 +1153,8 @@ wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_ptp_rst;
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -1171,23 +1172,14 @@ wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_en;
 wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_req;
 wire [PORT_COUNT*8-1:0]                       eth_rx_pfc_ack;
 
-wire [PTP_TS_WIDTH-1:0] qsfp_0_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_1_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_2_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_3_tx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_0_rx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_1_rx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_2_rx_ptp_time_int;
-wire [PTP_TS_WIDTH-1:0] qsfp_3_rx_ptp_time_int;
-
-assign qsfp_0_tx_ptp_time = qsfp_0_tx_ptp_time_int >> 16;
-assign qsfp_1_tx_ptp_time = qsfp_1_tx_ptp_time_int >> 16;
-assign qsfp_2_tx_ptp_time = qsfp_2_tx_ptp_time_int >> 16;
-assign qsfp_3_tx_ptp_time = qsfp_3_tx_ptp_time_int >> 16;
-assign qsfp_0_rx_ptp_time = qsfp_0_rx_ptp_time_int >> 16;
-assign qsfp_1_rx_ptp_time = qsfp_1_rx_ptp_time_int >> 16;
-assign qsfp_2_rx_ptp_time = qsfp_2_rx_ptp_time_int >> 16;
-assign qsfp_3_rx_ptp_time = qsfp_3_rx_ptp_time_int >> 16;
+assign qsfp_0_tx_ptp_time[79:48] = 0;
+assign qsfp_1_tx_ptp_time[79:48] = 0;
+assign qsfp_2_tx_ptp_time[79:48] = 0;
+assign qsfp_3_tx_ptp_time[79:48] = 0;
+assign qsfp_0_rx_ptp_time[79:48] = 0;
+assign qsfp_1_rx_ptp_time[79:48] = 0;
+assign qsfp_2_rx_ptp_time[79:48] = 0;
+assign qsfp_3_rx_ptp_time[79:48] = 0;
 
 mqnic_port_map_mac_axis #(
     .MAC_COUNT(4),
@@ -1213,7 +1205,7 @@ mqnic_port_map_mac_axis_inst (
 
     .mac_tx_ptp_clk(4'b0000),
     .mac_tx_ptp_rst(4'b0000),
-    .mac_tx_ptp_ts_96({qsfp_3_tx_ptp_time_int, qsfp_2_tx_ptp_time_int, qsfp_1_tx_ptp_time_int, qsfp_0_tx_ptp_time_int}),
+    .mac_tx_ptp_ts_96({qsfp_3_tx_ptp_time[47:0], qsfp_2_tx_ptp_time[47:0], qsfp_1_tx_ptp_time[47:0], qsfp_0_tx_ptp_time[47:0]}),
     .mac_tx_ptp_ts_step(),
 
     .m_axis_mac_tx_tdata({qsfp_3_tx_axis_tdata, qsfp_2_tx_axis_tdata, qsfp_1_tx_axis_tdata, qsfp_0_tx_axis_tdata}),
@@ -1223,7 +1215,7 @@ mqnic_port_map_mac_axis_inst (
     .m_axis_mac_tx_tlast({qsfp_3_tx_axis_tlast, qsfp_2_tx_axis_tlast, qsfp_1_tx_axis_tlast, qsfp_0_tx_axis_tlast}),
     .m_axis_mac_tx_tuser({qsfp_3_tx_axis_tuser, qsfp_2_tx_axis_tuser, qsfp_1_tx_axis_tuser, qsfp_0_tx_axis_tuser}),
 
-    .s_axis_mac_tx_ptp_ts({{qsfp_3_tx_ptp_ts, 16'd0}, {qsfp_2_tx_ptp_ts, 16'd0}, {qsfp_1_tx_ptp_ts, 16'd0}, {qsfp_0_tx_ptp_ts, 16'd0}}),
+    .s_axis_mac_tx_ptp_ts({qsfp_3_tx_ptp_ts[47:0], qsfp_2_tx_ptp_ts[47:0], qsfp_1_tx_ptp_ts[47:0], qsfp_0_tx_ptp_ts[47:0]}),
     .s_axis_mac_tx_ptp_ts_tag({qsfp_3_tx_ptp_ts_tag, qsfp_2_tx_ptp_ts_tag, qsfp_1_tx_ptp_ts_tag, qsfp_0_tx_ptp_ts_tag}),
     .s_axis_mac_tx_ptp_ts_valid({qsfp_3_tx_ptp_ts_valid, qsfp_2_tx_ptp_ts_valid, qsfp_1_tx_ptp_ts_valid, qsfp_0_tx_ptp_ts_valid}),
     .s_axis_mac_tx_ptp_ts_ready(),
@@ -1240,7 +1232,7 @@ mqnic_port_map_mac_axis_inst (
 
     .mac_rx_ptp_clk(4'b0000),
     .mac_rx_ptp_rst(4'b0000),
-    .mac_rx_ptp_ts_96({qsfp_3_rx_ptp_time_int, qsfp_2_rx_ptp_time_int, qsfp_1_rx_ptp_time_int, qsfp_0_rx_ptp_time_int}),
+    .mac_rx_ptp_ts_96({qsfp_3_rx_ptp_time[47:0], qsfp_2_rx_ptp_time[47:0], qsfp_1_rx_ptp_time[47:0], qsfp_0_rx_ptp_time[47:0]}),
     .mac_rx_ptp_ts_step(),
 
     .s_axis_mac_rx_tdata({qsfp_3_rx_axis_tdata, qsfp_2_rx_axis_tdata, qsfp_1_rx_axis_tdata, qsfp_0_rx_axis_tdata}),
@@ -1248,7 +1240,7 @@ mqnic_port_map_mac_axis_inst (
     .s_axis_mac_rx_tvalid({qsfp_3_rx_axis_tvalid, qsfp_2_rx_axis_tvalid, qsfp_1_rx_axis_tvalid, qsfp_0_rx_axis_tvalid}),
     .s_axis_mac_rx_tready(),
     .s_axis_mac_rx_tlast({qsfp_3_rx_axis_tlast, qsfp_2_rx_axis_tlast, qsfp_1_rx_axis_tlast, qsfp_0_rx_axis_tlast}),
-    .s_axis_mac_rx_tuser({{qsfp_3_rx_axis_tuser[80:1], 16'd0, qsfp_3_rx_axis_tuser[0]}, {qsfp_2_rx_axis_tuser[80:1], 16'd0, qsfp_2_rx_axis_tuser[0]}, {qsfp_1_rx_axis_tuser[80:1], 16'd0, qsfp_1_rx_axis_tuser[0]}, {qsfp_0_rx_axis_tuser[80:1], 16'd0, qsfp_0_rx_axis_tuser[0]}}),
+    .s_axis_mac_rx_tuser({qsfp_3_rx_axis_tuser[48:0], qsfp_2_rx_axis_tuser[48:0], qsfp_1_rx_axis_tuser[48:0], qsfp_0_rx_axis_tuser[48:0]}),
 
     .mac_rx_enable({qsfp_3_rx_enable, qsfp_2_rx_enable, qsfp_1_rx_enable, qsfp_0_rx_enable}),
     .mac_rx_status({qsfp_3_rx_status, qsfp_2_rx_status, qsfp_1_rx_status, qsfp_0_rx_status}),
@@ -1265,8 +1257,8 @@ mqnic_port_map_mac_axis_inst (
 
     .tx_ptp_clk(eth_tx_ptp_clk),
     .tx_ptp_rst(eth_tx_ptp_rst),
-    .tx_ptp_ts_96(eth_tx_ptp_ts_tod),
-    .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step),
+    .tx_ptp_ts_96(eth_tx_ptp_ts),
+    .tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .s_axis_tx_tdata(axis_eth_tx_tdata),
     .s_axis_tx_tkeep(axis_eth_tx_tkeep),
@@ -1292,8 +1284,8 @@ mqnic_port_map_mac_axis_inst (
 
     .rx_ptp_clk(eth_rx_ptp_clk),
     .rx_ptp_rst(eth_rx_ptp_rst),
-    .rx_ptp_ts_96(eth_rx_ptp_ts_tod),
-    .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step),
+    .rx_ptp_ts_96(eth_rx_ptp_ts),
+    .rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .m_axis_rx_tdata(axis_eth_rx_tdata),
     .m_axis_rx_tkeep(axis_eth_rx_tkeep),
@@ -1337,7 +1329,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1372,6 +1363,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1650,8 +1643,8 @@ core_inst (
 
     .eth_tx_ptp_clk(eth_tx_ptp_clk),
     .eth_tx_ptp_rst(eth_tx_ptp_rst),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1678,8 +1671,8 @@ core_inst (
 
     .eth_rx_ptp_clk(eth_rx_ptp_clk),
     .eth_rx_ptp_rst(eth_rx_ptp_rst),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile
index 14825b959..f54c00c8a 100644
--- a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile
@@ -59,6 +59,7 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
 VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py
index 5e53c5df9..87bdc9e7a 100644
--- a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -617,6 +617,7 @@ def test_fpga_core(request):
         os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile
index 948d37c77..bbd2df4ef 100644
--- a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile
@@ -80,6 +80,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -138,6 +139,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile
index 948d37c77..bbd2df4ef 100644
--- a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile
@@ -80,6 +80,7 @@ SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
 SYN_FILES += lib/eth/rtl/lfsr.v
 SYN_FILES += lib/eth/rtl/ptp_td_phc.v
 SYN_FILES += lib/eth/rtl/ptp_td_leaf.v
+SYN_FILES += lib/eth/rtl/ptp_td_rel2tod.v
 SYN_FILES += lib/eth/rtl/ptp_perout.v
 SYN_FILES += lib/axi/rtl/axil_interconnect.v
 SYN_FILES += lib/axi/rtl/axil_crossbar.v
@@ -138,6 +139,7 @@ XDC_FILES += boot.xdc
 XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
 XDC_FILES += lib/eth/syn/vivado/ptp_td_leaf.tcl
+XDC_FILES += lib/eth/syn/vivado/ptp_td_rel2tod.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
 XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v
index c50c189f6..768da711f 100644
--- a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v
@@ -318,11 +318,12 @@ module fpga #
 // PTP configuration
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
-parameter PTP_TS_WIDTH = 96;
 parameter IF_PTP_PERIOD_NS = 6'h2;
 parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
 
 // Interface configuration
+parameter PTP_TS_FMT_TOD = 0;
+parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48;
 parameter TX_TAG_WIDTH = 16;
 
 // RAM configuration
@@ -2408,7 +2409,6 @@ fpga_core #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@@ -2443,6 +2443,8 @@ fpga_core #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
     .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v
index 70b19329c..81a1e6587 100644
--- a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     // PTP configuration
     parameter PTP_CLK_PERIOD_NS_NUM = 1024,
     parameter PTP_CLK_PERIOD_NS_DENOM = 165,
-    parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
@@ -75,6 +74,8 @@ module fpga_core #
 
     // Interface configuration
     parameter PTP_TS_ENABLE = 1,
+    parameter PTP_TS_FMT_TOD = 0,
+    parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 48,
     parameter TX_CPL_FIFO_DEPTH = 32,
     parameter TX_TAG_WIDTH = 16,
     parameter TX_CHECKSUM_ENABLE = 1,
@@ -1291,8 +1292,8 @@ assign led_bmc_red[1] = 0;
 wire [PORT_COUNT-1:0]                         eth_tx_clk;
 wire [PORT_COUNT-1:0]                         eth_tx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_tx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_tx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_tx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_tx_tkeep;
@@ -1316,8 +1317,8 @@ wire [PORT_COUNT*8-1:0]                       eth_tx_pfc_req;
 wire [PORT_COUNT-1:0]                         eth_rx_clk;
 wire [PORT_COUNT-1:0]                         eth_rx_rst;
 
-wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts_tod;
-wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_tod_step;
+wire [PORT_COUNT*PTP_TS_WIDTH-1:0]            eth_rx_ptp_ts;
+wire [PORT_COUNT-1:0]                         eth_rx_ptp_ts_step;
 
 wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0]     axis_eth_rx_tdata;
 wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0]     axis_eth_rx_tkeep;
@@ -1405,7 +1406,7 @@ generate
             .PTP_PERIOD_NS(IF_PTP_PERIOD_NS),
             .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS),
             .PTP_TS_ENABLE(PTP_TS_ENABLE),
-            .PTP_TS_FMT_TOD(1),
+            .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
             .PTP_TS_WIDTH(PTP_TS_WIDTH),
             .TX_PTP_TS_CTRL_IN_TUSER(0),
             .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE),
@@ -1451,8 +1452,8 @@ generate
             /*
              * PTP
              */
-            .tx_ptp_ts(eth_tx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
-            .rx_ptp_ts(eth_rx_ptp_ts_tod[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
+            .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
             .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
             .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]),
@@ -1577,7 +1578,6 @@ mqnic_core_pcie_us #(
     // PTP configuration
     .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
     .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
-    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
@@ -1612,6 +1612,8 @@ mqnic_core_pcie_us #(
 
     // Interface configuration
     .PTP_TS_ENABLE(PTP_TS_ENABLE),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .TX_CPL_ENABLE(PTP_TS_ENABLE),
     .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
     .TX_TAG_WIDTH(TX_TAG_WIDTH),
@@ -1890,8 +1892,8 @@ core_inst (
 
     .eth_tx_ptp_clk(0),
     .eth_tx_ptp_rst(0),
-    .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod),
-    .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step),
+    .eth_tx_ptp_ts(eth_tx_ptp_ts),
+    .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
 
     .m_axis_eth_tx_tdata(axis_eth_tx_tdata),
     .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
@@ -1918,8 +1920,8 @@ core_inst (
 
     .eth_rx_ptp_clk(0),
     .eth_rx_ptp_rst(0),
-    .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod),
-    .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step),
+    .eth_rx_ptp_ts(eth_rx_ptp_ts),
+    .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
 
     .s_axis_eth_rx_tdata(axis_eth_rx_tdata),
     .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile
index 1c0b44be1..23bdde68f 100644
--- a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile
@@ -70,6 +70,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py
index 67b67cc88..6e32c1370 100644
--- a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -635,6 +635,7 @@ def test_fpga_core(request):
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
         os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_interconnect.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),