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alexforencichalexforencich
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fpga/mqnic: UltraScale devices use qpllrsvd pins for PCIe rate control
Signed-off-by: Alex Forencich <[email protected]>
1 parent 51b9eb2 commit 1f3b739

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22 files changed

+368
-18
lines changed

22 files changed

+368
-18
lines changed

‎fpga/common/rtl/eth_xcvr_phy_10g_gty_quad_wrapper.v

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ module eth_xcvr_phy_10g_gty_quad_wrapper #
1818

1919
// GT type
2020
parameter GT_GTH = 0,
21+
parameter GT_USP = 1,
2122

2223
// PLL parameters
2324
parameter QPLL0_PD = 1'b0,
@@ -288,6 +289,7 @@ if (COUNT > 0) begin : phy1
288289
eth_xcvr_phy_10g_gty_wrapper #(
289290
.HAS_COMMON(1),
290291
.GT_GTH(GT_GTH),
292+
.GT_USP(GT_USP),
291293
// PLL
292294
.QPLL0_PD(QPLL0_PD),
293295
.QPLL1_PD(QPLL1_PD),
@@ -397,6 +399,7 @@ if (COUNT > 1) begin : phy2
397399
eth_xcvr_phy_10g_gty_wrapper #(
398400
.HAS_COMMON(0),
399401
.GT_GTH(GT_GTH),
402+
.GT_USP(GT_USP),
400403
// GT
401404
.GT_TX_PD(GT_2_TX_PD),
402405
.GT_TX_QPLL_SEL(GT_2_TX_QPLL_SEL),
@@ -501,6 +504,7 @@ if (COUNT > 2) begin : phy3
501504
eth_xcvr_phy_10g_gty_wrapper #(
502505
.HAS_COMMON(0),
503506
.GT_GTH(GT_GTH),
507+
.GT_USP(GT_USP),
504508
// GT
505509
.GT_TX_PD(GT_3_TX_PD),
506510
.GT_TX_QPLL_SEL(GT_3_TX_QPLL_SEL),
@@ -605,6 +609,7 @@ if (COUNT > 3) begin : phy4
605609
eth_xcvr_phy_10g_gty_wrapper #(
606610
.HAS_COMMON(0),
607611
.GT_GTH(GT_GTH),
612+
.GT_USP(GT_USP),
608613
// GT
609614
.GT_TX_PD(GT_4_TX_PD),
610615
.GT_TX_QPLL_SEL(GT_4_TX_QPLL_SEL),

‎fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v

Lines changed: 275 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ module eth_xcvr_phy_10g_gty_wrapper #
1919

2020
// GT type
2121
parameter GT_GTH = 0,
22+
parameter GT_USP = 1,
2223

2324
// PLL parameters
2425
parameter QPLL0_PD = 1'b0,
@@ -987,7 +988,7 @@ end
987988

988989
generate
989990

990-
if (HAS_COMMON && !GT_GTH) begin : xcvr_gty_com
991+
if (HAS_COMMON && !GT_GTH && GT_USP) begin : xcvr_gty_com_usp
991992

992993
eth_xcvr_gty_full
993994
eth_xcvr_gty_full_inst (
@@ -1123,7 +1124,7 @@ if (HAS_COMMON && !GT_GTH) begin : xcvr_gty_com
11231124
assign xcvr_qpll1clk_out = qpll1_clk;
11241125
assign xcvr_qpll1refclk_out = qpll1_refclk;
11251126

1126-
end else if (HAS_COMMON && GT_GTH) begin : xcvr_gth_com
1127+
end else if (HAS_COMMON && GT_GTH && GT_USP) begin : xcvr_gth_com_usp
11271128

11281129
eth_xcvr_gth_full
11291130
eth_xcvr_gth_full_inst (
@@ -1259,6 +1260,278 @@ end else if (HAS_COMMON && GT_GTH) begin : xcvr_gth_com
12591260
assign xcvr_qpll1clk_out = qpll1_clk;
12601261
assign xcvr_qpll1refclk_out = qpll1_refclk;
12611262

1263+
end else if (HAS_COMMON && !GT_GTH && !GT_USP) begin : xcvr_gty_com_us
1264+
1265+
eth_xcvr_gty_full
1266+
eth_xcvr_gty_full_inst (
1267+
// Common
1268+
.gtpowergood_out(xcvr_gtpowergood_out),
1269+
.loopback_in(gt_loopback_reg),
1270+
1271+
// DRP
1272+
.drpclk_common_in(drp_clk),
1273+
.drpaddr_common_in(drp_addr_reg),
1274+
.drpdi_common_in(drp_di_reg),
1275+
.drpen_common_in(drp_en_reg_2),
1276+
.drpwe_common_in(drp_we_reg),
1277+
.drpdo_common_out(drp_do_2),
1278+
.drprdy_common_out(drp_rdy_2),
1279+
1280+
.drpclk_in(drp_clk),
1281+
.drpaddr_in(drp_addr_reg),
1282+
.drpdi_in(drp_di_reg),
1283+
.drpen_in(drp_en_reg_1),
1284+
.drpwe_in(drp_we_reg),
1285+
.drpdo_out(drp_do_1),
1286+
.drprdy_out(drp_rdy_1),
1287+
1288+
// PLL
1289+
.gtrefclk00_in(xcvr_gtrefclk00_in),
1290+
.qpll0lock_out(qpll0_lock),
1291+
.qpll0outclk_out(qpll0_clk),
1292+
.qpll0outrefclk_out(qpll0_refclk),
1293+
.gtrefclk01_in(xcvr_gtrefclk01_in),
1294+
.qpll1lock_out(qpll1_lock),
1295+
.qpll1outclk_out(qpll1_clk),
1296+
.qpll1outrefclk_out(qpll1_refclk),
1297+
1298+
.qpll0pd_in(QPLL0_EXT_CTRL ? xcvr_qpll0pd_in : qpll0_pd_reg),
1299+
.qpll0reset_in(QPLL0_EXT_CTRL ? xcvr_qpll0reset_in : qpll0_reset_reg),
1300+
.qpll1pd_in(QPLL1_EXT_CTRL ? xcvr_qpll1pd_in : qpll1_pd_reg),
1301+
.qpll1reset_in(QPLL1_EXT_CTRL ? xcvr_qpll1reset_in : qpll1_reset_reg),
1302+
1303+
.qpllrsvd2_in(QPLL0_EXT_CTRL ? {2'd0, xcvr_qpll0pcierate_in} : 5'd0), // [2:0] : QPLL0 rate
1304+
.qpllrsvd3_in(QPLL1_EXT_CTRL ? {2'd0, xcvr_qpll1pcierate_in} : 5'd0), // [2:0] : QPLL1 rate
1305+
1306+
// Serial data
1307+
.gtytxp_out(xcvr_txp),
1308+
.gtytxn_out(xcvr_txn),
1309+
.gtyrxp_in(xcvr_rxp),
1310+
.gtyrxn_in(xcvr_rxn),
1311+
1312+
// Transmit
1313+
.gtwiz_userclk_tx_reset_in(gt_tx_reset_reg),
1314+
.gtwiz_userclk_tx_srcclk_out(),
1315+
.gtwiz_userclk_tx_usrclk_out(),
1316+
.gtwiz_userclk_tx_usrclk2_out(gt_txusrclk2),
1317+
.gtwiz_userclk_tx_active_out(gt_userclk_tx_active),
1318+
.gtwiz_reset_tx_done_in(tx_reset_done_reg),
1319+
.txpdelecidlemode_in(1'b1),
1320+
.txpd_in(gt_tx_pd_reg ? 2'b11 : 2'b00),
1321+
.gttxreset_in(gt_tx_reset_reg),
1322+
.txpmareset_in(gt_tx_pma_reset_reg),
1323+
.txpcsreset_in(gt_tx_pcs_reset_reg),
1324+
.txresetdone_out(gt_tx_reset_done),
1325+
.txpmaresetdone_out(gt_tx_pma_reset_done),
1326+
.txprogdivreset_in(gt_tx_prgdiv_reset_reg),
1327+
.txprgdivresetdone_out(gt_tx_prgdiv_reset_done),
1328+
.txpllclksel_in(gt_tx_qpll_sel_reg ? 2'b10 : 2'b11),
1329+
.txsysclksel_in(gt_tx_qpll_sel_reg ? 2'b11 : 2'b10),
1330+
.txuserrdy_in(gt_tx_userrdy_reg),
1331+
1332+
.txpolarity_in(gt_txpolarity_sync_reg),
1333+
.txelecidle_in(gt_txelecidle_reg),
1334+
.txinhibit_in(gt_txinhibit_sync_reg),
1335+
.txdiffctrl_in(gt_txdiffctrl_reg),
1336+
.txmaincursor_in(gt_txmaincursor_reg),
1337+
.txprecursor_in(gt_txprecursor_reg),
1338+
.txpostcursor_in(gt_txpostcursor_reg),
1339+
1340+
.txprbsforceerr_in(gt_txprbsforceerr_sync_2_reg ^ gt_txprbsforceerr_sync_3_reg),
1341+
.txprbssel_in(gt_txprbssel_sync_reg),
1342+
1343+
.gtwiz_userdata_tx_in(gt_txdata),
1344+
.txheader_in(gt_txheader),
1345+
.txsequence_in(7'b0),
1346+
1347+
// Receive
1348+
.gtwiz_userclk_rx_reset_in(gt_rx_reset_reg),
1349+
.gtwiz_userclk_rx_srcclk_out(),
1350+
.gtwiz_userclk_rx_usrclk_out(),
1351+
.gtwiz_userclk_rx_usrclk2_out(gt_rxusrclk2),
1352+
.gtwiz_userclk_rx_active_out(gt_userclk_rx_active),
1353+
.gtwiz_reset_rx_done_in(rx_reset_done_reg),
1354+
.rxpd_in(gt_rx_pd_reg ? 2'b11 : 2'b00),
1355+
.gtrxreset_in(gt_rx_reset_reg),
1356+
.rxpmareset_in(gt_rx_pma_reset_reg),
1357+
.rxdfelpmreset_in(gt_rx_dfe_lpm_reset_reg),
1358+
.eyescanreset_in(gt_eyescan_reset_reg),
1359+
.rxpcsreset_in(gt_rx_pcs_reset_reg),
1360+
.rxresetdone_out(gt_rx_reset_done),
1361+
.rxpmaresetdone_out(gt_rx_pma_reset_done),
1362+
.rxprogdivreset_in(gt_rx_prgdiv_reset_reg),
1363+
.rxprgdivresetdone_out(gt_rx_prgdiv_reset_done),
1364+
.rxpllclksel_in(gt_rx_qpll_sel_reg ? 2'b10 : 2'b11),
1365+
.rxsysclksel_in(gt_rx_qpll_sel_reg ? 2'b11 : 2'b10),
1366+
.rxuserrdy_in(gt_rx_userrdy_reg),
1367+
1368+
.rxcdrlock_out(gt_rxcdrlock),
1369+
.rxcdrhold_in(gt_rxcdrhold_reg),
1370+
1371+
.rxlpmen_in(gt_rxlpmen_reg),
1372+
1373+
.dmonitorout_out(gt_dmonitorout),
1374+
1375+
.rxpolarity_in(gt_rxpolarity_sync_reg),
1376+
1377+
.rxprbscntreset_in(gt_rxprbscntreset_sync_2_reg ^ gt_rxprbscntreset_sync_3_reg),
1378+
.rxprbssel_in(gt_rxprbssel_sync_reg),
1379+
.rxprbserr_out(gt_rxprbserr),
1380+
.rxprbslocked_out(gt_rxprbslocked),
1381+
1382+
.eyescandataerror_out(),
1383+
1384+
.rxgearboxslip_in(gt_rxgearboxslip),
1385+
.gtwiz_userdata_rx_out(gt_rxdata),
1386+
.rxdatavalid_out(gt_rxdatavalid),
1387+
.rxheader_out(gt_rxheader),
1388+
.rxheadervalid_out(gt_rxheadervalid),
1389+
.rxstartofseq_out()
1390+
);
1391+
1392+
assign xcvr_qpll0lock_out = qpll0_lock;
1393+
assign xcvr_qpll0clk_out = qpll0_clk;
1394+
assign xcvr_qpll0refclk_out = qpll0_refclk;
1395+
assign xcvr_qpll1lock_out = qpll1_lock;
1396+
assign xcvr_qpll1clk_out = qpll1_clk;
1397+
assign xcvr_qpll1refclk_out = qpll1_refclk;
1398+
1399+
end else if (HAS_COMMON && GT_GTH && !GT_USP) begin : xcvr_gth_com_us
1400+
1401+
eth_xcvr_gth_full
1402+
eth_xcvr_gth_full_inst (
1403+
// Common
1404+
.gtpowergood_out(xcvr_gtpowergood_out),
1405+
.loopback_in(gt_loopback_reg),
1406+
1407+
// DRP
1408+
.drpclk_common_in(drp_clk),
1409+
.drpaddr_common_in(drp_addr_reg),
1410+
.drpdi_common_in(drp_di_reg),
1411+
.drpen_common_in(drp_en_reg_2),
1412+
.drpwe_common_in(drp_we_reg),
1413+
.drpdo_common_out(drp_do_2),
1414+
.drprdy_common_out(drp_rdy_2),
1415+
1416+
.drpclk_in(drp_clk),
1417+
.drpaddr_in(drp_addr_reg),
1418+
.drpdi_in(drp_di_reg),
1419+
.drpen_in(drp_en_reg_1),
1420+
.drpwe_in(drp_we_reg),
1421+
.drpdo_out(drp_do_1),
1422+
.drprdy_out(drp_rdy_1),
1423+
1424+
// PLL
1425+
.gtrefclk00_in(xcvr_gtrefclk00_in),
1426+
.qpll0lock_out(qpll0_lock),
1427+
.qpll0outclk_out(qpll0_clk),
1428+
.qpll0outrefclk_out(qpll0_refclk),
1429+
.gtrefclk01_in(xcvr_gtrefclk01_in),
1430+
.qpll1lock_out(qpll1_lock),
1431+
.qpll1outclk_out(qpll1_clk),
1432+
.qpll1outrefclk_out(qpll1_refclk),
1433+
1434+
.qpll0pd_in(QPLL0_EXT_CTRL ? xcvr_qpll0pd_in : qpll0_pd_reg),
1435+
.qpll0reset_in(QPLL0_EXT_CTRL ? xcvr_qpll0reset_in : qpll0_reset_reg),
1436+
.qpll1pd_in(QPLL1_EXT_CTRL ? xcvr_qpll1pd_in : qpll1_pd_reg),
1437+
.qpll1reset_in(QPLL1_EXT_CTRL ? xcvr_qpll1reset_in : qpll1_reset_reg),
1438+
1439+
.qpllrsvd2_in(QPLL0_EXT_CTRL ? {2'd0, xcvr_qpll0pcierate_in} : 5'd0), // [2:0] : QPLL0 rate
1440+
.qpllrsvd3_in(QPLL1_EXT_CTRL ? {2'd0, xcvr_qpll1pcierate_in} : 5'd0), // [2:0] : QPLL1 rate
1441+
1442+
// Serial data
1443+
.gthtxp_out(xcvr_txp),
1444+
.gthtxn_out(xcvr_txn),
1445+
.gthrxp_in(xcvr_rxp),
1446+
.gthrxn_in(xcvr_rxn),
1447+
1448+
// Transmit
1449+
.gtwiz_userclk_tx_reset_in(gt_tx_reset_reg),
1450+
.gtwiz_userclk_tx_srcclk_out(),
1451+
.gtwiz_userclk_tx_usrclk_out(),
1452+
.gtwiz_userclk_tx_usrclk2_out(gt_txusrclk2),
1453+
.gtwiz_userclk_tx_active_out(gt_userclk_tx_active),
1454+
.gtwiz_reset_tx_done_in(tx_reset_done_reg),
1455+
.txpdelecidlemode_in(1'b1),
1456+
.txpd_in(gt_tx_pd_reg ? 2'b11 : 2'b00),
1457+
.gttxreset_in(gt_tx_reset_reg),
1458+
.txpmareset_in(gt_tx_pma_reset_reg),
1459+
.txpcsreset_in(gt_tx_pcs_reset_reg),
1460+
.txresetdone_out(gt_tx_reset_done),
1461+
.txpmaresetdone_out(gt_tx_pma_reset_done),
1462+
.txprogdivreset_in(gt_tx_prgdiv_reset_reg),
1463+
.txprgdivresetdone_out(gt_tx_prgdiv_reset_done),
1464+
.txpllclksel_in(gt_tx_qpll_sel_reg ? 2'b10 : 2'b11),
1465+
.txsysclksel_in(gt_tx_qpll_sel_reg ? 2'b11 : 2'b10),
1466+
.txuserrdy_in(gt_tx_userrdy_reg),
1467+
1468+
.txpolarity_in(gt_txpolarity_sync_reg),
1469+
.txelecidle_in(gt_txelecidle_reg),
1470+
.txinhibit_in(gt_txinhibit_sync_reg),
1471+
.txdiffctrl_in(gt_txdiffctrl_reg),
1472+
.txmaincursor_in(gt_txmaincursor_reg),
1473+
.txprecursor_in(gt_txprecursor_reg),
1474+
.txpostcursor_in(gt_txpostcursor_reg),
1475+
1476+
.txprbsforceerr_in(gt_txprbsforceerr_sync_2_reg ^ gt_txprbsforceerr_sync_3_reg),
1477+
.txprbssel_in(gt_txprbssel_sync_reg),
1478+
1479+
.gtwiz_userdata_tx_in(gt_txdata),
1480+
.txheader_in(gt_txheader),
1481+
.txsequence_in(7'b0),
1482+
1483+
// Receive
1484+
.gtwiz_userclk_rx_reset_in(gt_rx_reset_reg),
1485+
.gtwiz_userclk_rx_srcclk_out(),
1486+
.gtwiz_userclk_rx_usrclk_out(),
1487+
.gtwiz_userclk_rx_usrclk2_out(gt_rxusrclk2),
1488+
.gtwiz_userclk_rx_active_out(gt_userclk_rx_active),
1489+
.gtwiz_reset_rx_done_in(rx_reset_done_reg),
1490+
.rxpd_in(gt_rx_pd_reg ? 2'b11 : 2'b00),
1491+
.gtrxreset_in(gt_rx_reset_reg),
1492+
.rxpmareset_in(gt_rx_pma_reset_reg),
1493+
.rxdfelpmreset_in(gt_rx_dfe_lpm_reset_reg),
1494+
.eyescanreset_in(gt_eyescan_reset_reg),
1495+
.rxpcsreset_in(gt_rx_pcs_reset_reg),
1496+
.rxresetdone_out(gt_rx_reset_done),
1497+
.rxpmaresetdone_out(gt_rx_pma_reset_done),
1498+
.rxprogdivreset_in(gt_rx_prgdiv_reset_reg),
1499+
.rxprgdivresetdone_out(gt_rx_prgdiv_reset_done),
1500+
.rxpllclksel_in(gt_rx_qpll_sel_reg ? 2'b10 : 2'b11),
1501+
.rxsysclksel_in(gt_rx_qpll_sel_reg ? 2'b11 : 2'b10),
1502+
.rxuserrdy_in(gt_rx_userrdy_reg),
1503+
1504+
.rxcdrlock_out(gt_rxcdrlock),
1505+
.rxcdrhold_in(gt_rxcdrhold_reg),
1506+
1507+
.rxlpmen_in(gt_rxlpmen_reg),
1508+
1509+
.dmonitorout_out(gt_dmonitorout),
1510+
1511+
.rxpolarity_in(gt_rxpolarity_sync_reg),
1512+
1513+
.rxprbscntreset_in(gt_rxprbscntreset_sync_2_reg ^ gt_rxprbscntreset_sync_3_reg),
1514+
.rxprbssel_in(gt_rxprbssel_sync_reg),
1515+
.rxprbserr_out(gt_rxprbserr),
1516+
.rxprbslocked_out(gt_rxprbslocked),
1517+
1518+
.eyescandataerror_out(),
1519+
1520+
.rxgearboxslip_in(gt_rxgearboxslip),
1521+
.gtwiz_userdata_rx_out(gt_rxdata),
1522+
.rxdatavalid_out(gt_rxdatavalid),
1523+
.rxheader_out(gt_rxheader),
1524+
.rxheadervalid_out(gt_rxheadervalid),
1525+
.rxstartofseq_out()
1526+
);
1527+
1528+
assign xcvr_qpll0lock_out = qpll0_lock;
1529+
assign xcvr_qpll0clk_out = qpll0_clk;
1530+
assign xcvr_qpll0refclk_out = qpll0_refclk;
1531+
assign xcvr_qpll1lock_out = qpll1_lock;
1532+
assign xcvr_qpll1clk_out = qpll1_clk;
1533+
assign xcvr_qpll1refclk_out = qpll1_refclk;
1534+
12621535
end else if (!GT_GTH) begin : xcvr_gty
12631536

12641537
eth_xcvr_gty_channel

‎fpga/mqnic/250_SoC/fpga_25g/ip/eth_xcvr_gty.tcl

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
2727
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
2828
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
2929
# PCIe
30-
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
30+
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
31+
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
32+
} else {
33+
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
34+
}
3135
# channel reset
3236
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
3337
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out

‎fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/eth_xcvr_gty.tcl

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
2727
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
2828
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
2929
# PCIe
30-
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
30+
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
31+
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
32+
} else {
33+
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
34+
}
3135
# channel reset
3236
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
3337
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out

‎fpga/mqnic/Alveo/fpga_25g/ip/eth_xcvr_gty.tcl

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
2727
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
2828
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
2929
# PCIe
30-
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
30+
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
31+
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
32+
} else {
33+
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
34+
}
3135
# channel reset
3236
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
3337
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out

‎fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/eth_xcvr_gth.tcl

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,11 @@ lappend extra_pll_ports qpll0pd_in qpll1pd_in
2727
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
2828
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
2929
# PCIe
30-
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
30+
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
31+
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
32+
} else {
33+
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
34+
}
3135
# channel reset
3236
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
3337
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out

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