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vector-op-base.csv
1 | Mnemonic | Category | V operands | G operands | Description | Src Type | Dst Type (dst_width = src_width) | Dst Type (dst_width = 2*src_width) | Dst Type (dst_width = src_width / 2) | Scalar dst behavior (m = 00) |
|---|---|---|---|---|---|---|---|---|---|---|
2 | VADD.X | arith | 2 | 0 | add | S/U | S/U | ILLEGAL | ILLEGAL | First Element |
3 | VFADD.[H,S,D] | arith | 2 | 0 | add | F | F | ILLEGAL | ILLEGAL | First Element |
4 | VADDI.X | arith | 1 | 0 | add immediate | S/U | S/U | ILLEGAL | ILLEGAL | First Element |
5 | VPOPC | arith | 1 | 0 | count bits set | I | I | ILLEGAL | ILLEGAL | First Element |
6 | VSUB.X | arith | 2 | 0 | subtract | I | I | ILLEGAL | ILLEGAL | First Element |
7 | VFSUB.[H,S,D] | arith | 2 | 0 | subtract | F | F | ILLEGAL | ILLEGAL | First Element |
8 | VNEG.X | arith | 1 | 0 | negate | S/U | S/U | ILLEGAL | ILLEGAL | First Element |
9 | VSEQ.X | compare | 2 | 0 | 1 if ==, else 0 | S/U | I | I | ILLEGAL | First Element |
10 | VFEQ.[H.S.D] | compare | 2 | 0 | 1 if ==, else 0 | F | I | I | ILLEGAL | First Element |
11 | VSGE.X | compare | 2 | 0 | 1 if >=, else 0 | S/U | I | I | ILLEGAL | First Element |
12 | VFLE.[H,S,D] | compare | 2 | 0 | 1 if <=, else 0 | F | I | I | ILLEGAL | First Element |
13 | VSLT.X | compare | 2 | 0 | 1 if <, else 0 | S/U | ן | I | ILLEGAL | First Element |
14 | VFLT.[H,S,D] | compare | 2 | 0 | 1 if <, else 0 | F | ן | I | ILLEGAL | First Element |
15 | VSNE.X | compare | 2 | 0 | 1 if <>, else 0 | S/U | ן | I | ILLEGAL | First Element |
16 | VFNE.[H,S,D] | compare | 2 | 0 | 1 if <>, else 0 | F | ן | I | ILLEGAL | First Element |
17 | VFCVT.[X,H,S,D].[X,H,S,D] | convert | 1 | 1 | convert type | S/U,F | F,S/U | ILLEGAL | ILLEGAL | First Element |
18 | VFSGNJ.[H,S,D] | copy/sign | 2 | 0 | FP sign injection | F | F | ILLEGAL | ILLEGAL | First Element |
19 | VFSGNJN.[H,S,D] | copy/sign | 2 | 0 | FP inverted sign injection | F | F | ILLEGAL | ILLEGAL | First Element |
20 | VFSGNJX.[H,S,D] | copy/sign | 2 | 0 | FP xor sign | F | F | ILLEGAL | ILLEGAL | First Element |
21 | VDIV.X[U] | divsqrt | 2 | 0 | divide | S/U | S/U | ILLEGAL | ILLEGAL | First Element |
22 | VFDIV[H,S,D] | divsqrt | 2 | 0 | divide | F | F | ILLEGAL | ILLEGAL | First Element |
23 | VREM.X[U] | divsqrt | 2 | 0 | partial remainder | S/U | S/U | ILLEGAL | ILLEGAL | First Element |
24 | VFREM.[H,S,D] | divsqrt | 2 | 0 | partial remainder | F | F | ILLEGAL | ILLEGAL | First Element |
25 | VFSQRT.[H,S,D] | divsqrt | 1 | 0 | square root | F | F | ILLEGAL | ILLEGAL | First Element |
26 | VFCLASS.[H,S,D] | identify FP | 1 | 0 | FP value class (e.g., 0, inf) | F | F | ILLEGAL | ILLEGAL | First Element |
27 | VL.[B,H,W,D][U] | load | 0 | 1 | load vector (unit stride) | I | B | ILLEGAL | ILLEGAL | First Element |
28 | VFL.[H,S,D] | load | 0 | 1 | load vector (unit stride) | I | F | ILLEGAL | ILLEGAL | First Element |
29 | VLS.[B,H,W,D][U] | load | 0 | 2 | load vector (stride) | I | B | ILLEGAL | ILLEGAL | First Element |
30 | VFLS.[H,S,D] | load | 0 | 2 | load vector (stride) | I | F | ILLEGAL | ILLEGAL | First Element |
31 | VLX.[B,H,W,D][U] | load | 1 | 1 | load vector indexed (gather) | I | B | ILLEGAL | ILLEGAL | First Element |
32 | VFLX.[H,S,D] | load | 1 | 1 | load vector indexed (gather) | I | F | ILLEGAL | ILLEGAL | First Element |
33 | VAND | logical | 2 | 0 | bitwise AND | B | B | ILLEGAL | ILLEGAL | Reduction |
34 | VANDI | logical | 1 | 0 | bitwise AND with immediate | B | B | ILLEGAL | ILLEGAL | Reduction |
35 | VOR | logical | 2 | 0 | bitwise OR | B | B | ILLEGAL | ILLEGAL | Reduction |
36 | VORI | logical | 1 | 0 | bitwise OR with immediate | B | B | ILLEGAL | ILLEGAL | Reduction |
37 | VXOR | logical | 2 | 0 | bitwise XOR | B | B | ILLEGAL | ILLEGAL | Reduction |
38 | VXORI | logical | 1 | 0 | bitwise XOR with immediate | B | B | ILLEGAL | ILLEGAL | Reduction |
39 | VMFIRST | mask | 1 | 0 | index of first TRUE lab -> GPR | B | B | ILLEGAL | ILLEGAL | GPR |
40 | VMPOP | mask | 1 | 0 | Count lsb of elements -> GPR | B | B | ILLEGAL | ILLEGAL | GPR |
41 | VMADD.X[U] | multiply-add | 2 | 0 | Destructive multiply add | S/U | S/U | S/U | ILLEGAL | First Element |
42 | VFMADD.[H,S,D] | multiply-add | 3 | 0 | Multiply add | F | F | F | ILLEGAL | First Element |
43 | VFMSUB.[H,S,D] | multiply-add | 3 | 0 | Multiply subtract | F | F | F | ILLEGAL | First Element |
44 | VMUL.X[U] | multiply-add | 2 | 0 | Multiply | S/U | S/U | ILLEGAL | ILLEGAL | First Element |
45 | VFMUL.[H,S,D] | multiply-add | 2 | 0 | Multiply | F | F | ILLEGAL | ILLEGAL | First Element |
46 | VMULH.X[U] | multiply-add | 2 | 0 | Multiply - return high half | S/U | S/U | ILLEGAL | S/U | First Element |
47 | VEXTRACT | permute | 1 | 1 | extract element -> GPR | B | B | ILLEGAL | ILLEGAL | GPR |
48 | VFEXTRACT | permute | 1 | 1 | extract element -> GPR | B | B | ILLEGAL | ILLEGAL | FPR |
49 | VINSERT | permute | 1 | 2 | insert element(s) from GPR | B | B | ILLEGAL | ILLEGAL | First Element |
50 | VFINSERT | permute | 1 | 2 | insert element(s) from FPR | B | B | ILLEGAL | ILLEGAL | First Element |
51 | VMERGE | permute | 2 | 0 | merge registers | B | B | ILLEGAL | ILLEGAL | First Element |
52 | VSELECT | permute | 2 | 0 | select from source by indicies | B | B | ILLEGAL | ILLEGAL | First Element |
53 | VSLIDEDOWN | permute | 1 | 1 | shift elements down by index | B | B | ILLEGAL | ILLEGAL | First Element |
54 | VSLIDEUP | permute | 1 | 1 | shift elements up by index | B | B | ILLEGAL | ILLEGAL | First Element |
55 | VRGATHER | permute | 2 | 0 | gather elements from vector register | B | B | ILLEGAL | ILLEGAL | First Element |
56 | VCLIP | round | 1 | 1 | clip to narrow | S/U | S/U | ILLEGAL | S/U | First Element |
57 | VCLIPI | round | 1 | 0 | Clip, shift by imm | S/U | S/U | ILLEGAL | S/U | First Element |
58 | VMAX.X | select | 2 | 0 | return max element | S/U | S/U | ILLEGAL | ILLEGAL | First Element |
59 | VFMAX.[H,S,D] | select | 2 | 0 | return max element | F | F | ILLEGAL | ILLEGAL | First Element |
60 | VMIN.X | select | 2 | 0 | return min element | S/U | S/U | ILLEGAL | ILLEGAL | First Element |
61 | VFMIN.[H,S,D] | select | 2 | 0 | return min element | F | F | ILLEGAL | ILLEGAL | First Element |
62 | VREDSUM.X | reduction | 1 | 0 | sum reduction | S/U | S/U | ILLEGAL | ILLEGAL | Reduction |
63 | VREDMIN.X[U] | reduction | 1 | 0 | min reduction | S/U | S/U | ILLEGAL | ILLEGAL | Reduction |
64 | VREDMAX.X[U] | reduction | 1 | 0 | max reduction | S/U | S/U | ILLEGAL | ILLEGAL | Reduction |
65 | VREDAND.X | reduction | 1 | 0 | and reduction | S/U | S/U | ILLEGAL | ILLEGAL | Reduction |
66 | VREDOR.X | reduction | 1 | 0 | or reduction | S/U | S/U | ILLEGAL | ILLEGAL | Reduction |
67 | VREDXOR.X | reduction | 1 | 0 | xor reduction | S/U | S/U | ILLEGAL | ILLEGAL | Reduction |
68 | VFREDSUM.[H,S,D] | reduction | 1 | 0 | sum reduction | F | F | ILLEGAL | ILLEGAL | Reduction |
69 | VFREDMIN.[H,S,D] | reduction | 1 | 0 | min reduction | F | F | ILLEGAL | ILLEGAL | Reduction |
70 | VFREDMAX.[H,S,D] | reduction | 1 | 0 | max reduction | F | F | ILLEGAL | ILLEGAL | Reduction |
71 | VSL | shift | 2 | 0 | Shift Left | I | B | ILLEGAL | ILLEGAL | First Element |
72 | VSLI | shift | 1 | 0 | shift left by immediate | I | B | ILLEGAL | ILLEGAL | First Element |
73 | VSRA | shift | 2 | 0 | Shift Right (arithmetic) | I | B | ILLEGAL | ILLEGAL | First Element |
74 | VSRAI | shift | 1 | 0 | arithmetic shift right by immediate | I | B | ILLEGAL | ILLEGAL | First Element |
75 | VSRL | shift | 2 | 0 | Shift Right (logical) | I | B | ILLEGAL | ILLEGAL | First Element |
76 | VSRLI | shift | 1 | 0 | logical shift right by immediate | I | B | ILLEGAL | ILLEGAL | First Element |
77 | VS.[B,H,W,D][U] | store | 1 | 1 | store vector (unit stride) | I | B | ILLEGAL | ILLEGAL | Write First Element |
78 | VSS.[B,H,W,D][U] | store | 1 | 2 | store vector (stride) | I | B | ILLEGAL | ILLEGAL | Write First Element |
79 | VSX.[B,H,W,D][U] | store | 2 | 1 | store vector indexed (scatter) | I | B | ILLEGAL | ILLEGAL | Write First Element |