{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":161755082,"defaultBranch":"reviewed/trunk","name":"gcc","ownerLogin":"tschwinge","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2018-12-14T08:31:19.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/21753?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1714132752.0","currentOid":""},"activityList":{"items":[{"before":"681ff5ccca153864eb86099eed201838d8d98bc2","after":"f793be787135ce7c52b169bf053af225b4828945","ref":"refs/heads/reviewed/trunk","pushedAt":"2024-07-27T21:04:13.000Z","pushType":"push","commitsCount":321,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"libstdc++: Fix -Wsign-compare warning in <charconv>\n\nCast ptrdiff_t to size_t to avoid a -Wsign-compare warning. We can check\nin __to_chars_i that the ptrdiff_t won't be negative, so that we know\nthe cast is safe.\n\nlibstdc++-v3/ChangeLog:\n\n\t* include/std/charconv (__to_chars_16, __to_chars_10)\n\t(__to_chars_8, __to_chars_2, __to_chars): Cast ptrdiff_t to\n\tsize_t for comparison.\n\t(__to_chars_i): Check for first >= last instead of first == last\n\tfor initial sanity check.","shortMessageHtmlLink":"libstdc++: Fix -Wsign-compare warning in &lt;charconv&gt;"}},{"before":"b644126237a1aa8599f767a5e0bbada1d7286f44","after":"681ff5ccca153864eb86099eed201838d8d98bc2","ref":"refs/heads/reviewed/trunk","pushedAt":"2024-07-15T20:58:21.000Z","pushType":"push","commitsCount":1149,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"[APX NF] Add a pass to convert legacy insn to NF insns\n\nFor APX ccmp, current infrastructure will always generate cstore for\nthe ccmp flag user, like\n\n\tcmpe    %rcx, %r8\n\tccmpnel %rax, %rbx\n\tseta\t%dil\n\tadd\t%rcx, %r9\n\tadd     %r9, %rdx\n\ttestb   %dil, %dil\n\tje\t.L2\n\nFor such case, the legacy add clobbers FLAGS_REG so there should have\nextra cstore to avoid the flag be reset before using it. If the\ninstructions between flag producer and user are NF insns, the setcc/\ntest sequence is not required.\n\nAdd a pass to convert legacy flag clobber insns to their NF counterpart.\nThe convertion only happens when\n1. APX_NF enabled.\n2. For a BB, cstore was find, and there are insns between such cstore\nand next explicit set insn to FLAGS_REG (test or cmp).\n3. All the insns found should have NF counterpart.\n\nThe pass was added after rtl-ifcvt which eliminates some branch when\nprofitable, which could cause some flag-clobbering insn put between\ncstore and jcc.\n\ngcc/ChangeLog:\n\n\t* config/i386/i386.md (has_nf): New define_attr, add to all\n\tnf related patterns.\n\t* config/i386/i386-features.cc (apx_nf_convert): New function\n\tto convert Non-NF insns to their NF counterparts.\n\t(class pass_apx_nf_convert): New pass class.\n\t(make_pass_apx_nf_convert): New.\n\t* config/i386/i386-passes.def: Add pass_apx_nf_convert after\n\trtl_ifcvt.\n\t* config/i386/i386-protos.h (make_pass_apx_nf_convert): Declare.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/i386/apx-nf-2.c: New test.","shortMessageHtmlLink":"[APX NF] Add a pass to convert legacy insn to NF insns"}},{"before":"b8e9fd535d6093e3a24af858364d8517a767b0d7","after":"cd0059a1976303638cea95f216de129334fc04d1","ref":"refs/heads/reviewed/releases/gcc-14","pushedAt":"2024-07-01T12:12:16.000Z","pushType":"push","commitsCount":35,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"Update ChangeLog and version files for release","shortMessageHtmlLink":"Update ChangeLog and version files for release"}},{"before":"b8e9fd535d6093e3a24af858364d8517a767b0d7","after":"b644126237a1aa8599f767a5e0bbada1d7286f44","ref":"refs/heads/reviewed/trunk","pushedAt":"2024-05-30T09:07:36.000Z","pushType":"push","commitsCount":889,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"Align tight&hot loop without considering max skipping bytes.\n\nWhen hot loop is small enough to fix into one cacheline, we should align\nthe loop with ceil_log2 (loop_size) without considering maximum\nskipp bytes. It will help code prefetch.\n\ngcc/ChangeLog:\n\n\t* config/i386/i386.cc (ix86_avoid_jump_mispredicts): Change\n\tgen_pad to gen_max_skip_align.\n\t(ix86_align_loops): New function.\n\t(ix86_reorg): Call ix86_align_loops.\n\t* config/i386/i386.md (pad): Rename to ..\n\t(max_skip_align): .. this, and accept 2 operands for align and\n\tskip.","shortMessageHtmlLink":"Align tight&amp;hot loop without considering max skipping bytes."}},{"before":"f3fdcf4a37a7be07f2acbf5c8ed5e3399440a0ef","after":"b8e9fd535d6093e3a24af858364d8517a767b0d7","ref":"refs/heads/reviewed/trunk","pushedAt":"2024-04-26T15:51:50.000Z","pushType":"push","commitsCount":229,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"amdgcn: Add gfx90c target\n\nAdd support for gfx90c GCN5 APU integrated graphics devices.\nThe LLVM AMDGPU documentation does not list those devices as supported\nby rocm-amdhsa, but it passes most libgomp offloading tests.\nAlthough they are constrainted compared to dGPUs, they might be\ninteresting for learning, experimentation, and testing.\n\ngcc/ChangeLog:\n\n\t* config.gcc: Add gfx90c.\n\t* config/gcn/gcn-hsa.h (NO_SRAM_ECC): Likewise.\n\t* config/gcn/gcn-opts.h (enum processor_type): Likewise.\n\t(TARGET_GFX90c): New macro.\n\t* config/gcn/gcn.cc (gcn_option_override): Handle gfx90c.\n\t(gcn_omp_device_kind_arch_isa): Likewise.\n\t(output_file_start): Likewise.\n\t* config/gcn/gcn.h: Add gfx90c.\n\t* config/gcn/gcn.opt: Likewise.\n\t* config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX90c): New macro.\n\t(get_arch): Handle gfx90c.\n\t(main): Handle EF_AMDGPU_MACH_AMDGCN_GFX90c\n\t* config/gcn/t-omp-device: Add gfx90c.\n\t* doc/install.texi: Likewise.\n\t* doc/invoke.texi: Likewise.\n\nlibgomp/ChangeLog:\n\n\t* plugin/plugin-gcn.c (isa_hsa_name): Handle EF_AMDGPU_MACH_AMDGCN_GFX90c.\n\t(isa_code): Handle gfx90c.\n\t(max_isa_vgprs): Handle EF_AMDGPU_MACH_AMDGCN_GFX90c.\n\nSigned-off-by: Frederik Harwath <frederik@harwath.name>","shortMessageHtmlLink":"amdgcn: Add gfx90c target"}},{"before":null,"after":"b8e9fd535d6093e3a24af858364d8517a767b0d7","ref":"refs/heads/reviewed/releases/gcc-14","pushedAt":"2024-04-26T11:59:12.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"amdgcn: Add gfx90c target\n\nAdd support for gfx90c GCN5 APU integrated graphics devices.\nThe LLVM AMDGPU documentation does not list those devices as supported\nby rocm-amdhsa, but it passes most libgomp offloading tests.\nAlthough they are constrainted compared to dGPUs, they might be\ninteresting for learning, experimentation, and testing.\n\ngcc/ChangeLog:\n\n\t* config.gcc: Add gfx90c.\n\t* config/gcn/gcn-hsa.h (NO_SRAM_ECC): Likewise.\n\t* config/gcn/gcn-opts.h (enum processor_type): Likewise.\n\t(TARGET_GFX90c): New macro.\n\t* config/gcn/gcn.cc (gcn_option_override): Handle gfx90c.\n\t(gcn_omp_device_kind_arch_isa): Likewise.\n\t(output_file_start): Likewise.\n\t* config/gcn/gcn.h: Add gfx90c.\n\t* config/gcn/gcn.opt: Likewise.\n\t* config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX90c): New macro.\n\t(get_arch): Handle gfx90c.\n\t(main): Handle EF_AMDGPU_MACH_AMDGCN_GFX90c\n\t* config/gcn/t-omp-device: Add gfx90c.\n\t* doc/install.texi: Likewise.\n\t* doc/invoke.texi: Likewise.\n\nlibgomp/ChangeLog:\n\n\t* plugin/plugin-gcn.c (isa_hsa_name): Handle EF_AMDGPU_MACH_AMDGCN_GFX90c.\n\t(isa_code): Handle gfx90c.\n\t(max_isa_vgprs): Handle EF_AMDGPU_MACH_AMDGCN_GFX90c.\n\nSigned-off-by: Frederik Harwath <frederik@harwath.name>","shortMessageHtmlLink":"amdgcn: Add gfx90c target"}},{"before":"6dedafe166cc02ae87b6a0699ad61ce3ffc46803","after":"f3fdcf4a37a7be07f2acbf5c8ed5e3399440a0ef","ref":"refs/heads/reviewed/trunk","pushedAt":"2024-04-11T07:30:46.000Z","pushType":"push","commitsCount":283,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"RISC-V: Remove -Wno-psabi for test build option [NFC]\n\nJust notice there are some test case still have -Wno-psabi option,\nwhich is deprecated now.  Remove them all for riscv test cases.\n\nThe below test are passed for this patch.\n* The riscv rvv regression test.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.target/riscv/rvv/base/pr109244.C: Remove deprecated\n\t-Wno-psabi option.\n\t* g++.target/riscv/rvv/base/pr109535.C: Ditto.\n\t* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Ditto.\n\t* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: Ditto.\n\nSigned-off-by: Pan Li <pan2.li@intel.com>","shortMessageHtmlLink":"RISC-V: Remove -Wno-psabi for test build option [NFC]"}},{"before":"6dedafe166cc02ae87b6a0699ad61ce3ffc46803","after":null,"ref":"refs/heads/reviewed/master","pushedAt":"2024-04-11T07:30:23.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"}},{"before":null,"after":"6dedafe166cc02ae87b6a0699ad61ce3ffc46803","ref":"refs/heads/reviewed/trunk","pushedAt":"2024-04-11T07:30:22.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"amdgcn: Prefer V32 on RDNA devices\n\nWe run these devices in wavefrontsize64 for compatibility, but they actually\nonly have 32-lane vectors, natively.  If the upper part of a V64 is masked\noff (as it is in V32) then RDNA devices will skip execution of the upper part\nfor most operations, so this adjustment shouldn't leave too much performance on\nthe table.  One exception is memory instructions, so full wavefrontsize32\nsupport would be better.\n\nThe advantage is that we avoid the missing V64 operations (such as permute and\nvec_extract).\n\ngcc/ChangeLog:\n\n\t* config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode): Prefer V32 on\n\tRDNA devices.","shortMessageHtmlLink":"amdgcn: Prefer V32 on RDNA devices"}},{"before":"ffd47fb63ddc024db847daa07f8ae27fffdfcb28","after":"6dedafe166cc02ae87b6a0699ad61ce3ffc46803","ref":"refs/heads/reviewed/master","pushedAt":"2024-03-25T23:03:44.000Z","pushType":"push","commitsCount":129,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"amdgcn: Prefer V32 on RDNA devices\n\nWe run these devices in wavefrontsize64 for compatibility, but they actually\nonly have 32-lane vectors, natively.  If the upper part of a V64 is masked\noff (as it is in V32) then RDNA devices will skip execution of the upper part\nfor most operations, so this adjustment shouldn't leave too much performance on\nthe table.  One exception is memory instructions, so full wavefrontsize32\nsupport would be better.\n\nThe advantage is that we avoid the missing V64 operations (such as permute and\nvec_extract).\n\ngcc/ChangeLog:\n\n\t* config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode): Prefer V32 on\n\tRDNA devices.","shortMessageHtmlLink":"amdgcn: Prefer V32 on RDNA devices"}},{"before":"ad860cc27b3312f9119c7fecb8638a7c1f6d77c9","after":"ffd47fb63ddc024db847daa07f8ae27fffdfcb28","ref":"refs/heads/reviewed/master","pushedAt":"2024-03-15T16:29:57.000Z","pushType":"push","commitsCount":59,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"testsuite: Fix pr113431.c FAIL on sparc* [PR113431]\n\nAs mentioned in the PR, the new testcase FAILs on sparc*-* due to\nlack of support of misaligned store.\n\nThis patch restricts that to vect_hw_misalign targets.\n\n2024-03-15  Jakub Jelinek  <jakub@redhat.com>\n\n\tPR tree-optimization/113431\n\t* gcc.dg/vect/pr113431.c: Restrict scan-tree-dump-times to\n\tvect_hw_misalign targets.","shortMessageHtmlLink":"testsuite: Fix pr113431.c FAIL on sparc* [PR113431]"}},{"before":"f5a805d82902fe2d6e0a7af8c0e6519f9d25a8f3","after":"ad860cc27b3312f9119c7fecb8638a7c1f6d77c9","ref":"refs/heads/reviewed/master","pushedAt":"2024-03-12T11:11:43.000Z","pushType":"push","commitsCount":25,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"asan: Instrument <retval> stores in callees rather than callers [PR112709]\n\nasan currently instruments since PR69276 r6-6758 fix calls which store\nthe return value into memory on the caller side, before the call it\nverifies the memory is writable.\nNow PR112709 where we ICE on trying to instrument such calls made me\nthink about whether that is what we want to do.\n\nThere are 3 different cases.\n\nOne is when a function returns an aggregate which is passed e.g. in\nregisters, say like struct S { int a[4]; }; returning on x86_64.\nThat would be ideally instrumented in between the actual call and\nstoring of the aggregate into memory, but asan currently mostly\nworks as a GIMPLE pass and arranging for the instrumentation to happen\nat that spot would be really hard.  We could diagnose after the call\nbut generally asan attempts to diagnose stuff before something is\noverwritten rather than after, or keep the current behavior (that is\nwhat this patch does, which has the disadvantage that it can complain\nabout UB even for functions which never return and so never actually store,\nand doesn't check whether the memory wasn't e.g. poisoned during the call)\nor could e.g. instrument both before and after the call (that would have\nthe disadvantage the current state has but at least would check post-factum\nthe store again afterwards).\n\nAnother case is when a function returns an aggregate through a hidden\nreference, struct T { int a[128]; }; on x86_64 or even the above struct S\non ia32 as example.  In the actual program such stores happen when storing\nsomething to <retval> or its parts in the callee, because <retval> there\nexpands to *hidden_retval.  So, IMHO we should instrument those in the\ncallee rather than caller, that is where the writes are and we can do that\neasily.  This is what the patch below does.\n\nAnd the last case is for builtins/internal functions.  Usually those don't\nreturn aggregates, but in case they'd do and can be expanded inline, it is\nbetter to instrument them in the caller (as before) rather than not\ninstrumenting the return stores at all.\n\nI had to tweak the expected output on the PR69276 testcase, because\nwith the patch it keeps previous behavior on x86_64 (structure returned\nin registers, stored in the caller, so reported as UB in A::A()),\nwhile on i686 it changed the behavior and is reported as UB in the\nvnull::operator vec which stores the structure, A::A() is then a frame\nabove it in the backtrace.\n\n2024-03-12  Jakub Jelinek  <jakub@redhat.com>\n\n\tPR sanitizer/112709\n\t* asan.cc (has_stmt_been_instrumented_p): Don't instrument call\n\tstores on the caller side unless it is a call to a builtin or\n\tinternal function or function doesn't return by hidden reference.\n\t(maybe_instrument_call): Likewise.\n\t(instrument_derefs): Instrument stores to RESULT_DECL if\n\treturning by hidden reference.\n\n\t* gcc.dg/asan/pr112709-1.c: New test.\n\t* g++.dg/asan/pr69276.C: Adjust expected output for some targets.","shortMessageHtmlLink":"asan: Instrument &lt;retval&gt; stores in callees rather than callers [PR11…"}},{"before":"9f7afa99c67f039e43019ebd08d14a7f01e2d89c","after":"f5a805d82902fe2d6e0a7af8c0e6519f9d25a8f3","ref":"refs/heads/reviewed/master","pushedAt":"2024-03-09T19:36:33.000Z","pushType":"push","commitsCount":2340,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"AVR: Fix typos in comment, indentation glitches in avr.md.\n\ngcc/\n\t* config/avr/avr.md: Fix typos in comment, indentation glitches\n\tand some other nits.","shortMessageHtmlLink":"AVR: Fix typos in comment, indentation glitches in avr.md."}},{"before":"7dbde0c56a032ec08d8a8b3f39f8f4e419ce5c8f","after":"9f7afa99c67f039e43019ebd08d14a7f01e2d89c","ref":"refs/heads/reviewed/master","pushedAt":"2024-01-09T23:03:16.000Z","pushType":"push","commitsCount":254,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"[committed] Adding missing prototype for __clzhi2 to xstormy port\n\nxstormy16 has failed since the c99 transition due to a missing prototype for\n__clzhi2 in the implementation of stormy16_count_leading_zeros.\n\nThis fixes the missing prototype.  Pushed to the trunk.\n\ninclude/\n\t* longlong.h (__stormy16_count_leading_zeros): Add prototype for\n\t__clzhi2.","shortMessageHtmlLink":"[committed] Adding missing prototype for __clzhi2 to xstormy port"}},{"before":"5f1bed2a7af828103ca23a3546466a23e8dd2f30","after":"7dbde0c56a032ec08d8a8b3f39f8f4e419ce5c8f","ref":"refs/heads/reviewed/master","pushedAt":"2023-12-28T09:13:52.000Z","pushType":"push","commitsCount":197,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"hppa: Fix pr110279-1.c on hppa\n\n2023-12-24  John David Anglin  <danglin@gcc.gnu.org>\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/pr110279-1.c: Add -march=2.0 option on hppa*-*-*.","shortMessageHtmlLink":"hppa: Fix pr110279-1.c on hppa"}},{"before":"36be2a0e91c76da4afcd5ddc37e03f5800396387","after":"5f1bed2a7af828103ca23a3546466a23e8dd2f30","ref":"refs/heads/reviewed/master","pushedAt":"2023-12-16T14:52:46.000Z","pushType":"push","commitsCount":266,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"analyzer: use bit-level granularity for concrete bounds-checking [PR112792]\n\nPR analyzer/112792 reports false positives from -fanalyzer's\nbounds-checking on certain packed structs containing bitfields e.g.\nin the Linux kernel's drivers/dma/idxd/device.c:\n\nunion msix_perm {\n  struct {\n    u32 rsvd2 : 8;\n    u32 pasid : 20;\n  };\n  u32 bits;\n} __attribute__((__packed__));\n\nThe root cause is that the bounds-checking is done using byte offsets\nand ranges; in the above, an access of \"pasid\" is treated as a 32-bit\naccess starting one byte inside the union, thus accessing byte offsets\n1-4 when only offsets 0-3 are valid.\n\nThis patch updates the bounds-checking to use bit offsets and ranges\nwherever possible - for concrete offsets and capacities.  In the above\naccessing \"pasid\" is treated as bits 8-27 of a 32-bit region, fixing the\nfalse positive.\n\nSymbolic offsets and ranges are still handled at byte granularity.\n\ngcc/analyzer/ChangeLog:\n\tPR analyzer/112792\n\t* bounds-checking.cc\n\t(out_of_bounds::oob_region_creation_event_capacity): Rename\n\t\"capacity\" to \"byte_capacity\".  Layout fix.\n\t(out_of_bounds::::add_region_creation_events): Rename\n\t\"capacity\" to \"byte_capacity\".\n\t(class concrete_out_of_bounds): Rename m_out_of_bounds_range to\n\tm_out_of_bounds_bits and convert from a byte_range to a bit_range.\n\t(concrete_out_of_bounds::get_out_of_bounds_bytes): New.\n\t(concrete_past_the_end::concrete_past_the_end): Rename param\n\t\"byte_bound\" to \"bit_bound\".  Initialize m_byte_bound.\n\t(concrete_past_the_end::subclass_equal_p): Update for renaming\n\tof m_byte_bound to m_bit_bound.\n\t(concrete_past_the_end::m_bit_bound): New field.\n\t(concrete_buffer_overflow::concrete_buffer_overflow): Convert\n\tparam \"range\" from byte_range to bit_range.  Rename param\n\t\"byte_bound\" to \"bit_bound\".\n\t(concrete_buffer_overflow::emit): Update for bits vs bytes.\n\t(concrete_buffer_overflow::describe_final_event): Split\n\tinto...\n\t(concrete_buffer_overflow::describe_final_event_as_bytes): ...this\n\t(concrete_buffer_overflow::describe_final_event_as_bits): ...and\n\tthis.\n\t(concrete_buffer_over_read::concrete_buffer_over_read): Convert\n\tparam \"range\" from byte_range to bit_range.  Rename param\n\t\"byte_bound\" to \"bit_bound\".\n\t(concrete_buffer_over_read::emit): Update for bits vs bytes.\n\t(concrete_buffer_over_read::describe_final_event): Split into...\n\t(concrete_buffer_over_read::describe_final_event_as_bytes):\n\t...this\n\t(concrete_buffer_over_read::describe_final_event_as_bits): ...and\n\tthis.\n\t(concrete_buffer_underwrite::concrete_buffer_underwrite): Convert\n\tparam \"range\" from byte_range to bit_range.\n\t(concrete_buffer_underwrite::describe_final_event): Split into...\n\t(concrete_buffer_underwrite::describe_final_event_as_bytes):\n\t...this\n\t(concrete_buffer_underwrite::describe_final_event_as_bits): ...and\n\tthis.\n\t(concrete_buffer_under_read::concrete_buffer_under_read): Convert\n\tparam \"range\" from byte_range to bit_range.\n\t(concrete_buffer_under_read::describe_final_event): Split into...\n\t(concrete_buffer_under_read::describe_final_event_as_bytes):\n\t...this\n\t(concrete_buffer_under_read::describe_final_event_as_bits): ...and\n\tthis.\n\t(region_model::check_region_bounds): Use bits for concrete values,\n\tand rename locals to indicate whether we're dealing with bits or\n\tbytes.  Specifically, replace \"num_bytes_sval\" with\n\t\"num_bits_sval\", and get it from reg's \"get_bit_size_sval\".\n\tReplace \"num_bytes_tree\" with \"num_bits_tree\".  Rename \"capacity\"\n\tto \"byte_capacity\".  Rename \"cst_capacity_tree\" to\n\t\"cst_byte_capacity_tree\".  Replace \"offset\" and\n\t\"num_bytes_unsigned\" with \"bit_offset\" and \"num_bits_unsigned\"\n\trespectively, converting from byte_offset_t to bit_offset_t.\n\tReplace \"out\" and \"read_bytes\" with \"bits_outside\" and \"read_bits\"\n\trespectively, converting from byte_range to bit_range.  Convert\n\t\"buffer\" from byte_range to bit_range.  Replace \"byte_bound\" with\n\t\"bit_bound\".\n\t* region.cc (region::get_bit_size_sval): New.\n\t(offset_region::get_bit_offset): New.\n\t(offset_region::get_bit_size_sval): New.\n\t(sized_region::get_bit_size_sval): New.\n\t(bit_range_region::get_bit_size_sval): New.\n\t* region.h (region::get_bit_size_sval): New vfunc.\n\t(offset_region::get_bit_offset): New decl.\n\t(offset_region::get_bit_size_sval): New decl.\n\t(sized_region::get_bit_size_sval): New decl.\n\t(bit_range_region::get_bit_size_sval): New decl.\n\t* store.cc (bit_range::intersects_p): New, based on\n\tbyte_range::intersects_p.\n\t(bit_range::exceeds_p): New, based on byte_range::exceeds_p.\n\t(bit_range::falls_short_of_p): New, based on\n\tbyte_range::falls_short_of_p.\n\t(byte_range::intersects_p): Delete.\n\t(byte_range::exceeds_p): Delete.\n\t(byte_range::falls_short_of_p): Delete.\n\t* store.h (bit_range::intersects_p): New overload.\n\t(bit_range::exceeds_p): New.\n\t(bit_range::falls_short_of_p): New.\n\t(byte_range::intersects_p): Delete.\n\t(byte_range::exceeds_p): Delete.\n\t(byte_range::falls_short_of_p): Delete.\n\ngcc/testsuite/ChangeLog:\n\tPR analyzer/112792\n\t* c-c++-common/analyzer/out-of-bounds-pr112792.c: New test.\n\nSigned-off-by: David Malcolm <dmalcolm@redhat.com>","shortMessageHtmlLink":"analyzer: use bit-level granularity for concrete bounds-checking [PR1…"}},{"before":"b74981b5cf32ebf4bfffd25e7174b5c80243447a","after":"36be2a0e91c76da4afcd5ddc37e03f5800396387","ref":"refs/heads/reviewed/master","pushedAt":"2023-12-09T11:35:40.000Z","pushType":"push","commitsCount":282,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"driver: Fix memory leak [PR93019]\n\ndriver:finalize used by JIT clears the mdswitches pointer; if it was\nallocated before, that leaks the memory.\n\n2023-12-09  Costas Argyris  <costas.argyris@gmail.com>\n\t    Jakub Jelinek  <jakub@redhat.com>\n\n\tPR driver/93019\n\t* gcc.cc (driver::finalize): Call XDELETEVEC on mdswitches before\n\tclearing it.\n\nSigned-off-by: Costas Argyris <costas.argyris@gmail.com>","shortMessageHtmlLink":"driver: Fix memory leak [PR93019]"}},{"before":"449b6b817ed76173e6475debd02b195ea9dab0a0","after":"b74981b5cf32ebf4bfffd25e7174b5c80243447a","ref":"refs/heads/reviewed/master","pushedAt":"2023-12-02T11:09:15.000Z","pushType":"push","commitsCount":245,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"Testsuite, Darwin: skip -mcmodel=large test\n\n-mcmodel=large is not supported (yet) on Darwin [PR90698]\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/i386/libcall-1.c: Skip on darwin.","shortMessageHtmlLink":"Testsuite, Darwin: skip -mcmodel=large test"}},{"before":"93e92b2e5d686606a4c37d729d0a26dd5fa50ffd","after":"449b6b817ed76173e6475debd02b195ea9dab0a0","ref":"refs/heads/reviewed/master","pushedAt":"2023-11-24T16:21:51.000Z","pushType":"push","commitsCount":458,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"OpenMP: Add -Wopenmp and use it\n\nThe new warning has two purposes: First, it makes clearer to the\nuser that it is about OpenMP and, secondly and more importantly,\nit permits to use -Wno-openmp.\n\nThe newly added -Wopenmp is enabled by default and replaces the\n'0' (always warning) in several OpenMP-related warning calls.\nFor code shared with OpenACC, it only uses OPT_Wopenmp for\n'flag_openmp | flag_openmp_simd'.\n\ngcc/c-family/ChangeLog:\n\n\t* c.opt (Wopenmp): Add, enable by default.\n\ngcc/c/ChangeLog:\n\n\t* c-parser.cc (c_parser_omp_clause_num_threads,\n\tc_parser_omp_clause_num_tasks, c_parser_omp_clause_grainsize,\n\tc_parser_omp_clause_priority, c_parser_omp_clause_schedule,\n\tc_parser_omp_clause_num_teams, c_parser_omp_clause_thread_limit,\n\tc_parser_omp_clause_dist_schedule, c_parser_omp_depobj,\n\tc_parser_omp_scan_loop_body, c_parser_omp_assumption_clauses):\n\tAdd OPT_Wopenmp to warning_at.\n\ngcc/cp/ChangeLog:\n\n\t* parser.cc (cp_parser_omp_clause_dist_schedule,\n\tcp_parser_omp_scan_loop_body, cp_parser_omp_assumption_clauses,\n\tcp_parser_omp_depobj): Add OPT_Wopenmp to warning_at.\n\t* semantics.cc (finish_omp_clauses): Likewise.\n\ngcc/ChangeLog:\n\n\t* doc/invoke.texi (-Wopenmp): Add.\n\t* gimplify.cc (gimplify_omp_for): Add OPT_Wopenmp to warning_at.\n\t* omp-expand.cc (expand_omp_ordered_sink): Likewise.\n\t* omp-general.cc (omp_check_context_selector): Likewise.\n\t* omp-low.cc (scan_omp_for, check_omp_nesting_restrictions,\n\tlower_omp_ordered_clauses): Likewise.\n\t* omp-simd-clone.cc (simd_clone_clauses_extract): Likewise.\n\ngcc/fortran/ChangeLog:\n\n\t* lang.opt (Wopenmp): Add, enabled by dafault and documented in C.\n\t* openmp.cc (gfc_match_omp_declare_target, resolve_positive_int_expr,\n\tresolve_nonnegative_int_expr, resolve_omp_clauses,\n\tgfc_resolve_omp_do_blocks): Use OPT_Wopenmp with gfc_warning{,_now}.","shortMessageHtmlLink":"OpenMP: Add -Wopenmp and use it"}},{"before":"a5922427c29fad177251d89cc946d1c5bfc135eb","after":"93e92b2e5d686606a4c37d729d0a26dd5fa50ffd","ref":"refs/heads/reviewed/master","pushedAt":"2023-11-12T21:20:13.000Z","pushType":"push","commitsCount":52,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"Revert \"[PATCH v2] In the pipeline, USE or CLOBBER should delay execution if it starts a new live range.\"\n\nThis reverts commit 85b49ad863965408668627f10b5b1b106053f319.","shortMessageHtmlLink":"Revert \"[PATCH v2] In the pipeline, USE or CLOBBER should delay execu…"}},{"before":"6e312b2b864bf923a9d772429f014375bf9dabc8","after":"a5922427c29fad177251d89cc946d1c5bfc135eb","ref":"refs/heads/reviewed/master","pushedAt":"2023-11-10T13:09:43.000Z","pushType":"push","commitsCount":47,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"vect: Don't set excess bits in unform masks\n\nAVX ignores any excess bits in the mask (at least for vector sizes >=8), but\nAMD GCN magically uses a larger vector than was intended (the smaller sizes are\n\"fake\"), leading to wrong-code.\n\nThis patch fixes amdgcn execution failures in gcc.dg/vect/pr81740-1.c,\ngfortran.dg/c-interop/contiguous-1.f90,\ngfortran.dg/c-interop/ff-descriptor-7.f90, and others.\n\ngcc/ChangeLog:\n\n\t* expr.cc (store_constructor): Add \"and\" operation to uniform mask\n\tgeneration.","shortMessageHtmlLink":"vect: Don't set excess bits in unform masks"}},{"before":"80f466aa1cce2759112c8b0121964d1bbb158f25","after":"6e312b2b864bf923a9d772429f014375bf9dabc8","ref":"refs/heads/reviewed/master","pushedAt":"2023-11-09T08:58:56.000Z","pushType":"push","commitsCount":29,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"c: Add -Wreturn-mismatch warning, split from -Wreturn-type\n\nThe existing -Wreturn-type option covers both constraint violations\n(which are mandatory to diagnose) and warnings that have known\nfalse positives.  The new -Wreturn-mismatch warning is only about\nthe constraint violations (missing or extra return expressions),\nand should eventually be turned into a permerror.\n\nThe -std=gnu89 test cases show that by default, we do not warn for\nreturn; in a function not returning void.  This matches previous\npractice for -Wreturn-type.\n\ngcc/c-family/\n\n\t* c.opt (Wreturn-mismatch): New.\n\ngcc/c/\n\n\t* c-typeck.cc (c_finish_return): Use pedwarn with\n\tOPT_Wreturn_mismatch for missing/extra return expressions.\n\ngcc/\n\n\t* doc/invoke.texi (Warning Options): Document\n\t-Wreturn-mismatch.  Update -Wreturn-type documentation.\n\ngcc/testsuite/\n\n\t* gcc.dg/Wreturn-mismatch-1.c: New.\n\t* gcc.dg/Wreturn-mismatch-2.c: New.\n\t* gcc.dg/Wreturn-mismatch-3.c: New.\n\t* gcc.dg/Wreturn-mismatch-4.c: New.\n\t* gcc.dg/Wreturn-mismatch-5.c: New.\n\t* gcc.dg/Wreturn-mismatch-6.c: New.\n\t* gcc.dg/noncompile/pr55976-1.c: Change -Werror=return-type\n\tto -Werror=return-mismatch.\n\t* gcc.dg/noncompile/pr55976-2.c: Change -Wreturn-type\n\tto -Wreturn-mismatch.","shortMessageHtmlLink":"c: Add -Wreturn-mismatch warning, split from -Wreturn-type"}},{"before":"0c42741ad95af3a1e3ac07350da4c3a94865ed63","after":"80f466aa1cce2759112c8b0121964d1bbb158f25","ref":"refs/heads/reviewed/master","pushedAt":"2023-11-08T10:51:52.000Z","pushType":"push","commitsCount":92,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"RISC-V: Eliminate unused parameter warning.\n\nThe parameter orig_fndecl is not used, use anonymous parameters instead.\n\n../.././gcc/gcc/config/riscv/riscv-c.cc: In function ‘bool riscv_check_builtin_call(location_t, vec<unsigned int>, tree, tree, unsigned int, tree_node**)’:\n../.././gcc/gcc/config/riscv/riscv-c.cc:207:11: warning: unused parameter ‘orig_fndecl’ [-Wunused-parameter]\n      tree orig_fndecl, unsigned int nargs, tree *args)\n           ^~~~~~~~~~~\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv-c.cc (riscv_check_builtin_call): Eliminate warning.","shortMessageHtmlLink":"RISC-V: Eliminate unused parameter warning."}},{"before":"8c8ad4e3533b8590ce063386b8b32f6fce1c3942","after":"0c42741ad95af3a1e3ac07350da4c3a94865ed63","ref":"refs/heads/reviewed/master","pushedAt":"2023-11-06T11:47:46.000Z","pushType":"push","commitsCount":57,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"internal-fn: Add VCOND_MASK_LEN.\n\nIn order to prevent simplification of a COND_OP with degenerate mask\n(CONSTM1_RTX) into just an OP in the presence of length masking this\npatch introduces a length-masked analog to VEC_COND_EXPR:\nIFN_VCOND_MASK_LEN.\n\nIt also adds new match patterns that allow the combination of\nunconditional unary, binary and ternay operations with the\nVCOND_MASK_LEN into a conditional operation if the target supports it.\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/111760\n\n\t* config/riscv/autovec.md (vcond_mask_len_<mode><vm>): Add\n\texpander.\n\t* config/riscv/riscv-protos.h (enum insn_type): Add.\n\t* config/riscv/riscv-v.cc (needs_fp_rounding): Add !pred_mov.\n\t* doc/md.texi: Add vcond_mask_len.\n\t* gimple-match-exports.cc (maybe_resimplify_conditional_op):\n\tCreate VCOND_MASK_LEN when length masking.\n\t* gimple-match.h (gimple_match_op::gimple_match_op): Always\n\tinitialize len and bias.\n\t* internal-fn.cc (vec_cond_mask_len_direct): Add.\n\t(direct_vec_cond_mask_len_optab_supported_p): Add.\n\t(internal_fn_len_index): Add VCOND_MASK_LEN.\n\t(internal_fn_mask_index): Ditto.\n\t* internal-fn.def (VCOND_MASK_LEN): New internal function.\n\t* match.pd: Combine unconditional unary, binary and ternary\n\toperations into the respective COND_LEN operations.\n\t* optabs.def (OPTAB_D): Add vcond_mask_len optab.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.dg/vect/vect-cond-arith-2.c: No vect cost model for\n\triscv_v.","shortMessageHtmlLink":"internal-fn: Add VCOND_MASK_LEN."}},{"before":"4d3d2cdb574488223d023b590c3a34ddd93f4dae","after":"8c8ad4e3533b8590ce063386b8b32f6fce1c3942","ref":"refs/heads/reviewed/master","pushedAt":"2023-11-03T08:23:37.000Z","pushType":"push","commitsCount":108,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"Fortran: Defined operators with unlimited polymorphic args [PR98498]\n\n2023-11-03  Paul Thomas  <pault@gcc.gnu.org>\n\ngcc/fortran\n\tPR fortran/98498\n\t* interface.cc (upoly_ok): Defined operators using unlimited\n\tpolymorphic formal arguments must not override the intrinsic\n\toperator use.\n\ngcc/testsuite/\n\tPR fortran/98498\n\t* gfortran.dg/interface_50.f90: New test.","shortMessageHtmlLink":"Fortran: Defined operators with unlimited polymorphic args [PR98498]"}},{"before":"8da9146d23829f39cd86854b33fe54781f65c111","after":"4d3d2cdb574488223d023b590c3a34ddd93f4dae","ref":"refs/heads/reviewed/master","pushedAt":"2023-10-27T21:38:42.000Z","pushType":"push","commitsCount":16,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"[RA]: Fixing i686 bootstrap failure because of pushing the equivalence patch\n\nGCC with my recent patch improving cost calculation for pseudos with\nequivalence may generate different code with and without debug info\nand as the result i686 bootstrap fails on i686.  The patch fixes this\nbug.\n\ngcc/ChangeLog:\n\n\tPR rtl-optimization/112107\n\t* ira-costs.cc: (calculate_equiv_gains): Use NONDEBUG_INSN_P\n\tinstead of INSN_P.","shortMessageHtmlLink":"[RA]: Fixing i686 bootstrap failure because of pushing the equivalenc…"}},{"before":"372e2d62bcb27287234f30908af167886611c12a","after":"8da9146d23829f39cd86854b33fe54781f65c111","ref":"refs/heads/reviewed/master","pushedAt":"2023-10-27T10:56:57.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"Move OpenMP tests to gomp subdir\n\ngcc/testsuite/ChangeLog:\n\n\t* gfortran.dg/c_ptr_tests_20.f90: Moved to...\n\t* gfortran.dg/gomp/c_ptr_tests_20.f90: ...here.\n\t* gfortran.dg/c_ptr_tests_21.f90: Moved to...\n\t* gfortran.dg/gomp/c_ptr_tests_21.f90: ...here.","shortMessageHtmlLink":"Move OpenMP tests to gomp subdir"}},{"before":"af4bb221153359f5948da917d5ef2df738bb1e61","after":"372e2d62bcb27287234f30908af167886611c12a","ref":"refs/heads/reviewed/master","pushedAt":"2023-10-27T10:36:11.000Z","pushType":"push","commitsCount":249,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"aarch64: Add basic target_print_operand support for CONST_STRING\n\nMotivated by the need to print system register names in output\nassembly, this patch adds the required logic to\n`aarch64_print_operand' to accept rtxs of type CONST_STRING and\nprocess these accordingly.\n\nConsequently, an rtx such as:\n\n  (set (reg/i:DI 0 x0)\n         (unspec:DI [(const_string (\"s3_3_c13_c2_2\"))])\n\ncan now be output correctly using the following output pattern when\ncomposing `define_insn's:\n\n  \"mrs\\t%x0, %1\"\n\ngcc/ChangeLog\n\n\t* config/aarch64/aarch64.cc (aarch64_print_operand): Add\n\tsupport for CONST_STRING.","shortMessageHtmlLink":"aarch64: Add basic target_print_operand support for CONST_STRING"}},{"before":"d3961765b506f75233e6ea144a80930629c3426b","after":"af4bb221153359f5948da917d5ef2df738bb1e61","ref":"refs/heads/reviewed/master","pushedAt":"2023-10-18T12:05:37.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"OpenMP: Avoid ICE with LTO and 'omp allocate'\n\ngcc/ChangeLog:\n\n\t* gimplify.cc (gimplify_bind_expr): Remove \"omp allocate\" attribute\n\tto avoid that auxillary statement list reaches LTO.\n\ngcc/testsuite/ChangeLog:\n\n\t* gfortran.dg/gomp/allocate-13a.f90: New test.","shortMessageHtmlLink":"OpenMP: Avoid ICE with LTO and 'omp allocate'"}},{"before":"cead92b7fc4d7a545dcf2f02397120e3c9afe1a3","after":"d3961765b506f75233e6ea144a80930629c3426b","ref":"refs/heads/reviewed/master","pushedAt":"2023-10-18T10:33:36.000Z","pushType":"push","commitsCount":17,"pusher":{"login":"tschwinge","name":"Thomas Schwinge","path":"/tschwinge","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/21753?s=80&v=4"},"commit":{"message":"nvptx: Use fatal_error when -march= is missing not an assert [PR111093]\n\ngcc/ChangeLog:\n\n\tPR target/111093\n\t* config/nvptx/nvptx.cc (nvptx_option_override): Issue fatal error\n\tinstead of an assert ICE when no -march= has been specified.","shortMessageHtmlLink":"nvptx: Use fatal_error when -march= is missing not an assert [PR111093]"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEiuA50QA","startCursor":null,"endCursor":null}},"title":"Activity · tschwinge/gcc"}