refac(D1): pull most of the code back into a core crate (#283)

By reintroducing a `mnemos-d1-core` crate, we can put most of the
platform implementation in a crate without a `forced-target`, allowing
us to run unit tests for the platform impl on the build host. The actual
dependencies on `riscv` and `riscv-rt`, which won't build for the host's
target, are now `cfg`-gated. We must still have the crate containing the
top-level binaries have a `forced-target`, or else we hit weird cargo
bugs I don't understand, but it's now a thin wrapper around the `core`
crate which has a `forced-target` and defines the board binaries.

This also has the side benefit of letting us put the `d1-core` crate in
the workspace's `default-members`, so it gets seen by `cargo
test`/`cargo fmt`/etc without having to pass it explicitly. And, we can
have tests now!

Author: hawkw

.vscode/settings.json

@@ -18,5 +18,5 @@
         "--all-targets"
     ],
     "rust-analyzer.workspace.symbol.search.scope": "workspace_and_dependencies",
-    "rust-analyzer.typing.continueCommentsOnNewline": false
+    "rust-analyzer.typing.continueCommentsOnNewline": false,
 }

Cargo.lock

@@ -28,6 +28,7 @@ members = [
     # platforms
     "platforms/allwinner-d1",
     "platforms/allwinner-d1/d1-config",
+    "platforms/allwinner-d1/d1-core",
     "platforms/beepy",
     "platforms/esp32c3-buddy",
     "platforms/melpomene",
@@ -55,6 +56,8 @@ default-members = [
     # platforms
     "platforms/melpomene",
     "platforms/melpomene/melpo-config",
+    "platforms/allwinner-d1/d1-config",
+    "platforms/allwinner-d1/d1-core",
 ]
 # this isn't actually a crate
 exclude = ["source/notes"]

Cargo.toml

@@ -33,7 +33,7 @@ default = ["i2c_puppet", "sharp-display", "serial-trace"]
 # enable i2c_puppet driver
 i2c_puppet = ["mnemos-beepy"]
 # enable the SHARP Memory Display driver
-sharp-display = []
+sharp-display = ["mnemos-d1-core/sharp-display"]
 # enable `mnemos-trace-proto` serial tracing.
 serial-trace = ["mnemos/serial-trace"]
 
@@ -48,7 +48,7 @@ miette = "5.10.0"
 serde = { version = "1.0.178", features = ["derive"], default-features = false }
 d1-config = { path = "./d1-config" }
 mnemos-config = { path = "../../source/config" }
-mnemos-bitslab = { path = "../../source/bitslab" }
+mnemos-d1-core = { path = "./d1-core" }
 
 d1-pac = "0.0.31"
 critical-section = "1.1.1"
@@ -68,14 +68,6 @@ version = "0.1.37"
 features = ["attributes"]
 default-features = false
 
-[dependencies.embedded-graphics]
-version = "0.7.1"
-
-[dependencies.futures]
-version = "0.3.21"
-features = ["async-await"]
-default-features = false
-
 [dependencies.riscv]
 version = "0.10"
 features =[ "critical-section-single-hart"]

platforms/allwinner-d1/Cargo.toml

@@ -4,14 +4,21 @@ This directory contains MnemOS platform support for the Allwinner D1 RISC-V SoC.
 
 ## Folder Layout
 
-* [`src/`]: Rust source code for the Allwinner D1 platform implementation.
+* [`src/`]: The top-level crate that produces MnemOS binaries for the Allwinner
+      D1.
 * [`board-configs/`]: [`mnemos-config`] configurations for supported D1
       single-board computers.
+* [`d1-core/`]: Core MnemOS implementation for the Allwinner D1. This is
+      factored out into a separate crate so that it can be built without
+      `forced-target="riscv64imac-unknown-none-elf"` (unlike the top-level
+      `mnemos-d1` crate), so that unit tests for the platform implementation can
+      be run on development host targets.
 * [`d1-config/`]: [`mnemos-config`] type definition crate for the Allwinner D1.
 
 [`src/`]: ./boards/
 [`board-configs/`]: ./board-configs/
 [`d1-config/`]: ./d1-config/
+[`d1-core/`]: ./d1-core/
 
 ## Getting started with MnemOS on the D1
 

platforms/allwinner-d1/README.md

@@ -0,0 +1,44 @@
+
+cargo-features = ["per-package-target", "profile-rustflags"]
+
+[package]
+name = "mnemos-d1-core"
+version = "0.1.0"
+edition.workspace = true
+repository.workspace = true
+homepage.workspace = true
+license.workspace = true
+
+
+[features]
+# enable the SHARP Memory Display driver
+sharp-display = []
+
+[dependencies]
+serde = { version = "1.0.178", features = ["derive"], default-features = false }
+mnemos-bitslab = { path = "../../../source/bitslab" }
+
+d1-pac = "0.0.31"
+critical-section = "1.1.1"
+
+[target.'cfg(any(target_arch = "riscv64", target_arch = "riscv32"))'.dependencies]
+riscv = "0.10.0"
+riscv-rt = "0.11"
+
+# kernel
+[dependencies.mnemos]
+path = "../../../source/kernel"
+default-features = false
+
+[dependencies.tracing]
+version = "0.1.37"
+features = ["attributes"]
+default-features = false
+
+[dependencies.embedded-graphics]
+version = "0.7.1"
+
+[dependencies.futures]
+version = "0.3.21"
+features = ["async-await"]
+default-features = false

platforms/allwinner-d1/d1-core/Cargo.toml

@@ -35,6 +35,13 @@ impl Clint {
     }
 
     /// Get the (machine) time value.
+    #[cfg(not(any(target_arch = "riscv64", target_arch = "riscv32")))]
+    pub fn get_mtime(&self) -> usize {
+        unimplemented!("called `Clint::get_mtime` on a non-RISC-V architecture, this shouldn't happen while running host tests!")
+    }
+
+    /// Get the (machine) time value.
+    #[cfg(any(target_arch = "riscv64", target_arch = "riscv32"))]
     pub fn get_mtime(&self) -> usize {
         // Note that the CLINT of the C906 core does not implement
         // the `mtime` register and we need to get the time value

platforms/allwinner-d1/src/ccu.rs renamed to platforms/allwinner-d1/d1-core/src/ccu.rs

@@ -51,9 +51,9 @@ pub struct Dmac {
 ///
 /// The DMA controller owns a shared pool of 16 DMA channels, which may be used
 /// by drivers to initiate DMA transfers. Channels can be acquired from the
-/// shared pool using the [`Dmac::claim`] and [`Dmac::try_claim`] methods.
-/// Dropping a `Channel` releases it back to the shared pool, allowing it to be
-/// claimed by other drivers.
+/// shared pool using the [`Dmac::claim_channel`] and
+/// [`Dmac::try_claim_channel`] methods. Dropping a `Channel` releases it back
+/// to the shared pool, allowing it to be claimed by other drivers.
 pub struct Channel {
     idx: u8,
     xfer_done: &'static WaitCell,
@@ -298,7 +298,7 @@ impl Dmac {
     }
 
     /// Handle a DMAC interrupt.
-    pub(crate) fn handle_interrupt() {
+    pub fn handle_interrupt() {
         let dmac = unsafe { &*DMAC::PTR };
         // there are two registers that contain DMA channel IRQ status bits,
         // `DMAC_IRQ_PEND0` and `DMAC_IRQ_PEND1`. the first 8 channels (0-7) set
@@ -334,7 +334,12 @@ impl Dmac {
     ///
     /// This is generally used when shutting down the system, such as in panic
     /// and exception handlers.
-    pub(crate) unsafe fn cancel_all() {
+    ///
+    /// # Safety
+    ///
+    /// Cancelling DMA transfers abruptly might put peripherals in a weird state
+    /// i guess?
+    pub unsafe fn cancel_all() {
         for (i, channel) in STATE.channel_wait.iter().enumerate() {
             channel.close();
             Channel {
@@ -444,10 +449,7 @@ impl Channel {
     /// flight on this channel. This is ensured when using the
     /// [`Channel::transfer`] method, which mutably borrows the channel while
     /// the transfer is in progress, preventing the channel modes from being
-    /// changed. However, if a transfer is started with
-    /// [`Channel::start_descriptor`], it is possible to manipulate the channel
-    /// modes while a transfer is in progress. I don't know what happens if you
-    /// do this, but it's probably bad.
+    /// changed.
     pub unsafe fn set_channel_modes(&mut self, src: ChannelMode, dst: ChannelMode) {
         self.mode_reg().write(|w| {
             match src {
@@ -662,15 +664,6 @@ fn queue_irq_en_offset(idx: u8) -> u8 {
     (idx * 4) + 2
 }
 
-// Unfortunately, we can't define tests in this crate and have them run on the
-// development host machine, because the `mnemos-d1` crate has a `forced-target`
-// in its `Cargo.toml`, and will therefore not compile at all for host
-// architectures, even just to run tests. In the future, we should look into
-// whether it's possible to change our build configurations to allow host tests
-// in this crate.
-// TODO(eliza): if we can run tests for this crate on the build host, we should
-// uncomment these tests.
-/*
 #[cfg(test)]
 mod tests {
     use super::*;
@@ -687,4 +680,3 @@ mod tests {
         assert_eq!(dbg!(queue_irq_en_offset(7)), 30);
     }
 }
-*/