🏠
Home-Office
FPGA-Engineer doing design and verification using VHDL, SystemVerilog, SVA and PSL.
- Dresden, Germany
- https://git.goodcleanfun.de
- @__tmeissner__
- xgcfx
Earned achievements
Public Sponsor
Public Sponsor
Loading
Starstruck
Starstruck
Loading
Pull Shark
x2
Pull Shark
x2

Pull Shark
x2@tmeissner opened pull requests that have been merged.
History
Bronze unlocked
·
First unlocked
2019-09-20 01:48:50 UTC
ghdl/ghdl-yosys-plugin#43 · 2nd pull request merged
ghdl/ghdl#1487 · 16th pull request merged
Arctic Code Vault Contributor
Arctic Code Vault Contributor
Loading