uart_brgene.sv

//=============================================================================
//  basic_uart_tmct: Baud-rate generator
//-----------------------------------------------------------------------------
//  uart_brgene.sv
//  Baud-rate generator part of basic uart
//-----------------------------------------------------------------------------
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//
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//
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//=============================================================================
module uart_brgene
(
    input   logic           i_clk,      // System clock input
    input   logic           i_reset,    // System reset input(high active)
    input   logic   [15:0]  i_prer,     // Baud-rate generator frequency divider parameter
    output  logic           o_txclken,  // Transmit timing signal output (same as baud rate interval)
    output  logic           o_rxclken   // Receive timing signal output (one quarter of the baud rate interval)
);

    logic   [1:0]   txcnt;
    logic   [15:0]  rxprer;
    logic   [15:0]  counter;


    //-------------------------------------------------------------------------
    //  Combinational logic
    //-------------------------------------------------------------------------
    // Generates 4 times the baud rate timing
    always_comb rxprer = ({2'd0, i_prer[15:2]} - {9'd0, i_prer[15:9]} - 16'd1);


    //-------------------------------------------------------------------------
    //  Main counter
    //-------------------------------------------------------------------------
    always_ff @(posedge i_clk, posedge i_reset)
    begin
        if (i_reset)
        begin
            //-----------------------------------------------------------------
            //  Asynchronous reset
            //-----------------------------------------------------------------
            counter <= 15'd0;
            txcnt <= 2'd0;
            o_txclken <= 1'b0;
            o_rxclken <= 1'b0;
        end
        else
        begin
            //-----------------------------------------------------------------
            //  Operational state
            //-----------------------------------------------------------------
            if (counter < rxprer)
            begin
                counter <= counter + 15'd1;
                o_txclken <= 1'b0;
                o_rxclken <= 1'b0;
            end
            else
            begin
                counter <= 15'd0;
                o_rxclken <= 1'b1;
                txcnt <= txcnt + 2'd1;
                if (txcnt == 2'd0) o_txclken <= 1'b1; else o_txclken <= 1'b0;
            end
        end
    end
    
endmodule