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teachopteachop
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formatted astyle -A10 -s2
1 parent f0d1880 commit d536db8

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4 files changed

+60
-45
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4 files changed

+60
-45
lines changed

‎FlexCAN.cpp

Lines changed: 27 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -40,16 +40,16 @@ FlexCAN::FlexCAN(uint32_t baud)
4040
// segment timings from freescale loopback test
4141
if ( 250000 == baud ) {
4242
FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(2) | FLEXCAN_CTRL_RJW(1)
43-
| FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(15));
43+
| FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(15));
4444
} else if ( 500000 == baud ) {
4545
FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(2) | FLEXCAN_CTRL_RJW(1)
46-
| FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(7));
46+
| FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(7));
4747
} else if ( 1000000 == baud ) {
4848
FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(3) | FLEXCAN_CTRL_RJW(0)
49-
| FLEXCAN_CTRL_PSEG1(0) | FLEXCAN_CTRL_PSEG2(1) | FLEXCAN_CTRL_PRESDIV(5));
49+
| FLEXCAN_CTRL_PSEG1(0) | FLEXCAN_CTRL_PSEG2(1) | FLEXCAN_CTRL_PRESDIV(5));
5050
} else { // 125000
5151
FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(2) | FLEXCAN_CTRL_RJW(2)
52-
| FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(31));
52+
| FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(31));
5353
}
5454

5555
// Default mask is allow everything
@@ -75,17 +75,18 @@ void FlexCAN::begin(const CAN_filter_t &mask)
7575
FLEXCAN0_RXMGMASK = 0;
7676

7777
//enable reception of all messages that fit the mask
78-
if (mask.ext)
78+
if (mask.ext) {
7979
FLEXCAN0_RXFGMASK = ((mask.rtr?1:0) << 31) | ((mask.ext?1:0) << 30) | ((mask.id & FLEXCAN_MB_ID_EXT_MASK) << 1);
80-
else
80+
} else {
8181
FLEXCAN0_RXFGMASK = ((mask.rtr?1:0) << 31) | ((mask.ext?1:0) << 30) | (FLEXCAN_MB_ID_IDSTD(mask.id) << 1);
82+
}
8283

8384
// start the CAN
8485
FLEXCAN0_MCR &= ~(FLEXCAN_MCR_HALT);
8586
// wait till exit of freeze mode
8687
while(FLEXCAN0_MCR & FLEXCAN_MCR_FRZ_ACK);
8788

88-
// wait till ready
89+
// wait till ready
8990
while(FLEXCAN0_MCR & FLEXCAN_MCR_NOT_RDY);
9091

9192
//set tx buffers to inactive
@@ -99,10 +100,11 @@ void FlexCAN::begin(const CAN_filter_t &mask)
99100
void FlexCAN::setFilter(const CAN_filter_t &filter, uint8_t n)
100101
{
101102
if ( 8 > n ) {
102-
if (filter.ext)
103+
if (filter.ext) {
103104
FLEXCAN0_IDFLT_TAB(n) = ((filter.rtr?1:0) << 31) | ((filter.ext?1:0) << 30) | ((filter.id & FLEXCAN_MB_ID_EXT_MASK) << 1);
104-
else
105+
} else {
105106
FLEXCAN0_IDFLT_TAB(n) = ((filter.rtr?1:0) << 31) | ((filter.ext?1:0) << 30) | (FLEXCAN_MB_ID_IDSTD(filter.id) << 1);
107+
}
106108
}
107109
}
108110

@@ -130,7 +132,7 @@ int FlexCAN::read(CAN_message_t &msg)
130132
}
131133
yield();
132134
}
133-
135+
134136
// get identifier and dlc
135137
msg.len = FLEXCAN_get_length(FLEXCAN0_MBn_CS(rxb));
136138
msg.ext = (FLEXCAN0_MBn_CS(rxb) & FLEXCAN_MB_CS_IDE)? 1:0;
@@ -141,15 +143,21 @@ int FlexCAN::read(CAN_message_t &msg)
141143

142144
// copy out message
143145
uint32_t dataIn = FLEXCAN0_MBn_WORD0(rxb);
144-
msg.buf[3] = dataIn; dataIn >>=8;
145-
msg.buf[2] = dataIn; dataIn >>=8;
146-
msg.buf[1] = dataIn; dataIn >>=8;
146+
msg.buf[3] = dataIn;
147+
dataIn >>=8;
148+
msg.buf[2] = dataIn;
149+
dataIn >>=8;
150+
msg.buf[1] = dataIn;
151+
dataIn >>=8;
147152
msg.buf[0] = dataIn;
148153
if ( 4 < msg.len ) {
149154
dataIn = FLEXCAN0_MBn_WORD1(rxb);
150-
msg.buf[7] = dataIn; dataIn >>=8;
151-
msg.buf[6] = dataIn; dataIn >>=8;
152-
msg.buf[5] = dataIn; dataIn >>=8;
155+
msg.buf[7] = dataIn;
156+
dataIn >>=8;
157+
msg.buf[6] = dataIn;
158+
dataIn >>=8;
159+
msg.buf[5] = dataIn;
160+
dataIn >>=8;
153161
msg.buf[4] = dataIn;
154162
}
155163
for( int loop=msg.len; loop<8; ++loop ) {
@@ -170,7 +178,7 @@ int FlexCAN::write(const CAN_message_t &msg)
170178
if ( msg.timeout ) {
171179
startMillis = millis();
172180
}
173-
181+
174182
// find an available buffer
175183
int buffer = -1;
176184
for ( int index = txb; ; ) {
@@ -202,10 +210,10 @@ int FlexCAN::write(const CAN_message_t &msg)
202210
FLEXCAN0_MBn_WORD1(buffer) = (msg.buf[4]<<24)|(msg.buf[5]<<16)|(msg.buf[6]<<8)|msg.buf[7];
203211
if(msg.ext) {
204212
FLEXCAN0_MBn_CS(buffer) = FLEXCAN_MB_CS_CODE(FLEXCAN_MB_CODE_TX_ONCE)
205-
| FLEXCAN_MB_CS_LENGTH(msg.len) | FLEXCAN_MB_CS_SRR | FLEXCAN_MB_CS_IDE;
213+
| FLEXCAN_MB_CS_LENGTH(msg.len) | FLEXCAN_MB_CS_SRR | FLEXCAN_MB_CS_IDE;
206214
} else {
207215
FLEXCAN0_MBn_CS(buffer) = FLEXCAN_MB_CS_CODE(FLEXCAN_MB_CODE_TX_ONCE)
208-
| FLEXCAN_MB_CS_LENGTH(msg.len);
216+
| FLEXCAN_MB_CS_LENGTH(msg.len);
209217
}
210218

211219
return 1;

‎FlexCAN.h

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,31 +4,33 @@
44
//
55
#include <Arduino.h>
66

7-
typedef struct CAN_message_t
8-
{
7+
typedef struct CAN_message_t {
98
uint32_t id; // can identifier
109
uint8_t ext; // identifier is extended
1110
uint8_t len; // length of data
1211
uint16_t timeout; // milliseconds, zero will disable waiting
1312
uint8_t buf[8];
1413
} CAN_message_t;
1514

16-
typedef struct CAN_filter_t
17-
{
15+
typedef struct CAN_filter_t {
1816
uint8_t rtr;
1917
uint8_t ext;
2018
uint32_t id;
2119
} CAN_filter_t;
2220

2321
// -------------------------------------------------------------
24-
class FlexCAN {
22+
class FlexCAN
23+
{
2524
private:
2625
struct CAN_filter_t defaultMask;
2726

2827
public:
2928
FlexCAN(uint32_t baud = 125000);
3029
void begin(const CAN_filter_t &mask);
31-
inline void begin() { begin(defaultMask);}
30+
inline void begin()
31+
{
32+
begin(defaultMask);
33+
}
3234
void setFilter(const CAN_filter_t &filter, uint8_t n);
3335
void end(void);
3436
int available(void);

‎examples/CANtest/CANtest.ino

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,8 @@ unsigned int txTimer,rxTimer;
2323

2424

2525
// -------------------------------------------------------------
26-
static void hexDump(uint8_t dumpLen, uint8_t *bytePtr) {
26+
static void hexDump(uint8_t dumpLen, uint8_t *bytePtr)
27+
{
2728
uint8_t working;
2829
while( dumpLen-- ) {
2930
working = *bytePtr++;
@@ -44,7 +45,7 @@ void setup(void)
4445

4546
delay(1000);
4647
Serial.println(F("Hello Teensy 3.1 CAN Test."));
47-
48+
4849
sysTimer.reset();
4950
}
5051

@@ -54,10 +55,14 @@ void loop(void)
5455
{
5556
// service software timers based on Metro tick
5657
if ( sysTimer.check() ) {
57-
if ( txTimer ) --txTimer;
58-
if ( rxTimer ) --rxTimer;
58+
if ( txTimer ) {
59+
--txTimer;
60+
}
61+
if ( rxTimer ) {
62+
--rxTimer;
63+
}
5964
}
60-
65+
6166
// if not time-delayed, read CAN messages and print 1st byte
6267
if ( !rxTimer ) {
6368
while ( CANbus.read(rxmsg) ) {

‎kinetis_flexcan.h

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@ typedef volatile uint32_t vuint32_t;
8080
#define FLEXCAN0_DBG2 (*(vuint32_t*)(FLEXCAN0_BASE+0x5C))
8181

8282
#define FLEXCAN0_IMEUR FLEXCAN0_FUREQ
83-
#define FLEXCAN0_LRFR FLEXCAN0_FUACK
83+
#define FLEXCAN0_LRFR FLEXCAN0_FUACK
8484

8585

8686
/* Message Buffers */
@@ -89,7 +89,7 @@ typedef volatile uint32_t vuint32_t;
8989
#define FLEXCAN0_MB0_WORD0 (*(vuint32_t*)(FLEXCAN0_BASE+0x88))
9090
#define FLEXCAN0_MB0_WORD1 (*(vuint32_t*)(FLEXCAN0_BASE+0x8C))
9191

92-
#define FLEXCAN0_MBn_CS(n) (*(vuint32_t*)(FLEXCAN0_BASE+0x80+n*0x10))
92+
#define FLEXCAN0_MBn_CS(n) (*(vuint32_t*)(FLEXCAN0_BASE+0x80+n*0x10))
9393
#define FLEXCAN0_MBn_ID(n) (*(vuint32_t*)(FLEXCAN0_BASE+0x84+n*0x10))
9494
#define FLEXCAN0_MBn_WORD0(n) (*(vuint32_t*)(FLEXCAN0_BASE+0x88+n*0x10))
9595
#define FLEXCAN0_MBn_WORD1(n) (*(vuint32_t*)(FLEXCAN0_BASE+0x8C+n*0x10))
@@ -158,15 +158,15 @@ typedef volatile uint32_t vuint32_t;
158158
#define FLEXCAN1_DBG2 (*(vuint32_t*)(FLEXCAN1_BASE+0x5C))
159159

160160
#define FLEXCAN1_IMEUR FLEXCAN1_FUREQ
161-
#define FLEXCAN1_LRFR FLEXCAN1_FUACK
161+
#define FLEXCAN1_LRFR FLEXCAN1_FUACK
162162

163163
/* Message Buffers */
164164
#define FLEXCAN1_MB0_CS (*(vuint32_t*)(FLEXCAN1_BASE+0x80))
165165
#define FLEXCAN1_MB0_ID (*(vuint32_t*)(FLEXCAN1_BASE+0x84))
166166
#define FLEXCAN1_MB0_WORD0 (*(vuint32_t*)(FLEXCAN1_BASE+0x88))
167167
#define FLEXCAN1_MB0_WORD1 (*(vuint32_t*)(FLEXCAN1_BASE+0x8C))
168168

169-
#define FLEXCAN1_MBn_CS(n) (*(vuint32_t*)(FLEXCAN1_BASE+0x80+n*0x10))
169+
#define FLEXCAN1_MBn_CS(n) (*(vuint32_t*)(FLEXCAN1_BASE+0x80+n*0x10))
170170
#define FLEXCAN1_MBn_ID(n) (*(vuint32_t*)(FLEXCAN1_BASE+0x84+n*0x10))
171171
#define FLEXCAN1_MBn_WORD0(n) (*(vuint32_t*)(FLEXCAN1_BASE+0x88+n*0x10))
172172
#define FLEXCAN1_MBn_WORD1(n) (*(vuint32_t*)(FLEXCAN1_BASE+0x8C+n*0x10))
@@ -181,7 +181,7 @@ typedef volatile uint32_t vuint32_t;
181181
#define FLEXCAN1_IDFLT_TAB(n) (*(vuint32_t*)(FLEXCAN1_BASE+0xE0+(n<<2)))
182182

183183
/* Memory Error Control Register */
184-
#define FLEXCAN1_MECR *(vuint32_t*)(FLEXCAN1_BASE+0x7B70))
184+
#define FLEXCAN1_MECR *(vuint32_t*)(FLEXCAN1_BASE+0x7B70))
185185

186186
/* Error Injection Address Register */
187187
#define FLEXCAN1_ERRIAR *(vuint32_t*)(FLEXCAN1_BASE+0x3B74))
@@ -410,7 +410,7 @@ typedef volatile uint32_t vuint32_t;
410410
#define FLEXCAN_ESR2_LOSTRLF (0x00000004)
411411
#define FLEXCAN_ESR2_LOSTRMF (0x00000002)
412412
#define FLEXCAN_ESR2_IMEUF (0x00000001)
413-
#define FLEXCAN_get_LTM(esr2_value) (((esr2_value) & (FLEXCAN_ESR2_LTM))>>(FLEXCAN_ESR2_LTM_BIT_NO))
413+
#define FLEXCAN_get_LTM(esr2_value) (((esr2_value) & (FLEXCAN_ESR2_LTM))>>(FLEXCAN_ESR2_LTM_BIT_NO))
414414

415415
/* Bit definitions and macros for FLEXCAN_IMASK1 */
416416
#define FLEXCAN_IMASK1_BUF0M (0x00000001)
@@ -1086,7 +1086,7 @@ typedef volatile uint32_t vuint32_t;
10861086
#define FLEXCAN_IMEUR_IMEUP_BIT_NO (0)
10871087
#define FLEXCAN_IMEUR_IMEUREQ_MASK (0x00000100)
10881088
#define FLEXCAN_IMEUR_IMEUACK_MASK (0x00000200)
1089-
#define FLEXCAN_Set_IMEUP(imeur,imeup) imeur = (imeur & ~(FLEXCAN_IMEUR_IMEUP_MASK)) | (imeup & FLEXCAN_IMEUR_IMEUP_MASK)
1089+
#define FLEXCAN_Set_IMEUP(imeur,imeup) imeur = (imeur & ~(FLEXCAN_IMEUR_IMEUP_MASK)) | (imeup & FLEXCAN_IMEUR_IMEUP_MASK)
10901090
#define FLEXCAN_Get_IMEUP(imeur) (imeur & FLEXCAN_IMEUR_IMEUP_MASK)
10911091

10921092
/* Bit definition for Lost Rx Frames Register (LRFR)
@@ -1099,7 +1099,7 @@ typedef volatile uint32_t vuint32_t;
10991099
#define FLEXCAN_LRFR_LOSTRMP_BIT_NO (0)
11001100
#define FLEXCAN_Get_LostMBLocked(lrfr) ((lrfr & FLEXCAN_LRFR_LOSTRLP_MASK)>>(FLEXCAN_LRFR_LOSTRLP_BIT_NO))
11011101
#define FLEXCAN_Get_LostMBUpdated(lrfr) ((lrfr & FLEXCAN_LRFR_LOSTRMP_MASK))
1102-
1102+
11031103
/* Bit definition for Memory Error Control Register */
11041104
#define FLEXCAN_MECR_NCEFAFRZ_MASK (0x00000080)
11051105
#define FLEXCAN_MECR_RERRDIS_MASK (0x00000100)
@@ -1110,24 +1110,24 @@ typedef volatile uint32_t vuint32_t;
11101110
#define FLEXCAN_MECR_FANCEI_MSK_MAKS (0x00040000)
11111111
#define FLEXCAN_MECR_HANCEI_MSK_MAKS (0x00080000)
11121112
#define FLEXCAN_MECR_ECRWRDIS_MSK_MAKS (0x80000000)
1113-
1113+
11141114
/* Bit definition for Error Report Address Register (RERRAR) */
11151115
#define FLEXCAN_RERRAR_NCE_MASK (0x01000000)
11161116
#define FLEXCAN_RERRAR_SAID_MASK (0x00070000)
1117-
#define FLEXCAN_ERRADDR_MASK (0x00003FFF)
1117+
#define FLEXCAN_ERRADDR_MASK (0x00003FFF)
11181118

11191119
/* Bit definition for Error Report Syndrome Register (RERRSYNR) */
11201120
#define FLEXCAN_RERRSYNR_BE3_MASK (0x80000000)
11211121
#define FLEXCAN_RERRSYNR_SYND3_MASK (0x1F000000)
11221122
#define FLEXCAN_RERRSYNR_SYND3_BIT_NO (24)
1123-
#define FLEXCAN_RERRSYNR_BE2_MASK (0x00800000)
1124-
#define FLEXCAN_RERRSYNR_SYND2_MASK (0x001F0000)
1123+
#define FLEXCAN_RERRSYNR_BE2_MASK (0x00800000)
1124+
#define FLEXCAN_RERRSYNR_SYND2_MASK (0x001F0000)
11251125
#define FLEXCAN_RERRSYNR_SYND2_BIT_NO (16)
11261126
#define FLEXCAN_RERRSYNR_BE1_MASK (0x00008000)
11271127
#define FLEXCAN_RERRSYNR_SYND1_MASK (0x00001F00)
11281128
#define FLEXCAN_RERRSYNR_SYND1_BIT_NO (8)
1129-
#define FLEXCAN_RERRSYNR_BE0_MASK (0x00000080)
1130-
#define FLEXCAN_RERRSYNR_SYND0_MASK (0x0000001F)
1129+
#define FLEXCAN_RERRSYNR_BE0_MASK (0x00000080)
1130+
#define FLEXCAN_RERRSYNR_SYND0_MASK (0x0000001F)
11311131
#define FLEXCAN_RERRSYNR_SYND0_BIT_NO (0)
11321132

11331133
#define FLEXCAN_RERRSYNR_check_BEn_Bit(errsynr,n) (errsynr & FLEXCAN_RERRSYNR_BE##n##_MASK)
@@ -1142,6 +1142,6 @@ typedef volatile uint32_t vuint32_t;
11421142
#define FLEXCAN_ERRSR_FANCEIF_MASK (0x00040000)
11431143
#define FLEXCAN_ERRSR_HANCEIF_MASK (0x00080000)
11441144

1145-
1145+
11461146
/********************************************************************/
11471147
#endif // __KINETIS_FLEXCAN_H

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